drivers/crypto/sunxi-ss/sun4i-ss.h

   1 /*
   2  * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
   3  *
   4  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
   5  *
   6  * Support AES cipher with 128,192,256 bits keysize.
   7  * Support MD5 and SHA1 hash algorithms.
   8  * Support DES and 3DES
   9  *
  10  * You could find the datasheet in Documentation/arm/sunxi/README
  11  *
  12  * Licensed under the GPL-2.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/crypto.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset.h>
  22 #include <crypto/scatterwalk.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <crypto/md5.h>
  27 #include <crypto/skcipher.h>
  28 #include <crypto/sha.h>
  29 #include <crypto/hash.h>
  30 #include <crypto/internal/hash.h>
  31 #include <crypto/internal/skcipher.h>
  32 #include <crypto/aes.h>
  33 #include <crypto/des.h>
  34 #include <crypto/internal/rng.h>
  35
  36 #define SS_CTL            0x00
  37 #define SS_KEY0           0x04
  38 #define SS_KEY1           0x08
  39 #define SS_KEY2           0x0C
  40 #define SS_KEY3           0x10
  41 #define SS_KEY4           0x14
  42 #define SS_KEY5           0x18
  43 #define SS_KEY6           0x1C
  44 #define SS_KEY7           0x20
  45
  46 #define SS_IV0            0x24
  47 #define SS_IV1            0x28
  48 #define SS_IV2            0x2C
  49 #define SS_IV3            0x30
  50
  51 #define SS_FCSR           0x44
  52
  53 #define SS_MD0            0x4C
  54 #define SS_MD1            0x50
  55 #define SS_MD2            0x54
  56 #define SS_MD3            0x58
  57 #define SS_MD4            0x5C
  58
  59 #define SS_RXFIFO         0x200
  60 #define SS_TXFIFO         0x204
  61
  62 /* SS_CTL configuration values */
  63
  64 /* PRNG generator mode - bit 15 */
  65 #define SS_PRNG_ONESHOT         (0 << 15)
  66 #define SS_PRNG_CONTINUE        (1 << 15)
  67
  68 /* IV mode for hash */
  69 #define SS_IV_ARBITRARY         (1 << 14)
  70
  71 /* SS operation mode - bits 12-13 */
  72 #define SS_ECB                  (0 << 12)
  73 #define SS_CBC                  (1 << 12)
  74 #define SS_CTS                  (3 << 12)
  75
  76 /* Counter width for CNT mode - bits 10-11 */
  77 #define SS_CNT_16BITS           (0 << 10)
  78 #define SS_CNT_32BITS           (1 << 10)
  79 #define SS_CNT_64BITS           (2 << 10)
  80
  81 /* Key size for AES - bits 8-9 */
  82 #define SS_AES_128BITS          (0 << 8)
  83 #define SS_AES_192BITS          (1 << 8)
  84 #define SS_AES_256BITS          (2 << 8)
  85
  86 /* Operation direction - bit 7 */
  87 #define SS_ENCRYPTION           (0 << 7)
  88 #define SS_DECRYPTION           (1 << 7)
  89
  90 /* SS Method - bits 4-6 */
  91 #define SS_OP_AES               (0 << 4)
  92 #define SS_OP_DES               (1 << 4)
  93 #define SS_OP_3DES              (2 << 4)
  94 #define SS_OP_SHA1              (3 << 4)
  95 #define SS_OP_MD5               (4 << 4)
  96 #define SS_OP_PRNG              (5 << 4)
  97
  98 /* Data end bit - bit 2 */
  99 #define SS_DATA_END             (1 << 2)
 100
 101 /* PRNG start bit - bit 1 */
 102 #define SS_PRNG_START           (1 << 1)
 103
 104 /* SS Enable bit - bit 0 */
 105 #define SS_DISABLED             (0 << 0)
 106 #define SS_ENABLED              (1 << 0)
 107
 108 /* SS_FCSR configuration values */
 109 /* RX FIFO status - bit 30 */
 110 #define SS_RXFIFO_FREE          (1 << 30)
 111
 112 /* RX FIFO empty spaces - bits 24-29 */
 113 #define SS_RXFIFO_SPACES(val)   (((val) >> 24) & 0x3f)
 114
 115 /* TX FIFO status - bit 22 */
 116 #define SS_TXFIFO_AVAILABLE     (1 << 22)
 117
 118 /* TX FIFO available spaces - bits 16-21 */
 119 #define SS_TXFIFO_SPACES(val)   (((val) >> 16) & 0x3f)
 120
 121 #define SS_RX_MAX       32
 122 #define SS_RX_DEFAULT   SS_RX_MAX
 123 #define SS_TX_MAX       33
 124
 125 #define SS_RXFIFO_EMP_INT_PENDING       (1 << 10)
 126 #define SS_TXFIFO_AVA_INT_PENDING       (1 << 8)
 127 #define SS_RXFIFO_EMP_INT_ENABLE        (1 << 2)
 128 #define SS_TXFIFO_AVA_INT_ENABLE        (1 << 0)
 129
 130 struct sun4i_ss_ctx {
 131         void __iomem *base;
 132         int irq;
 133         struct clk *busclk;
 134         struct clk *ssclk;
 135         struct reset_control *reset;
 136         struct device *dev;
 137         struct resource *res;
 138         spinlock_t slock; /* control the use of the device */
 139 };
 140
 141 struct sun4i_ss_alg_template {
 142         u32 type;
 143         u32 mode;
 144         union {
 145                 struct skcipher_alg crypto;
 146                 struct ahash_alg hash;
 147         } alg;
 148         struct sun4i_ss_ctx *ss;
 149 };
 150
 151 struct sun4i_tfm_ctx {
 152         u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
 153         u32 keylen;
 154         u32 keymode;
 155         struct sun4i_ss_ctx *ss;
 156 };
 157
 158 struct sun4i_cipher_req_ctx {
 159         u32 mode;
 160 };
 161
 162 struct sun4i_req_ctx {
 163         u32 mode;
 164         u64 byte_count; /* number of bytes "uploaded" to the device */
 165         u32 hash[5]; /* for storing SS_IVx register */
 166         char buf[64];
 167         unsigned int len;
 168         int flags;
 169 };
 170
 171 int sun4i_hash_crainit(struct crypto_tfm *tfm);
 172 int sun4i_hash_init(struct ahash_request *areq);
 173 int sun4i_hash_update(struct ahash_request *areq);
 174 int sun4i_hash_final(struct ahash_request *areq);
 175 int sun4i_hash_finup(struct ahash_request *areq);
 176 int sun4i_hash_digest(struct ahash_request *areq);
 177 int sun4i_hash_export_md5(struct ahash_request *areq, void *out);
 178 int sun4i_hash_import_md5(struct ahash_request *areq, const void *in);
 179 int sun4i_hash_export_sha1(struct ahash_request *areq, void *out);
 180 int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in);
 181
 182 int sun4i_ss_cbc_aes_encrypt(struct skcipher_request *areq);
 183 int sun4i_ss_cbc_aes_decrypt(struct skcipher_request *areq);
 184 int sun4i_ss_ecb_aes_encrypt(struct skcipher_request *areq);
 185 int sun4i_ss_ecb_aes_decrypt(struct skcipher_request *areq);
 186
 187 int sun4i_ss_cbc_des_encrypt(struct skcipher_request *areq);
 188 int sun4i_ss_cbc_des_decrypt(struct skcipher_request *areq);
 189 int sun4i_ss_ecb_des_encrypt(struct skcipher_request *areq);
 190 int sun4i_ss_ecb_des_decrypt(struct skcipher_request *areq);
 191
 192 int sun4i_ss_cbc_des3_encrypt(struct skcipher_request *areq);
 193 int sun4i_ss_cbc_des3_decrypt(struct skcipher_request *areq);
 194 int sun4i_ss_ecb_des3_encrypt(struct skcipher_request *areq);
 195 int sun4i_ss_ecb_des3_decrypt(struct skcipher_request *areq);
 196
 197 int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
 198 int sun4i_ss_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
 199                         unsigned int keylen);
 200 int sun4i_ss_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
 201                         unsigned int keylen);
 202 int sun4i_ss_des3_setkey(struct crypto_skcipher *tfm, const u8 *key,
 203                          unsigned int keylen);