drivers/scsi/smartpqi/smartpqi_sis.c

   1 /*
   2  *    driver for Microsemi PQI-based storage controllers
   3  *    Copyright (c) 2016-2017 Microsemi Corporation
   4  *    Copyright (c) 2016 PMC-Sierra, Inc.
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; version 2 of the License.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  14  *
  15  *    Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/pci.h>
  23 #include <scsi/scsi_device.h>
  24 #include <asm/unaligned.h>
  25 #include "smartpqi.h"
  26 #include "smartpqi_sis.h"
  27
  28 /* legacy SIS interface commands */
  29 #define SIS_CMD_GET_ADAPTER_PROPERTIES          0x19
  30 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS        0x1b
  31 #define SIS_CMD_GET_PQI_CAPABILITIES            0x3000
  32
  33 /* for submission of legacy SIS commands */
  34 #define SIS_REENABLE_SIS_MODE                   0x1
  35 #define SIS_ENABLE_MSIX                         0x40
  36 #define SIS_ENABLE_INTX                         0x80
  37 #define SIS_SOFT_RESET                          0x100
  38 #define SIS_TRIGGER_SHUTDOWN                    0x800000
  39 #define SIS_CMD_READY                           0x200
  40 #define SIS_CMD_COMPLETE                        0x1000
  41 #define SIS_CLEAR_CTRL_TO_HOST_DOORBELL         0x1000
  42 #define SIS_CMD_STATUS_SUCCESS                  0x1
  43 #define SIS_CMD_COMPLETE_TIMEOUT_SECS           30
  44 #define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS    10
  45
  46 /* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
  47 #define SIS_EXTENDED_PROPERTIES_SUPPORTED       0x800000
  48 #define SIS_SMARTARRAY_FEATURES_SUPPORTED       0x2
  49 #define SIS_PQI_MODE_SUPPORTED                  0x4
  50 #define SIS_REQUIRED_EXTENDED_PROPERTIES        \
  51         (SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
  52
  53 /* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
  54 #define SIS_BASE_STRUCT_REVISION                9
  55 #define SIS_BASE_STRUCT_ALIGNMENT               16
  56
  57 #define SIS_CTRL_KERNEL_UP                      0x80
  58 #define SIS_CTRL_KERNEL_PANIC                   0x100
  59 #define SIS_CTRL_READY_TIMEOUT_SECS             30
  60 #define SIS_CTRL_READY_RESUME_TIMEOUT_SECS      90
  61 #define SIS_CTRL_READY_POLL_INTERVAL_MSECS      10
  62
  63 #pragma pack(1)
  64
  65 /* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
  66 struct sis_base_struct {
  67         __le32  revision;               /* revision of this structure */
  68         __le32  flags;                  /* reserved */
  69         __le32  error_buffer_paddr_low; /* lower 32 bits of physical memory */
  70                                         /* buffer for PQI error response */
  71                                         /* data */
  72         __le32  error_buffer_paddr_high;        /* upper 32 bits of physical */
  73                                                 /* memory buffer for PQI */
  74                                                 /* error response data */
  75         __le32  error_buffer_element_length;    /* length of each PQI error */
  76                                                 /* response buffer element */
  77                                                 /*   in bytes */
  78         __le32  error_buffer_num_elements;      /* total number of PQI error */
  79                                                 /* response buffers available */
  80 };
  81
  82 #pragma pack()
  83
  84 static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info,
  85         unsigned int timeout_secs)
  86 {
  87         unsigned long timeout;
  88         u32 status;
  89
  90         timeout = (timeout_secs * HZ) + jiffies;
  91
  92         while (1) {
  93                 status = readl(&ctrl_info->registers->sis_firmware_status);
  94                 if (status != ~0) {
  95                         if (status & SIS_CTRL_KERNEL_PANIC) {
  96                                 dev_err(&ctrl_info->pci_dev->dev,
  97                                         "controller is offline: status code 0x%x\n",
  98                                         readl(
  99                                         &ctrl_info->registers->sis_mailbox[7]));
 100                                 return -ENODEV;
 101                         }
 102                         if (status & SIS_CTRL_KERNEL_UP)
 103                                 break;
 104                 }
 105                 if (time_after(jiffies, timeout)) {
 106                         dev_err(&ctrl_info->pci_dev->dev,
 107                                 "controller not ready after %u seconds\n",
 108                                 timeout_secs);
 109                         return -ETIMEDOUT;
 110                 }
 111                 msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS);
 112         }
 113
 114         return 0;
 115 }
 116
 117 int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
 118 {
 119         return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
 120                 SIS_CTRL_READY_TIMEOUT_SECS);
 121 }
 122
 123 int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info)
 124 {
 125         return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
 126                 SIS_CTRL_READY_RESUME_TIMEOUT_SECS);
 127 }
 128
 129 bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
 130 {
 131         bool running;
 132         u32 status;
 133
 134         status = readl(&ctrl_info->registers->sis_firmware_status);
 135
 136         if (status & SIS_CTRL_KERNEL_PANIC)
 137                 running = false;
 138         else
 139                 running = true;
 140
 141         if (!running)
 142                 dev_err(&ctrl_info->pci_dev->dev,
 143                         "controller is offline: status code 0x%x\n",
 144                         readl(&ctrl_info->registers->sis_mailbox[7]));
 145
 146         return running;
 147 }
 148
 149 bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info)
 150 {
 151         return readl(&ctrl_info->registers->sis_firmware_status) &
 152                                 SIS_CTRL_KERNEL_UP;
 153 }
 154
 155 /* used for passing command parameters/results when issuing SIS commands */
 156 struct sis_sync_cmd_params {
 157         u32     mailbox[6];     /* mailboxes 0-5 */
 158 };
 159
 160 static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
 161         u32 cmd, struct sis_sync_cmd_params *params)
 162 {
 163         struct pqi_ctrl_registers __iomem *registers;
 164         unsigned int i;
 165         unsigned long timeout;
 166         u32 doorbell;
 167         u32 cmd_status;
 168
 169         registers = ctrl_info->registers;
 170
 171         /* Write the command to mailbox 0. */
 172         writel(cmd, &registers->sis_mailbox[0]);
 173
 174         /*
 175          * Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
 176          * when sending a command to the controller).
 177          */
 178         for (i = 1; i <= 4; i++)
 179                 writel(params->mailbox[i], &registers->sis_mailbox[i]);
 180
 181         /* Clear the command doorbell. */
 182         writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
 183                 &registers->sis_ctrl_to_host_doorbell_clear);
 184
 185         /* Disable doorbell interrupts by masking all interrupts. */
 186         writel(~0, &registers->sis_interrupt_mask);
 187
 188         /*
 189          * Force the completion of the interrupt mask register write before
 190          * submitting the command.
 191          */
 192         readl(&registers->sis_interrupt_mask);
 193
 194         /* Submit the command to the controller. */
 195         writel(SIS_CMD_READY, &registers->sis_host_to_ctrl_doorbell);
 196
 197         /*
 198          * Poll for command completion.  Note that the call to msleep() is at
 199          * the top of the loop in order to give the controller time to start
 200          * processing the command before we start polling.
 201          */
 202         timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies;
 203         while (1) {
 204                 msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
 205                 doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
 206                 if (doorbell & SIS_CMD_COMPLETE)
 207                         break;
 208                 if (time_after(jiffies, timeout))
 209                         return -ETIMEDOUT;
 210         }
 211
 212         /* Read the command status from mailbox 0. */
 213         cmd_status = readl(&registers->sis_mailbox[0]);
 214         if (cmd_status != SIS_CMD_STATUS_SUCCESS) {
 215                 dev_err(&ctrl_info->pci_dev->dev,
 216                         "SIS command failed for command 0x%x: status = 0x%x\n",
 217                         cmd, cmd_status);
 218                 return -EINVAL;
 219         }
 220
 221         /*
 222          * The command completed successfully, so save the command status and
 223          * read the values returned in mailboxes 1-5.
 224          */
 225         params->mailbox[0] = cmd_status;
 226         for (i = 1; i < ARRAY_SIZE(params->mailbox); i++)
 227                 params->mailbox[i] = readl(&registers->sis_mailbox[i]);
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * This function verifies that we are talking to a controller that speaks PQI.
 234  */
 235
 236 int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
 237 {
 238         int rc;
 239         u32 properties;
 240         u32 extended_properties;
 241         struct sis_sync_cmd_params params;
 242
 243         memset(&params, 0, sizeof(params));
 244
 245         rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
 246                 &params);
 247         if (rc)
 248                 return rc;
 249
 250         properties = params.mailbox[1];
 251
 252         if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED))
 253                 return -ENODEV;
 254
 255         extended_properties = params.mailbox[4];
 256
 257         if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) !=
 258                 SIS_REQUIRED_EXTENDED_PROPERTIES)
 259                 return -ENODEV;
 260
 261         return 0;
 262 }
 263
 264 int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
 265 {
 266         int rc;
 267         struct sis_sync_cmd_params params;
 268
 269         memset(&params, 0, sizeof(params));
 270
 271         rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
 272                 &params);
 273         if (rc)
 274                 return rc;
 275
 276         ctrl_info->max_sg_entries = params.mailbox[1];
 277         ctrl_info->max_transfer_size = params.mailbox[2];
 278         ctrl_info->max_outstanding_requests = params.mailbox[3];
 279         ctrl_info->config_table_offset = params.mailbox[4];
 280         ctrl_info->config_table_length = params.mailbox[5];
 281
 282         return 0;
 283 }
 284
 285 int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
 286 {
 287         int rc;
 288         void *base_struct_unaligned;
 289         struct sis_base_struct *base_struct;
 290         struct sis_sync_cmd_params params;
 291         unsigned long error_buffer_paddr;
 292         dma_addr_t bus_address;
 293
 294         base_struct_unaligned = kzalloc(sizeof(*base_struct)
 295                 + SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL);
 296         if (!base_struct_unaligned)
 297                 return -ENOMEM;
 298
 299         base_struct = PTR_ALIGN(base_struct_unaligned,
 300                 SIS_BASE_STRUCT_ALIGNMENT);
 301         error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
 302
 303         put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision);
 304         put_unaligned_le32(lower_32_bits(error_buffer_paddr),
 305                 &base_struct->error_buffer_paddr_low);
 306         put_unaligned_le32(upper_32_bits(error_buffer_paddr),
 307                 &base_struct->error_buffer_paddr_high);
 308         put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH,
 309                 &base_struct->error_buffer_element_length);
 310         put_unaligned_le32(ctrl_info->max_io_slots,
 311                 &base_struct->error_buffer_num_elements);
 312
 313         bus_address = pci_map_single(ctrl_info->pci_dev, base_struct,
 314                 sizeof(*base_struct), PCI_DMA_TODEVICE);
 315         if (pci_dma_mapping_error(ctrl_info->pci_dev, bus_address)) {
 316                 rc = -ENOMEM;
 317                 goto out;
 318         }
 319
 320         memset(&params, 0, sizeof(params));
 321         params.mailbox[1] = lower_32_bits((u64)bus_address);
 322         params.mailbox[2] = upper_32_bits((u64)bus_address);
 323         params.mailbox[3] = sizeof(*base_struct);
 324
 325         rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
 326                 &params);
 327
 328         pci_unmap_single(ctrl_info->pci_dev, bus_address, sizeof(*base_struct),
 329                 PCI_DMA_TODEVICE);
 330
 331 out:
 332         kfree(base_struct_unaligned);
 333
 334         return rc;
 335 }
 336
 337 #define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS     30
 338
 339 static void sis_wait_for_doorbell_bit_to_clear(
 340         struct pqi_ctrl_info *ctrl_info, u32 bit)
 341 {
 342         u32 doorbell_register;
 343         unsigned long timeout;
 344
 345         timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * HZ) + jiffies;
 346
 347         while (1) {
 348                 doorbell_register =
 349                         readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
 350                 if ((doorbell_register & bit) == 0)
 351                         break;
 352                 if (readl(&ctrl_info->registers->sis_firmware_status) &
 353                         SIS_CTRL_KERNEL_PANIC)
 354                         break;
 355                 if (time_after(jiffies, timeout)) {
 356                         dev_err(&ctrl_info->pci_dev->dev,
 357                                 "doorbell register bit 0x%x not cleared\n",
 358                                 bit);
 359                         break;
 360                 }
 361                 usleep_range(1000, 2000);
 362         }
 363 }
 364
 365 /* Enable MSI-X interrupts on the controller. */
 366
 367 void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
 368 {
 369         u32 doorbell_register;
 370
 371         doorbell_register =
 372                 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
 373         doorbell_register |= SIS_ENABLE_MSIX;
 374
 375         writel(doorbell_register,
 376                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 377
 378         sis_wait_for_doorbell_bit_to_clear(ctrl_info, SIS_ENABLE_MSIX);
 379 }
 380
 381 /* Disable MSI-X interrupts on the controller. */
 382
 383 void sis_disable_msix(struct pqi_ctrl_info *ctrl_info)
 384 {
 385         u32 doorbell_register;
 386
 387         doorbell_register =
 388                 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
 389         doorbell_register &= ~SIS_ENABLE_MSIX;
 390
 391         writel(doorbell_register,
 392                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 393 }
 394
 395 void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
 396 {
 397         u32 doorbell_register;
 398
 399         doorbell_register =
 400                 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
 401         doorbell_register |= SIS_ENABLE_INTX;
 402
 403         writel(doorbell_register,
 404                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 405
 406         sis_wait_for_doorbell_bit_to_clear(ctrl_info, SIS_ENABLE_INTX);
 407 }
 408
 409 void sis_disable_intx(struct pqi_ctrl_info *ctrl_info)
 410 {
 411         u32 doorbell_register;
 412
 413         doorbell_register =
 414                 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
 415         doorbell_register &= ~SIS_ENABLE_INTX;
 416
 417         writel(doorbell_register,
 418                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 419 }
 420
 421 void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
 422 {
 423         writel(SIS_SOFT_RESET,
 424                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 425 }
 426
 427 void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info)
 428 {
 429         if (readl(&ctrl_info->registers->sis_firmware_status) &
 430                 SIS_CTRL_KERNEL_PANIC)
 431                 return;
 432
 433         writel(SIS_TRIGGER_SHUTDOWN,
 434                 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
 435 }
 436
 437 #define SIS_MODE_READY_TIMEOUT_SECS     30
 438
 439 int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
 440 {
 441         int rc;
 442         unsigned long timeout;
 443         struct pqi_ctrl_registers __iomem *registers;
 444         u32 doorbell;
 445
 446         registers = ctrl_info->registers;
 447
 448         writel(SIS_REENABLE_SIS_MODE,
 449                 &registers->sis_host_to_ctrl_doorbell);
 450
 451         rc = 0;
 452         timeout = (SIS_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
 453
 454         while (1) {
 455                 doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
 456                 if ((doorbell & SIS_REENABLE_SIS_MODE) == 0)
 457                         break;
 458                 if (time_after(jiffies, timeout)) {
 459                         rc = -ETIMEDOUT;
 460                         break;
 461                 }
 462         }
 463
 464         if (rc)
 465                 dev_err(&ctrl_info->pci_dev->dev,
 466                         "re-enabling SIS mode failed\n");
 467
 468         return rc;
 469 }
 470
 471 void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
 472 {
 473         writel(value, &ctrl_info->registers->sis_driver_scratch);
 474 }
 475
 476 u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
 477 {
 478         return readl(&ctrl_info->registers->sis_driver_scratch);
 479 }
 480
 481 static void __attribute__((unused)) verify_structures(void)
 482 {
 483         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 484                 revision) != 0x0);
 485         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 486                 flags) != 0x4);
 487         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 488                 error_buffer_paddr_low) != 0x8);
 489         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 490                 error_buffer_paddr_high) != 0xc);
 491         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 492                 error_buffer_element_length) != 0x10);
 493         BUILD_BUG_ON(offsetof(struct sis_base_struct,
 494                 error_buffer_num_elements) != 0x14);
 495         BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18);
 496 }