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USB: SERIAL CP2101 add device IDs
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic3x.c
blob5f9abb199435b35e82d99d7603e11f2338556080
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48
49 #include "tlv320aic3x.h"
50
51 #define AUDIO_NAME "aic3x"
52 #define AIC3X_VERSION "0.2"
53
54 /* codec private data */
55 struct aic3x_priv {
56 unsigned int sysclk;
57 int master;
58 };
59
60 /*
61 * AIC3X register cache
62 * We can't read the AIC3X register space when we are
63 * using 2 wire for device control, so we cache them instead.
64 * There is no point in caching the reset register
65 */
66 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
67 0x00, 0x00, 0x00, 0x10, /* 0 */
68 0x04, 0x00, 0x00, 0x00, /* 4 */
69 0x00, 0x00, 0x00, 0x01, /* 8 */
70 0x00, 0x00, 0x00, 0x80, /* 12 */
71 0x80, 0xff, 0xff, 0x78, /* 16 */
72 0x78, 0x78, 0x78, 0x78, /* 20 */
73 0x78, 0x00, 0x00, 0xfe, /* 24 */
74 0x00, 0x00, 0xfe, 0x00, /* 28 */
75 0x18, 0x18, 0x00, 0x00, /* 32 */
76 0x00, 0x00, 0x00, 0x00, /* 36 */
77 0x00, 0x00, 0x00, 0x80, /* 40 */
78 0x80, 0x00, 0x00, 0x00, /* 44 */
79 0x00, 0x00, 0x00, 0x04, /* 48 */
80 0x00, 0x00, 0x00, 0x00, /* 52 */
81 0x00, 0x00, 0x04, 0x00, /* 56 */
82 0x00, 0x00, 0x00, 0x00, /* 60 */
83 0x00, 0x04, 0x00, 0x00, /* 64 */
84 0x00, 0x00, 0x00, 0x00, /* 68 */
85 0x04, 0x00, 0x00, 0x00, /* 72 */
86 0x00, 0x00, 0x00, 0x00, /* 76 */
87 0x00, 0x00, 0x00, 0x00, /* 80 */
88 0x00, 0x00, 0x00, 0x00, /* 84 */
89 0x00, 0x00, 0x00, 0x00, /* 88 */
90 0x00, 0x00, 0x00, 0x00, /* 92 */
91 0x00, 0x00, 0x00, 0x00, /* 96 */
92 0x00, 0x00, 0x02, /* 100 */
93 };
94
95 /*
96 * read aic3x register cache
97 */
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
99 unsigned int reg)
100 {
101 u8 *cache = codec->reg_cache;
102 if (reg >= AIC3X_CACHEREGNUM)
103 return -1;
104 return cache[reg];
105 }
106
107 /*
108 * write aic3x register cache
109 */
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
111 u8 reg, u8 value)
112 {
113 u8 *cache = codec->reg_cache;
114 if (reg >= AIC3X_CACHEREGNUM)
115 return;
116 cache[reg] = value;
117 }
118
119 /*
120 * write to the aic3x register space
121 */
122 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
123 unsigned int value)
124 {
125 u8 data[2];
126
127 /* data is
128 * D15..D8 aic3x register offset
129 * D7...D0 register data
130 */
131 data[0] = reg & 0xff;
132 data[1] = value & 0xff;
133
134 aic3x_write_reg_cache(codec, data[0], data[1]);
135 if (codec->hw_write(codec->control_data, data, 2) == 2)
136 return 0;
137 else
138 return -EIO;
139 }
140
141 /*
142 * read from the aic3x register space
143 */
144 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
145 u8 *value)
146 {
147 *value = reg & 0xff;
148 if (codec->hw_read(codec->control_data, value, 1) != 1)
149 return -EIO;
150
151 aic3x_write_reg_cache(codec, reg, *value);
152 return 0;
153 }
154
155 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
157 .info = snd_soc_info_volsw, \
158 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
159 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
160
161 /*
162 * All input lines are connected when !0xf and disconnected with 0xf bit field,
163 * so we have to use specific dapm_put call for input mixer
164 */
165 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
166 struct snd_ctl_elem_value *ucontrol)
167 {
168 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
169 int reg = kcontrol->private_value & 0xff;
170 int shift = (kcontrol->private_value >> 8) & 0x0f;
171 int mask = (kcontrol->private_value >> 16) & 0xff;
172 int invert = (kcontrol->private_value >> 24) & 0x01;
173 unsigned short val, val_mask;
174 int ret;
175 struct snd_soc_dapm_path *path;
176 int found = 0;
177
178 val = (ucontrol->value.integer.value[0] & mask);
179
180 mask = 0xf;
181 if (val)
182 val = mask;
183
184 if (invert)
185 val = mask - val;
186 val_mask = mask << shift;
187 val = val << shift;
188
189 mutex_lock(&widget->codec->mutex);
190
191 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
192 /* find dapm widget path assoc with kcontrol */
193 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
194 if (path->kcontrol != kcontrol)
195 continue;
196
197 /* found, now check type */
198 found = 1;
199 if (val)
200 /* new connection */
201 path->connect = invert ? 0 : 1;
202 else
203 /* old connection must be powered down */
204 path->connect = invert ? 1 : 0;
205 break;
206 }
207
208 if (found)
209 snd_soc_dapm_sync(widget->codec);
210 }
211
212 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
213
214 mutex_unlock(&widget->codec->mutex);
215 return ret;
216 }
217
218 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
219 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
220 static const char *aic3x_left_hpcom_mux[] =
221 { "differential of HPLOUT", "constant VCM", "single-ended" };
222 static const char *aic3x_right_hpcom_mux[] =
223 { "differential of HPROUT", "constant VCM", "single-ended",
224 "differential of HPLCOM", "external feedback" };
225 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
226 static const char *aic3x_adc_hpf[] =
227 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
228
229 #define LDAC_ENUM 0
230 #define RDAC_ENUM 1
231 #define LHPCOM_ENUM 2
232 #define RHPCOM_ENUM 3
233 #define LINE1L_ENUM 4
234 #define LINE1R_ENUM 5
235 #define LINE2L_ENUM 6
236 #define LINE2R_ENUM 7
237 #define ADC_HPF_ENUM 8
238
239 static const struct soc_enum aic3x_enum[] = {
240 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
241 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
242 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
243 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
244 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
245 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
249 };
250
251 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
252 /* Output */
253 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
254
255 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
256 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
257 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
258 0x01, 0),
259 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
260 PGAR_2_RLOPM_VOL, 0, 0x7f, 1),
261 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
262 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
263
264 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
265 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
266 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
267 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
268 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
269 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
270 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
271
272 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
273 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
274 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
275 0x01, 0),
276 SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
277 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
278 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
279 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
280
281 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
282 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
283 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
284 0x01, 0),
285 SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
286 PGAR_2_HPRCOM_VOL, 0, 0x7f, 1),
287 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
288 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
289
290 /*
291 * Note: enable Automatic input Gain Controller with care. It can
292 * adjust PGA to max value when ADC is on and will never go back.
293 */
294 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
295
296 /* Input */
297 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
298 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
299
300 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
301 };
302
303 /* add non dapm controls */
304 static int aic3x_add_controls(struct snd_soc_codec *codec)
305 {
306 int err, i;
307
308 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
309 err = snd_ctl_add(codec->card,
310 snd_soc_cnew(&aic3x_snd_controls[i],
311 codec, NULL));
312 if (err < 0)
313 return err;
314 }
315
316 return 0;
317 }
318
319 /* Left DAC Mux */
320 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
321 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
322
323 /* Right DAC Mux */
324 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
325 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
326
327 /* Left HPCOM Mux */
328 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
329 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
330
331 /* Right HPCOM Mux */
332 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
333 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
334
335 /* Left DAC_L1 Mixer */
336 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
337 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
338 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
339 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
340 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
341 };
342
343 /* Right DAC_R1 Mixer */
344 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
345 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
346 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
347 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
348 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
349 };
350
351 /* Left PGA Mixer */
352 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
353 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
354 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
355 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
356 };
357
358 /* Right PGA Mixer */
359 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
360 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
361 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
362 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
363 };
364
365 /* Left Line1 Mux */
366 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
367 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
368
369 /* Right Line1 Mux */
370 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
371 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
372
373 /* Left Line2 Mux */
374 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
375 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
376
377 /* Right Line2 Mux */
378 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
379 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
380
381 /* Left PGA Bypass Mixer */
382 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
383 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
384 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
385 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
386 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
387 };
388
389 /* Right PGA Bypass Mixer */
390 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
391 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
395 };
396
397 /* Left Line2 Bypass Mixer */
398 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
399 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
400 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
401 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
403 };
404
405 /* Right Line2 Bypass Mixer */
406 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
407 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
410 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
411 };
412
413 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
414 /* Left DAC to Left Outputs */
415 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
416 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
417 &aic3x_left_dac_mux_controls),
418 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
419 &aic3x_left_dac_mixer_controls[0],
420 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
421 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
422 &aic3x_left_hpcom_mux_controls),
423 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
424 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
425 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
426
427 /* Right DAC to Right Outputs */
428 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
429 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
430 &aic3x_right_dac_mux_controls),
431 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
432 &aic3x_right_dac_mixer_controls[0],
433 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
434 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
435 &aic3x_right_hpcom_mux_controls),
436 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
437 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
438 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
439
440 /* Mono Output */
441 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
442
443 /* Left Inputs to Left ADC */
444 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
445 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
446 &aic3x_left_pga_mixer_controls[0],
447 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
448 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
449 &aic3x_left_line1_mux_controls),
450 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
451 &aic3x_left_line2_mux_controls),
452
453 /* Right Inputs to Right ADC */
454 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
455 LINE1R_2_RADC_CTRL, 2, 0),
456 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
457 &aic3x_right_pga_mixer_controls[0],
458 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
459 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
460 &aic3x_right_line1_mux_controls),
461 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
462 &aic3x_right_line2_mux_controls),
463
464 /*
465 * Not a real mic bias widget but similar function. This is for dynamic
466 * control of GPIO1 digital mic modulator clock output function when
467 * using digital mic.
468 */
469 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
470 AIC3X_GPIO1_REG, 4, 0xf,
471 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
472 AIC3X_GPIO1_FUNC_DISABLED),
473
474 /*
475 * Also similar function like mic bias. Selects digital mic with
476 * configurable oversampling rate instead of ADC converter.
477 */
478 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
479 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
480 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
481 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
482 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
483 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
484
485 /* Mic Bias */
486 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
487 MICBIAS_CTRL, 6, 3, 1, 0),
488 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
489 MICBIAS_CTRL, 6, 3, 2, 0),
490 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
491 MICBIAS_CTRL, 6, 3, 3, 0),
492
493 /* Left PGA to Left Output bypass */
494 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
495 &aic3x_left_pga_bp_mixer_controls[0],
496 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
497
498 /* Right PGA to Right Output bypass */
499 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
500 &aic3x_right_pga_bp_mixer_controls[0],
501 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
502
503 /* Left Line2 to Left Output bypass */
504 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
505 &aic3x_left_line2_bp_mixer_controls[0],
506 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
507
508 /* Right Line2 to Right Output bypass */
509 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
510 &aic3x_right_line2_bp_mixer_controls[0],
511 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
512
513 SND_SOC_DAPM_OUTPUT("LLOUT"),
514 SND_SOC_DAPM_OUTPUT("RLOUT"),
515 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
516 SND_SOC_DAPM_OUTPUT("HPLOUT"),
517 SND_SOC_DAPM_OUTPUT("HPROUT"),
518 SND_SOC_DAPM_OUTPUT("HPLCOM"),
519 SND_SOC_DAPM_OUTPUT("HPRCOM"),
520
521 SND_SOC_DAPM_INPUT("MIC3L"),
522 SND_SOC_DAPM_INPUT("MIC3R"),
523 SND_SOC_DAPM_INPUT("LINE1L"),
524 SND_SOC_DAPM_INPUT("LINE1R"),
525 SND_SOC_DAPM_INPUT("LINE2L"),
526 SND_SOC_DAPM_INPUT("LINE2R"),
527 };
528
529 static const struct snd_soc_dapm_route intercon[] = {
530 /* Left Output */
531 {"Left DAC Mux", "DAC_L1", "Left DAC"},
532 {"Left DAC Mux", "DAC_L2", "Left DAC"},
533 {"Left DAC Mux", "DAC_L3", "Left DAC"},
534
535 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
536 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
537 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
538 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
539 {"Left Line Out", NULL, "Left DAC Mux"},
540 {"Left HP Out", NULL, "Left DAC Mux"},
541
542 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
543 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
544 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
545
546 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
547 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
548 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
549 {"Left HP Com", NULL, "Left HPCOM Mux"},
550
551 {"LLOUT", NULL, "Left Line Out"},
552 {"LLOUT", NULL, "Left Line Out"},
553 {"HPLOUT", NULL, "Left HP Out"},
554 {"HPLCOM", NULL, "Left HP Com"},
555
556 /* Right Output */
557 {"Right DAC Mux", "DAC_R1", "Right DAC"},
558 {"Right DAC Mux", "DAC_R2", "Right DAC"},
559 {"Right DAC Mux", "DAC_R3", "Right DAC"},
560
561 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
562 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
563 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
564 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
565 {"Right Line Out", NULL, "Right DAC Mux"},
566 {"Right HP Out", NULL, "Right DAC Mux"},
567
568 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
569 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
570 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
571 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
572 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
573
574 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
575 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
576 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
577 {"Right HP Com", NULL, "Right HPCOM Mux"},
578
579 {"RLOUT", NULL, "Right Line Out"},
580 {"RLOUT", NULL, "Right Line Out"},
581 {"HPROUT", NULL, "Right HP Out"},
582 {"HPRCOM", NULL, "Right HP Com"},
583
584 /* Mono Output */
585 {"MONO_LOUT", NULL, "Mono Out"},
586 {"MONO_LOUT", NULL, "Mono Out"},
587
588 /* Left Input */
589 {"Left Line1L Mux", "single-ended", "LINE1L"},
590 {"Left Line1L Mux", "differential", "LINE1L"},
591
592 {"Left Line2L Mux", "single-ended", "LINE2L"},
593 {"Left Line2L Mux", "differential", "LINE2L"},
594
595 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
596 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
597 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
598
599 {"Left ADC", NULL, "Left PGA Mixer"},
600 {"Left ADC", NULL, "GPIO1 dmic modclk"},
601
602 /* Right Input */
603 {"Right Line1R Mux", "single-ended", "LINE1R"},
604 {"Right Line1R Mux", "differential", "LINE1R"},
605
606 {"Right Line2R Mux", "single-ended", "LINE2R"},
607 {"Right Line2R Mux", "differential", "LINE2R"},
608
609 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
610 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
611 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
612
613 {"Right ADC", NULL, "Right PGA Mixer"},
614 {"Right ADC", NULL, "GPIO1 dmic modclk"},
615
616 /* Left PGA Bypass */
617 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
618 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
619 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
620 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
621
622 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
623 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
624 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
625
626 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
627 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
628 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
629
630 /* Right PGA Bypass */
631 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
632 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
633 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
634 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
635
636 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
637 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
638 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
639 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
640 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
641
642 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
643 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
644 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
645
646 /* Left Line2 Bypass */
647 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
648 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
649 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
650 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
651
652 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
653 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
654 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
655
656 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
657 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
658 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
659
660 /* Right Line2 Bypass */
661 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
662 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
663 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
664 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
665
666 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
667 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
668 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
669 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
670 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
671
672 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
673 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
674 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
675
676 /*
677 * Logical path between digital mic enable and GPIO1 modulator clock
678 * output function
679 */
680 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
681 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
682 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
683 };
684
685 static int aic3x_add_widgets(struct snd_soc_codec *codec)
686 {
687 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
688 ARRAY_SIZE(aic3x_dapm_widgets));
689
690 /* set up audio path interconnects */
691 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
692
693 snd_soc_dapm_new_widgets(codec);
694 return 0;
695 }
696
697 static int aic3x_hw_params(struct snd_pcm_substream *substream,
698 struct snd_pcm_hw_params *params)
699 {
700 struct snd_soc_pcm_runtime *rtd = substream->private_data;
701 struct snd_soc_device *socdev = rtd->socdev;
702 struct snd_soc_codec *codec = socdev->codec;
703 struct aic3x_priv *aic3x = codec->private_data;
704 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
705 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
706 u16 pll_d = 1;
707
708 /* select data word length */
709 data =
710 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
711 switch (params_format(params)) {
712 case SNDRV_PCM_FORMAT_S16_LE:
713 break;
714 case SNDRV_PCM_FORMAT_S20_3LE:
715 data |= (0x01 << 4);
716 break;
717 case SNDRV_PCM_FORMAT_S24_LE:
718 data |= (0x02 << 4);
719 break;
720 case SNDRV_PCM_FORMAT_S32_LE:
721 data |= (0x03 << 4);
722 break;
723 }
724 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
725
726 /* Fsref can be 44100 or 48000 */
727 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
728
729 /* Try to find a value for Q which allows us to bypass the PLL and
730 * generate CODEC_CLK directly. */
731 for (pll_q = 2; pll_q < 18; pll_q++)
732 if (aic3x->sysclk / (128 * pll_q) == fsref) {
733 bypass_pll = 1;
734 break;
735 }
736
737 if (bypass_pll) {
738 pll_q &= 0xf;
739 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
740 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
741 } else
742 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
743
744 /* Route Left DAC to left channel input and
745 * right DAC to right channel input */
746 data = (LDAC2LCH | RDAC2RCH);
747 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
748 if (params_rate(params) >= 64000)
749 data |= DUAL_RATE_MODE;
750 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
751
752 /* codec sample rate select */
753 data = (fsref * 20) / params_rate(params);
754 if (params_rate(params) < 64000)
755 data /= 2;
756 data /= 5;
757 data -= 2;
758 data |= (data << 4);
759 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
760
761 if (bypass_pll)
762 return 0;
763
764 /* Use PLL
765 * find an apropriate setup for j, d, r and p by iterating over
766 * p and r - j and d are calculated for each fraction.
767 * Up to 128 values are probed, the closest one wins the game.
768 * The sysclk is divided by 1000 to prevent integer overflows.
769 */
770 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
771
772 for (r = 1; r <= 16; r++)
773 for (p = 1; p <= 8; p++) {
774 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
775 u8 j = tmp / 10000;
776 u16 d = tmp % 10000;
777
778 if (j > 63)
779 continue;
780
781 if (d != 0 && aic3x->sysclk < 10000000)
782 continue;
783
784 /* This is actually 1000 * ((j + (d/10000)) * r) / p
785 * The term had to be converted to get rid of the
786 * division by 10000 */
787 clk = ((10000 * j * r) + (d * r)) / (10 * p);
788
789 /* check whether this values get closer than the best
790 * ones we had before */
791 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
792 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
793 last_clk = clk;
794 }
795
796 /* Early exit for exact matches */
797 if (clk == codec_clk)
798 break;
799 }
800
801 if (last_clk == 0) {
802 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
803 return -EINVAL;
804 }
805
806 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
807 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
808 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
809 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
810 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
811 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
812 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
813
814 return 0;
815 }
816
817 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
818 {
819 struct snd_soc_codec *codec = dai->codec;
820 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
821 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
822
823 if (mute) {
824 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
825 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
826 } else {
827 aic3x_write(codec, LDAC_VOL, ldac_reg);
828 aic3x_write(codec, RDAC_VOL, rdac_reg);
829 }
830
831 return 0;
832 }
833
834 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
835 int clk_id, unsigned int freq, int dir)
836 {
837 struct snd_soc_codec *codec = codec_dai->codec;
838 struct aic3x_priv *aic3x = codec->private_data;
839
840 aic3x->sysclk = freq;
841 return 0;
842 }
843
844 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
845 unsigned int fmt)
846 {
847 struct snd_soc_codec *codec = codec_dai->codec;
848 struct aic3x_priv *aic3x = codec->private_data;
849 u8 iface_areg, iface_breg;
850
851 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
852 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
853
854 /* set master/slave audio interface */
855 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
856 case SND_SOC_DAIFMT_CBM_CFM:
857 aic3x->master = 1;
858 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
859 break;
860 case SND_SOC_DAIFMT_CBS_CFS:
861 aic3x->master = 0;
862 break;
863 default:
864 return -EINVAL;
865 }
866
867 /* interface format */
868 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
869 case SND_SOC_DAIFMT_I2S:
870 break;
871 case SND_SOC_DAIFMT_DSP_A:
872 iface_breg |= (0x01 << 6);
873 break;
874 case SND_SOC_DAIFMT_RIGHT_J:
875 iface_breg |= (0x02 << 6);
876 break;
877 case SND_SOC_DAIFMT_LEFT_J:
878 iface_breg |= (0x03 << 6);
879 break;
880 default:
881 return -EINVAL;
882 }
883
884 /* set iface */
885 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
886 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
887
888 return 0;
889 }
890
891 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
892 enum snd_soc_bias_level level)
893 {
894 struct aic3x_priv *aic3x = codec->private_data;
895 u8 reg;
896
897 switch (level) {
898 case SND_SOC_BIAS_ON:
899 /* all power is driven by DAPM system */
900 if (aic3x->master) {
901 /* enable pll */
902 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
903 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
904 reg | PLL_ENABLE);
905 }
906 break;
907 case SND_SOC_BIAS_PREPARE:
908 break;
909 case SND_SOC_BIAS_STANDBY:
910 /*
911 * all power is driven by DAPM system,
912 * so output power is safe if bypass was set
913 */
914 if (aic3x->master) {
915 /* disable pll */
916 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
917 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
918 reg & ~PLL_ENABLE);
919 }
920 break;
921 case SND_SOC_BIAS_OFF:
922 /* force all power off */
923 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
924 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
925 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
926 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
927
928 reg = aic3x_read_reg_cache(codec, DAC_PWR);
929 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
930
931 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
932 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
933 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
934 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
935
936 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
937 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
938 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
939 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
940
941 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
942 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
943
944 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
945 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
946 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
947 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
948
949 if (aic3x->master) {
950 /* disable pll */
951 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
952 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
953 reg & ~PLL_ENABLE);
954 }
955 break;
956 }
957 codec->bias_level = level;
958
959 return 0;
960 }
961
962 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
963 {
964 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
965 u8 bit = gpio ? 3: 0;
966 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
967 aic3x_write(codec, reg, val | (!!state << bit));
968 }
969 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
970
971 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
972 {
973 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
974 u8 val, bit = gpio ? 2: 1;
975
976 aic3x_read(codec, reg, &val);
977 return (val >> bit) & 1;
978 }
979 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
980
981 int aic3x_headset_detected(struct snd_soc_codec *codec)
982 {
983 u8 val;
984 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
985 return (val >> 2) & 1;
986 }
987 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
988
989 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
990 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
991 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
992
993 struct snd_soc_dai aic3x_dai = {
994 .name = "aic3x",
995 .playback = {
996 .stream_name = "Playback",
997 .channels_min = 1,
998 .channels_max = 2,
999 .rates = AIC3X_RATES,
1000 .formats = AIC3X_FORMATS,},
1001 .capture = {
1002 .stream_name = "Capture",
1003 .channels_min = 1,
1004 .channels_max = 2,
1005 .rates = AIC3X_RATES,
1006 .formats = AIC3X_FORMATS,},
1007 .ops = {
1008 .hw_params = aic3x_hw_params,
1009 },
1010 .dai_ops = {
1011 .digital_mute = aic3x_mute,
1012 .set_sysclk = aic3x_set_dai_sysclk,
1013 .set_fmt = aic3x_set_dai_fmt,
1014 }
1015 };
1016 EXPORT_SYMBOL_GPL(aic3x_dai);
1017
1018 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1019 {
1020 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1021 struct snd_soc_codec *codec = socdev->codec;
1022
1023 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1024
1025 return 0;
1026 }
1027
1028 static int aic3x_resume(struct platform_device *pdev)
1029 {
1030 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1031 struct snd_soc_codec *codec = socdev->codec;
1032 int i;
1033 u8 data[2];
1034 u8 *cache = codec->reg_cache;
1035
1036 /* Sync reg_cache with the hardware */
1037 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1038 data[0] = i;
1039 data[1] = cache[i];
1040 codec->hw_write(codec->control_data, data, 2);
1041 }
1042
1043 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1044
1045 return 0;
1046 }
1047
1048 /*
1049 * initialise the AIC3X driver
1050 * register the mixer and dsp interfaces with the kernel
1051 */
1052 static int aic3x_init(struct snd_soc_device *socdev)
1053 {
1054 struct snd_soc_codec *codec = socdev->codec;
1055 struct aic3x_setup_data *setup = socdev->codec_data;
1056 int reg, ret = 0;
1057
1058 codec->name = "aic3x";
1059 codec->owner = THIS_MODULE;
1060 codec->read = aic3x_read_reg_cache;
1061 codec->write = aic3x_write;
1062 codec->set_bias_level = aic3x_set_bias_level;
1063 codec->dai = &aic3x_dai;
1064 codec->num_dai = 1;
1065 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1066 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1067 if (codec->reg_cache == NULL)
1068 return -ENOMEM;
1069
1070 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1071 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1072
1073 /* register pcms */
1074 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1075 if (ret < 0) {
1076 printk(KERN_ERR "aic3x: failed to create pcms\n");
1077 goto pcm_err;
1078 }
1079
1080 /* DAC default volume and mute */
1081 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1082 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1083
1084 /* DAC to HP default volume and route to Output mixer */
1085 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1086 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1087 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1088 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1089 /* DAC to Line Out default volume and route to Output mixer */
1090 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1091 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1092 /* DAC to Mono Line Out default volume and route to Output mixer */
1093 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1094 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1095
1096 /* unmute all outputs */
1097 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1098 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1099 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1100 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1101 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1102 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1103 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1104 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1105 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1106 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1107 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1108 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1109 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1110 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1111
1112 /* ADC default volume and unmute */
1113 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1114 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1115 /* By default route Line1 to ADC PGA mixer */
1116 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1117 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1118
1119 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1120 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1121 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1122 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1123 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1124 /* PGA to Line Out default volume, disconnect from Output Mixer */
1125 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1126 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1127 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1128 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1129 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1130
1131 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1132 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1133 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1134 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1135 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1136 /* Line2 Line Out default volume, disconnect from Output Mixer */
1137 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1138 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1139 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1140 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1141 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1142
1143 /* off, with power on */
1144 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1145
1146 /* setup GPIO functions */
1147 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1148 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1149
1150 aic3x_add_controls(codec);
1151 aic3x_add_widgets(codec);
1152 ret = snd_soc_register_card(socdev);
1153 if (ret < 0) {
1154 printk(KERN_ERR "aic3x: failed to register card\n");
1155 goto card_err;
1156 }
1157
1158 return ret;
1159
1160 card_err:
1161 snd_soc_free_pcms(socdev);
1162 snd_soc_dapm_free(socdev);
1163 pcm_err:
1164 kfree(codec->reg_cache);
1165 return ret;
1166 }
1167
1168 static struct snd_soc_device *aic3x_socdev;
1169
1170 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1171 /*
1172 * AIC3X 2 wire address can be up to 4 devices with device addresses
1173 * 0x18, 0x19, 0x1A, 0x1B
1174 */
1175 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1176
1177 /* Magic definition of all other variables and things */
1178 I2C_CLIENT_INSMOD;
1179
1180 static struct i2c_driver aic3x_i2c_driver;
1181 static struct i2c_client client_template;
1182
1183 /*
1184 * If the i2c layer weren't so broken, we could pass this kind of data
1185 * around
1186 */
1187 static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1188 {
1189 struct snd_soc_device *socdev = aic3x_socdev;
1190 struct aic3x_setup_data *setup = socdev->codec_data;
1191 struct snd_soc_codec *codec = socdev->codec;
1192 struct i2c_client *i2c;
1193 int ret;
1194
1195 if (addr != setup->i2c_address)
1196 return -ENODEV;
1197
1198 client_template.adapter = adap;
1199 client_template.addr = addr;
1200
1201 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1202 if (i2c == NULL)
1203 return -ENOMEM;
1204
1205 i2c_set_clientdata(i2c, codec);
1206 codec->control_data = i2c;
1207
1208 ret = i2c_attach_client(i2c);
1209 if (ret < 0) {
1210 printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n",
1211 addr);
1212 goto err;
1213 }
1214
1215 ret = aic3x_init(socdev);
1216 if (ret < 0) {
1217 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1218 goto err;
1219 }
1220 return ret;
1221
1222 err:
1223 kfree(i2c);
1224 return ret;
1225 }
1226
1227 static int aic3x_i2c_detach(struct i2c_client *client)
1228 {
1229 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1230 i2c_detach_client(client);
1231 kfree(codec->reg_cache);
1232 kfree(client);
1233 return 0;
1234 }
1235
1236 static int aic3x_i2c_attach(struct i2c_adapter *adap)
1237 {
1238 return i2c_probe(adap, &addr_data, aic3x_codec_probe);
1239 }
1240
1241 /* machine i2c codec control layer */
1242 static struct i2c_driver aic3x_i2c_driver = {
1243 .driver = {
1244 .name = "aic3x I2C Codec",
1245 .owner = THIS_MODULE,
1246 },
1247 .attach_adapter = aic3x_i2c_attach,
1248 .detach_client = aic3x_i2c_detach,
1249 };
1250
1251 static struct i2c_client client_template = {
1252 .name = "AIC3X",
1253 .driver = &aic3x_i2c_driver,
1254 };
1255
1256 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1257 {
1258 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1259 return (len == 1);
1260 }
1261 #endif
1262
1263 static int aic3x_probe(struct platform_device *pdev)
1264 {
1265 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1266 struct aic3x_setup_data *setup;
1267 struct snd_soc_codec *codec;
1268 struct aic3x_priv *aic3x;
1269 int ret = 0;
1270
1271 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1272
1273 setup = socdev->codec_data;
1274 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1275 if (codec == NULL)
1276 return -ENOMEM;
1277
1278 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1279 if (aic3x == NULL) {
1280 kfree(codec);
1281 return -ENOMEM;
1282 }
1283
1284 codec->private_data = aic3x;
1285 socdev->codec = codec;
1286 mutex_init(&codec->mutex);
1287 INIT_LIST_HEAD(&codec->dapm_widgets);
1288 INIT_LIST_HEAD(&codec->dapm_paths);
1289
1290 aic3x_socdev = socdev;
1291 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1292 if (setup->i2c_address) {
1293 normal_i2c[0] = setup->i2c_address;
1294 codec->hw_write = (hw_write_t) i2c_master_send;
1295 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1296 ret = i2c_add_driver(&aic3x_i2c_driver);
1297 if (ret != 0)
1298 printk(KERN_ERR "can't add i2c driver");
1299 }
1300 #else
1301 /* Add other interfaces here */
1302 #endif
1303
1304 if (ret != 0) {
1305 kfree(codec->private_data);
1306 kfree(codec);
1307 }
1308 return ret;
1309 }
1310
1311 static int aic3x_remove(struct platform_device *pdev)
1312 {
1313 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1314 struct snd_soc_codec *codec = socdev->codec;
1315
1316 /* power down chip */
1317 if (codec->control_data)
1318 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1319
1320 snd_soc_free_pcms(socdev);
1321 snd_soc_dapm_free(socdev);
1322 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1323 i2c_del_driver(&aic3x_i2c_driver);
1324 #endif
1325 kfree(codec->private_data);
1326 kfree(codec);
1327
1328 return 0;
1329 }
1330
1331 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1332 .probe = aic3x_probe,
1333 .remove = aic3x_remove,
1334 .suspend = aic3x_suspend,
1335 .resume = aic3x_resume,
1336 };
1337 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1338
1339 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1340 MODULE_AUTHOR("Vladimir Barinov");
1341 MODULE_LICENSE("GPL");
Linux with added FPC-III support