?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / gpu / drm / msm / dsi / pll / dsi_pll_14nm.c
blob0e18cddd6f22e0eb4bba70ff4ac52af312c9b9d4
1 /*
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16
17 #include "dsi_pll.h"
18 #include "dsi.xml.h"
19
20 /*
21 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 *
23 * dsi0n1_postdiv_clk
24 * |
25 * |
26 * +----+ | +----+
27 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
28 * +----+ | +----+
29 * | dsi0n1_postdivby2_clk
30 * | +----+ |
31 * o---| /2 |--o--|\
32 * | +----+ | \ +----+
33 * | | |--| n2 |-- dsi0pll
34 * o--------------| / +----+
35 * |/
36 */
37
38 #define POLL_MAX_READS 15
39 #define POLL_TIMEOUT_US 1000
40
41 #define NUM_PROVIDED_CLKS 2
42
43 #define VCO_REF_CLK_RATE 19200000
44 #define VCO_MIN_RATE 1300000000UL
45 #define VCO_MAX_RATE 2600000000UL
46
47 #define DSI_BYTE_PLL_CLK 0
48 #define DSI_PIXEL_PLL_CLK 1
49
50 #define DSI_PLL_DEFAULT_VCO_POSTDIV 1
51
52 struct dsi_pll_input {
53 u32 fref; /* reference clk */
54 u32 fdata; /* bit clock rate */
55 u32 dsiclk_sel; /* Mux configuration (see diagram) */
56 u32 ssc_en; /* SSC enable/disable */
57 u32 ldo_en;
58
59 /* fixed params */
60 u32 refclk_dbler_en;
61 u32 vco_measure_time;
62 u32 kvco_measure_time;
63 u32 bandgap_timer;
64 u32 pll_wakeup_timer;
65 u32 plllock_cnt;
66 u32 plllock_rng;
67 u32 ssc_center;
68 u32 ssc_adj_period;
69 u32 ssc_spread;
70 u32 ssc_freq;
71 u32 pll_ie_trim;
72 u32 pll_ip_trim;
73 u32 pll_iptat_trim;
74 u32 pll_cpcset_cur;
75 u32 pll_cpmset_cur;
76
77 u32 pll_icpmset;
78 u32 pll_icpcset;
79
80 u32 pll_icpmset_p;
81 u32 pll_icpmset_m;
82
83 u32 pll_icpcset_p;
84 u32 pll_icpcset_m;
85
86 u32 pll_lpf_res1;
87 u32 pll_lpf_cap1;
88 u32 pll_lpf_cap2;
89 u32 pll_c3ctrl;
90 u32 pll_r3ctrl;
91 };
92
93 struct dsi_pll_output {
94 u32 pll_txclk_en;
95 u32 dec_start;
96 u32 div_frac_start;
97 u32 ssc_period;
98 u32 ssc_step_size;
99 u32 plllock_cmp;
100 u32 pll_vco_div_ref;
101 u32 pll_vco_count;
102 u32 pll_kvco_div_ref;
103 u32 pll_kvco_count;
104 u32 pll_misc1;
105 u32 pll_lpf2_postdiv;
106 u32 pll_resetsm_cntrl;
107 u32 pll_resetsm_cntrl2;
108 u32 pll_resetsm_cntrl5;
109 u32 pll_kvco_code;
110
111 u32 cmn_clk_cfg0;
112 u32 cmn_clk_cfg1;
113 u32 cmn_ldo_cntrl;
114
115 u32 pll_postdiv;
116 u32 fcvo;
117 };
118
119 struct pll_14nm_cached_state {
120 unsigned long vco_rate;
121 u8 n2postdiv;
122 u8 n1postdiv;
123 };
124
125 struct dsi_pll_14nm {
126 struct msm_dsi_pll base;
127
128 int id;
129 struct platform_device *pdev;
130
131 void __iomem *phy_cmn_mmio;
132 void __iomem *mmio;
133
134 int vco_delay;
135
136 struct dsi_pll_input in;
137 struct dsi_pll_output out;
138
139 /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
140 spinlock_t postdiv_lock;
141
142 u64 vco_current_rate;
143 u64 vco_ref_clk_rate;
144
145 /* private clocks: */
146 struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
147 u32 num_hws;
148
149 /* clock-provider: */
150 struct clk_hw_onecell_data *hw_data;
151
152 struct pll_14nm_cached_state cached_state;
153
154 enum msm_dsi_phy_usecase uc;
155 struct dsi_pll_14nm *slave;
156 };
157
158 #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
159
160 /*
161 * Private struct for N1/N2 post-divider clocks. These clocks are similar to
162 * the generic clk_divider class of clocks. The only difference is that it
163 * also sets the slave DSI PLL's post-dividers if in Dual DSI mode
164 */
165 struct dsi_pll_14nm_postdiv {
166 struct clk_hw hw;
167
168 /* divider params */
169 u8 shift;
170 u8 width;
171 u8 flags; /* same flags as used by clk_divider struct */
172
173 struct dsi_pll_14nm *pll;
174 };
175
176 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
177
178 /*
179 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
180 * mode, where the master PLL's clk_ops needs access the slave's private data
181 */
182 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
183
184 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
185 u32 nb_tries, u32 timeout_us)
186 {
187 bool pll_locked = false;
188 void __iomem *base = pll_14nm->mmio;
189 u32 tries, val;
190
191 tries = nb_tries;
192 while (tries--) {
193 val = pll_read(base +
194 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
195 pll_locked = !!(val & BIT(5));
196
197 if (pll_locked)
198 break;
199
200 udelay(timeout_us);
201 }
202
203 if (!pll_locked) {
204 tries = nb_tries;
205 while (tries--) {
206 val = pll_read(base +
207 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
208 pll_locked = !!(val & BIT(0));
209
210 if (pll_locked)
211 break;
212
213 udelay(timeout_us);
214 }
215 }
216
217 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
218
219 return pll_locked;
220 }
221
222 static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
223 {
224 pll->in.fref = pll->vco_ref_clk_rate;
225 pll->in.fdata = 0;
226 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
227 pll->in.ldo_en = 0; /* disabled for now */
228
229 /* fixed input */
230 pll->in.refclk_dbler_en = 0;
231 pll->in.vco_measure_time = 5;
232 pll->in.kvco_measure_time = 5;
233 pll->in.bandgap_timer = 4;
234 pll->in.pll_wakeup_timer = 5;
235 pll->in.plllock_cnt = 1;
236 pll->in.plllock_rng = 0;
237
238 /*
239 * SSC is enabled by default. We might need DT props for configuring
240 * some SSC params like PPM and center/down spread etc.
241 */
242 pll->in.ssc_en = 1;
243 pll->in.ssc_center = 0; /* down spread by default */
244 pll->in.ssc_spread = 5; /* PPM / 1000 */
245 pll->in.ssc_freq = 31500; /* default recommended */
246 pll->in.ssc_adj_period = 37;
247
248 pll->in.pll_ie_trim = 4;
249 pll->in.pll_ip_trim = 4;
250 pll->in.pll_cpcset_cur = 1;
251 pll->in.pll_cpmset_cur = 1;
252 pll->in.pll_icpmset = 4;
253 pll->in.pll_icpcset = 4;
254 pll->in.pll_icpmset_p = 0;
255 pll->in.pll_icpmset_m = 0;
256 pll->in.pll_icpcset_p = 0;
257 pll->in.pll_icpcset_m = 0;
258 pll->in.pll_lpf_res1 = 3;
259 pll->in.pll_lpf_cap1 = 11;
260 pll->in.pll_lpf_cap2 = 1;
261 pll->in.pll_iptat_trim = 7;
262 pll->in.pll_c3ctrl = 2;
263 pll->in.pll_r3ctrl = 1;
264 }
265
266 #define CEIL(x, y) (((x) + ((y) - 1)) / (y))
267
268 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
269 {
270 u32 period, ssc_period;
271 u32 ref, rem;
272 u64 step_size;
273
274 DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate);
275
276 ssc_period = pll->in.ssc_freq / 500;
277 period = (u32)pll->vco_ref_clk_rate / 1000;
278 ssc_period = CEIL(period, ssc_period);
279 ssc_period -= 1;
280 pll->out.ssc_period = ssc_period;
281
282 DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
283 pll->in.ssc_spread, pll->out.ssc_period);
284
285 step_size = (u32)pll->vco_current_rate;
286 ref = pll->vco_ref_clk_rate;
287 ref /= 1000;
288 step_size = div_u64(step_size, ref);
289 step_size <<= 20;
290 step_size = div_u64(step_size, 1000);
291 step_size *= pll->in.ssc_spread;
292 step_size = div_u64(step_size, 1000);
293 step_size *= (pll->in.ssc_adj_period + 1);
294
295 rem = 0;
296 step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
297 if (rem)
298 step_size++;
299
300 DBG("step_size=%lld", step_size);
301
302 step_size &= 0x0ffff; /* take lower 16 bits */
303
304 pll->out.ssc_step_size = step_size;
305 }
306
307 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
308 {
309 struct dsi_pll_input *pin = &pll->in;
310 struct dsi_pll_output *pout = &pll->out;
311 u64 multiplier = BIT(20);
312 u64 dec_start_multiple, dec_start, pll_comp_val;
313 u32 duration, div_frac_start;
314 u64 vco_clk_rate = pll->vco_current_rate;
315 u64 fref = pll->vco_ref_clk_rate;
316
317 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
318
319 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
320 div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
321
322 dec_start = div_u64(dec_start_multiple, multiplier);
323
324 pout->dec_start = (u32)dec_start;
325 pout->div_frac_start = div_frac_start;
326
327 if (pin->plllock_cnt == 0)
328 duration = 1024;
329 else if (pin->plllock_cnt == 1)
330 duration = 256;
331 else if (pin->plllock_cnt == 2)
332 duration = 128;
333 else
334 duration = 32;
335
336 pll_comp_val = duration * dec_start_multiple;
337 pll_comp_val = div_u64(pll_comp_val, multiplier);
338 do_div(pll_comp_val, 10);
339
340 pout->plllock_cmp = (u32)pll_comp_val;
341
342 pout->pll_txclk_en = 1;
343 pout->cmn_ldo_cntrl = 0x3c;
344 }
345
346 static u32 pll_14nm_kvco_slop(u32 vrate)
347 {
348 u32 slop = 0;
349
350 if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
351 slop = 600;
352 else if (vrate > 1800000000UL && vrate < 2300000000UL)
353 slop = 400;
354 else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
355 slop = 280;
356
357 return slop;
358 }
359
360 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
361 {
362 struct dsi_pll_input *pin = &pll->in;
363 struct dsi_pll_output *pout = &pll->out;
364 u64 vco_clk_rate = pll->vco_current_rate;
365 u64 fref = pll->vco_ref_clk_rate;
366 u64 data;
367 u32 cnt;
368
369 data = fref * pin->vco_measure_time;
370 do_div(data, 1000000);
371 data &= 0x03ff; /* 10 bits */
372 data -= 2;
373 pout->pll_vco_div_ref = data;
374
375 data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
376 data *= pin->vco_measure_time;
377 do_div(data, 10);
378 pout->pll_vco_count = data;
379
380 data = fref * pin->kvco_measure_time;
381 do_div(data, 1000000);
382 data &= 0x03ff; /* 10 bits */
383 data -= 1;
384 pout->pll_kvco_div_ref = data;
385
386 cnt = pll_14nm_kvco_slop(vco_clk_rate);
387 cnt *= 2;
388 cnt /= 100;
389 cnt *= pin->kvco_measure_time;
390 pout->pll_kvco_count = cnt;
391
392 pout->pll_misc1 = 16;
393 pout->pll_resetsm_cntrl = 48;
394 pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
395 pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
396 pout->pll_kvco_code = 0;
397 }
398
399 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
400 {
401 void __iomem *base = pll->mmio;
402 struct dsi_pll_input *pin = &pll->in;
403 struct dsi_pll_output *pout = &pll->out;
404 u8 data;
405
406 data = pin->ssc_adj_period;
407 data &= 0x0ff;
408 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
409 data = (pin->ssc_adj_period >> 8);
410 data &= 0x03;
411 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
412
413 data = pout->ssc_period;
414 data &= 0x0ff;
415 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
416 data = (pout->ssc_period >> 8);
417 data &= 0x0ff;
418 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
419
420 data = pout->ssc_step_size;
421 data &= 0x0ff;
422 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
423 data = (pout->ssc_step_size >> 8);
424 data &= 0x0ff;
425 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
426
427 data = (pin->ssc_center & 0x01);
428 data <<= 1;
429 data |= 0x01; /* enable */
430 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
431
432 wmb(); /* make sure register committed */
433 }
434
435 static void pll_db_commit_common(struct dsi_pll_14nm *pll,
436 struct dsi_pll_input *pin,
437 struct dsi_pll_output *pout)
438 {
439 void __iomem *base = pll->mmio;
440 u8 data;
441
442 /* confgiure the non frequency dependent pll registers */
443 data = 0;
444 pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
445
446 data = pout->pll_txclk_en;
447 pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
448
449 data = pout->pll_resetsm_cntrl;
450 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
451 data = pout->pll_resetsm_cntrl2;
452 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
453 data = pout->pll_resetsm_cntrl5;
454 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
455
456 data = pout->pll_vco_div_ref & 0xff;
457 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
458 data = (pout->pll_vco_div_ref >> 8) & 0x3;
459 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
460
461 data = pout->pll_kvco_div_ref & 0xff;
462 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
463 data = (pout->pll_kvco_div_ref >> 8) & 0x3;
464 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
465
466 data = pout->pll_misc1;
467 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
468
469 data = pin->pll_ie_trim;
470 pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
471
472 data = pin->pll_ip_trim;
473 pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
474
475 data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
476 pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
477
478 data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
479 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
480
481 data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
482 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
483
484 data = pin->pll_icpmset << 3 | pin->pll_icpcset;
485 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
486
487 data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
488 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
489
490 data = pin->pll_iptat_trim;
491 pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
492
493 data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
494 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
495 }
496
497 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
498 {
499 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
500
501 /* de assert pll start and apply pll sw reset */
502
503 /* stop pll */
504 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
505
506 /* pll sw reset */
507 pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
508 wmb(); /* make sure register committed */
509
510 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
511 wmb(); /* make sure register committed */
512 }
513
514 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
515 struct dsi_pll_input *pin,
516 struct dsi_pll_output *pout)
517 {
518 void __iomem *base = pll->mmio;
519 void __iomem *cmn_base = pll->phy_cmn_mmio;
520 u8 data;
521
522 DBG("DSI%d PLL", pll->id);
523
524 data = pout->cmn_ldo_cntrl;
525 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
526
527 pll_db_commit_common(pll, pin, pout);
528
529 pll_14nm_software_reset(pll);
530
531 data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
532 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
533
534 data = 0xff; /* data, clk, pll normal operation */
535 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
536
537 /* configure the frequency dependent pll registers */
538 data = pout->dec_start;
539 pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
540
541 data = pout->div_frac_start & 0xff;
542 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
543 data = (pout->div_frac_start >> 8) & 0xff;
544 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
545 data = (pout->div_frac_start >> 16) & 0xf;
546 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
547
548 data = pout->plllock_cmp & 0xff;
549 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
550
551 data = (pout->plllock_cmp >> 8) & 0xff;
552 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
553
554 data = (pout->plllock_cmp >> 16) & 0x3;
555 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
556
557 data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
558 pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
559
560 data = pout->pll_vco_count & 0xff;
561 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
562 data = (pout->pll_vco_count >> 8) & 0xff;
563 pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
564
565 data = pout->pll_kvco_count & 0xff;
566 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
567 data = (pout->pll_kvco_count >> 8) & 0x3;
568 pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
569
570 data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
571 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
572
573 if (pin->ssc_en)
574 pll_db_commit_ssc(pll);
575
576 wmb(); /* make sure register committed */
577 }
578
579 /*
580 * VCO clock Callbacks
581 */
582 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
583 unsigned long parent_rate)
584 {
585 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
586 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
587 struct dsi_pll_input *pin = &pll_14nm->in;
588 struct dsi_pll_output *pout = &pll_14nm->out;
589
590 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
591 parent_rate);
592
593 pll_14nm->vco_current_rate = rate;
594 pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
595
596 dsi_pll_14nm_input_init(pll_14nm);
597
598 /*
599 * This configures the post divider internal to the VCO. It's
600 * fixed to divide by 1 for now.
601 *
602 * tx_band = pll_postdiv.
603 * 0: divided by 1
604 * 1: divided by 2
605 * 2: divided by 4
606 * 3: divided by 8
607 */
608 pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
609
610 pll_14nm_dec_frac_calc(pll_14nm);
611
612 if (pin->ssc_en)
613 pll_14nm_ssc_calc(pll_14nm);
614
615 pll_14nm_calc_vco_count(pll_14nm);
616
617 /* commit the slave DSI PLL registers if we're master. Note that we
618 * don't lock the slave PLL. We just ensure that the PLL/PHY registers
619 * of the master and slave are identical
620 */
621 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
622 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
623
624 pll_db_commit_14nm(pll_14nm_slave, pin, pout);
625 }
626
627 pll_db_commit_14nm(pll_14nm, pin, pout);
628
629 return 0;
630 }
631
632 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
633 unsigned long parent_rate)
634 {
635 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
636 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
637 void __iomem *base = pll_14nm->mmio;
638 u64 vco_rate, multiplier = BIT(20);
639 u32 div_frac_start;
640 u32 dec_start;
641 u64 ref_clk = parent_rate;
642
643 dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
644 dec_start &= 0x0ff;
645
646 DBG("dec_start = %x", dec_start);
647
648 div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
649 & 0xf) << 16;
650 div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
651 & 0xff) << 8;
652 div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
653 & 0xff;
654
655 DBG("div_frac_start = %x", div_frac_start);
656
657 vco_rate = ref_clk * dec_start;
658
659 vco_rate += ((ref_clk * div_frac_start) / multiplier);
660
661 /*
662 * Recalculating the rate from dec_start and frac_start doesn't end up
663 * the rate we originally set. Convert the freq to KHz, round it up and
664 * convert it back to MHz.
665 */
666 vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
667
668 DBG("returning vco rate = %lu", (unsigned long)vco_rate);
669
670 return (unsigned long)vco_rate;
671 }
672
673 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
674 .round_rate = msm_dsi_pll_helper_clk_round_rate,
675 .set_rate = dsi_pll_14nm_vco_set_rate,
676 .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
677 .prepare = msm_dsi_pll_helper_clk_prepare,
678 .unprepare = msm_dsi_pll_helper_clk_unprepare,
679 };
680
681 /*
682 * N1 and N2 post-divider clock callbacks
683 */
684 #define div_mask(width) ((1 << (width)) - 1)
685 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
686 unsigned long parent_rate)
687 {
688 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
689 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
690 void __iomem *base = pll_14nm->phy_cmn_mmio;
691 u8 shift = postdiv->shift;
692 u8 width = postdiv->width;
693 u32 val;
694
695 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
696
697 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
698 val &= div_mask(width);
699
700 return divider_recalc_rate(hw, parent_rate, val, NULL,
701 postdiv->flags, width);
702 }
703
704 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
705 unsigned long rate,
706 unsigned long *prate)
707 {
708 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
709 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
710
711 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
712
713 return divider_round_rate(hw, rate, prate, NULL,
714 postdiv->width,
715 postdiv->flags);
716 }
717
718 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
719 unsigned long parent_rate)
720 {
721 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
722 struct dsi_pll_14nm *pll_14nm = postdiv->pll;
723 void __iomem *base = pll_14nm->phy_cmn_mmio;
724 spinlock_t *lock = &pll_14nm->postdiv_lock;
725 u8 shift = postdiv->shift;
726 u8 width = postdiv->width;
727 unsigned int value;
728 unsigned long flags = 0;
729 u32 val;
730
731 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
732 parent_rate);
733
734 value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
735 postdiv->flags);
736
737 spin_lock_irqsave(lock, flags);
738
739 val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
740 val &= ~(div_mask(width) << shift);
741
742 val |= value << shift;
743 pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
744
745 /* If we're master in dual DSI mode, then the slave PLL's post-dividers
746 * follow the master's post dividers
747 */
748 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
749 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
750 void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
751
752 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
753 }
754
755 spin_unlock_irqrestore(lock, flags);
756
757 return 0;
758 }
759
760 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
761 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
762 .round_rate = dsi_pll_14nm_postdiv_round_rate,
763 .set_rate = dsi_pll_14nm_postdiv_set_rate,
764 };
765
766 /*
767 * PLL Callbacks
768 */
769
770 static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
771 {
772 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
773 void __iomem *base = pll_14nm->mmio;
774 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
775 bool locked;
776
777 DBG("");
778
779 pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
780 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
781
782 locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
783 POLL_TIMEOUT_US);
784
785 if (unlikely(!locked))
786 DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
787 else
788 DBG("DSI PLL lock success");
789
790 return locked ? 0 : -EINVAL;
791 }
792
793 static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
794 {
795 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
796 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
797
798 DBG("");
799
800 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
801 }
802
803 static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
804 {
805 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
806 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
807 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
808 u32 data;
809
810 data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
811
812 cached_state->n1postdiv = data & 0xf;
813 cached_state->n2postdiv = (data >> 4) & 0xf;
814
815 DBG("DSI%d PLL save state %x %x", pll_14nm->id,
816 cached_state->n1postdiv, cached_state->n2postdiv);
817
818 cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
819 }
820
821 static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll)
822 {
823 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
824 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
825 void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
826 u32 data;
827 int ret;
828
829 ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw,
830 cached_state->vco_rate, 0);
831 if (ret) {
832 DRM_DEV_ERROR(&pll_14nm->pdev->dev,
833 "restore vco rate failed. ret=%d\n", ret);
834 return ret;
835 }
836
837 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
838
839 DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
840 cached_state->n1postdiv, cached_state->n2postdiv);
841
842 pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
843
844 /* also restore post-dividers for slave DSI PLL */
845 if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
846 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
847 void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
848
849 pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
850 }
851
852 return 0;
853 }
854
855 static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
856 enum msm_dsi_phy_usecase uc)
857 {
858 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
859 void __iomem *base = pll_14nm->mmio;
860 u32 clkbuflr_en, bandgap = 0;
861
862 switch (uc) {
863 case MSM_DSI_PHY_STANDALONE:
864 clkbuflr_en = 0x1;
865 break;
866 case MSM_DSI_PHY_MASTER:
867 clkbuflr_en = 0x3;
868 pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
869 break;
870 case MSM_DSI_PHY_SLAVE:
871 clkbuflr_en = 0x0;
872 bandgap = 0x3;
873 break;
874 default:
875 return -EINVAL;
876 }
877
878 pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
879 if (bandgap)
880 pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
881
882 pll_14nm->uc = uc;
883
884 return 0;
885 }
886
887 static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
888 struct clk **byte_clk_provider,
889 struct clk **pixel_clk_provider)
890 {
891 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
892 struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
893
894 if (byte_clk_provider)
895 *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
896 if (pixel_clk_provider)
897 *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
898
899 return 0;
900 }
901
902 static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
903 {
904 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
905 struct platform_device *pdev = pll_14nm->pdev;
906 int num_hws = pll_14nm->num_hws;
907
908 of_clk_del_provider(pdev->dev.of_node);
909
910 while (num_hws--)
911 clk_hw_unregister(pll_14nm->hws[num_hws]);
912 }
913
914 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
915 const char *name,
916 const char *parent_name,
917 unsigned long flags,
918 u8 shift)
919 {
920 struct dsi_pll_14nm_postdiv *pll_postdiv;
921 struct device *dev = &pll_14nm->pdev->dev;
922 struct clk_init_data postdiv_init = {
923 .parent_names = (const char *[]) { parent_name },
924 .num_parents = 1,
925 .name = name,
926 .flags = flags,
927 .ops = &clk_ops_dsi_pll_14nm_postdiv,
928 };
929 int ret;
930
931 pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
932 if (!pll_postdiv)
933 return ERR_PTR(-ENOMEM);
934
935 pll_postdiv->pll = pll_14nm;
936 pll_postdiv->shift = shift;
937 /* both N1 and N2 postdividers are 4 bits wide */
938 pll_postdiv->width = 4;
939 /* range of each divider is from 1 to 15 */
940 pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
941 pll_postdiv->hw.init = &postdiv_init;
942
943 ret = clk_hw_register(dev, &pll_postdiv->hw);
944 if (ret)
945 return ERR_PTR(ret);
946
947 return &pll_postdiv->hw;
948 }
949
950 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
951 {
952 char clk_name[32], parent[32], vco_name[32];
953 struct clk_init_data vco_init = {
954 .parent_names = (const char *[]){ "xo" },
955 .num_parents = 1,
956 .name = vco_name,
957 .flags = CLK_IGNORE_UNUSED,
958 .ops = &clk_ops_dsi_pll_14nm_vco,
959 };
960 struct device *dev = &pll_14nm->pdev->dev;
961 struct clk_hw **hws = pll_14nm->hws;
962 struct clk_hw_onecell_data *hw_data;
963 struct clk_hw *hw;
964 int num = 0;
965 int ret;
966
967 DBG("DSI%d", pll_14nm->id);
968
969 hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
970 NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
971 GFP_KERNEL);
972 if (!hw_data)
973 return -ENOMEM;
974
975 snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
976 pll_14nm->base.clk_hw.init = &vco_init;
977
978 ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
979 if (ret)
980 return ret;
981
982 hws[num++] = &pll_14nm->base.clk_hw;
983
984 snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
985 snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
986
987 /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
988 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
989 CLK_SET_RATE_PARENT, 0);
990 if (IS_ERR(hw))
991 return PTR_ERR(hw);
992
993 hws[num++] = hw;
994
995 snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
996 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
997
998 /* DSI Byte clock = VCO_CLK / N1 / 8 */
999 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
1000 CLK_SET_RATE_PARENT, 1, 8);
1001 if (IS_ERR(hw))
1002 return PTR_ERR(hw);
1003
1004 hws[num++] = hw;
1005 hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
1006
1007 snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
1008 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
1009
1010 /*
1011 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
1012 * on the way. Don't let it set parent.
1013 */
1014 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
1015 if (IS_ERR(hw))
1016 return PTR_ERR(hw);
1017
1018 hws[num++] = hw;
1019
1020 snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
1021 snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
1022
1023 /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
1024 * This is the output of N2 post-divider, bits 4-7 in
1025 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
1026 */
1027 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
1028 if (IS_ERR(hw))
1029 return PTR_ERR(hw);
1030
1031 hws[num++] = hw;
1032 hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
1033
1034 pll_14nm->num_hws = num;
1035
1036 hw_data->num = NUM_PROVIDED_CLKS;
1037 pll_14nm->hw_data = hw_data;
1038
1039 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
1040 pll_14nm->hw_data);
1041 if (ret) {
1042 DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
1043 return ret;
1044 }
1045
1046 return 0;
1047 }
1048
1049 struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
1050 {
1051 struct dsi_pll_14nm *pll_14nm;
1052 struct msm_dsi_pll *pll;
1053 int ret;
1054
1055 if (!pdev)
1056 return ERR_PTR(-ENODEV);
1057
1058 pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
1059 if (!pll_14nm)
1060 return ERR_PTR(-ENOMEM);
1061
1062 DBG("PLL%d", id);
1063
1064 pll_14nm->pdev = pdev;
1065 pll_14nm->id = id;
1066 pll_14nm_list[id] = pll_14nm;
1067
1068 pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
1069 if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
1070 DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
1071 return ERR_PTR(-ENOMEM);
1072 }
1073
1074 pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
1075 if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
1076 DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
1077 return ERR_PTR(-ENOMEM);
1078 }
1079
1080 spin_lock_init(&pll_14nm->postdiv_lock);
1081
1082 pll = &pll_14nm->base;
1083 pll->min_rate = VCO_MIN_RATE;
1084 pll->max_rate = VCO_MAX_RATE;
1085 pll->get_provider = dsi_pll_14nm_get_provider;
1086 pll->destroy = dsi_pll_14nm_destroy;
1087 pll->disable_seq = dsi_pll_14nm_disable_seq;
1088 pll->save_state = dsi_pll_14nm_save_state;
1089 pll->restore_state = dsi_pll_14nm_restore_state;
1090 pll->set_usecase = dsi_pll_14nm_set_usecase;
1091
1092 pll_14nm->vco_delay = 1;
1093
1094 pll->en_seq_cnt = 1;
1095 pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
1096
1097 ret = pll_14nm_register(pll_14nm);
1098 if (ret) {
1099 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
1100 return ERR_PTR(ret);
1101 }
1102
1103 return pll;
1104 }
Linux with added FPC-III support