?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / ethernet / cortina / gemini.c
blob949103db8a8ad75afab234f879acddc7e8c4a515
1 // SPDX-License-Identifier: GPL-2.0
2 /* Ethernet device driver for Cortina Systems Gemini SoC
3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
4 * Net Engine and Gigabit Ethernet MAC (GMAC)
5 * This hardware contains a TCP Offload Engine (TOE) but currently the
6 * driver does not make use of it.
7 *
8 * Authors:
9 * Linus Walleij <linus.walleij@linaro.org>
10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
14 * Gary Chen & Ch Hsu Storlink Semiconductor
15 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/cache.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 #include <linux/clk.h>
27 #include <linux/of.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_platform.h>
31 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/skbuff.h>
34 #include <linux/phy.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/tcp.h>
38 #include <linux/u64_stats_sync.h>
39
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/ipv6.h>
43
44 #include "gemini.h"
45
46 #define DRV_NAME "gmac-gemini"
47 #define DRV_VERSION "1.0"
48
49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
50 static int debug = -1;
51 module_param(debug, int, 0);
52 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
53
54 #define HSIZE_8 0x00
55 #define HSIZE_16 0x01
56 #define HSIZE_32 0x02
57
58 #define HBURST_SINGLE 0x00
59 #define HBURST_INCR 0x01
60 #define HBURST_INCR4 0x02
61 #define HBURST_INCR8 0x03
62
63 #define HPROT_DATA_CACHE BIT(0)
64 #define HPROT_PRIVILIGED BIT(1)
65 #define HPROT_BUFFERABLE BIT(2)
66 #define HPROT_CACHABLE BIT(3)
67
68 #define DEFAULT_RX_COALESCE_NSECS 0
69 #define DEFAULT_GMAC_RXQ_ORDER 9
70 #define DEFAULT_GMAC_TXQ_ORDER 8
71 #define DEFAULT_RX_BUF_ORDER 11
72 #define DEFAULT_NAPI_WEIGHT 64
73 #define TX_MAX_FRAGS 16
74 #define TX_QUEUE_NUM 1 /* max: 6 */
75 #define RX_MAX_ALLOC_ORDER 2
76
77 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
78 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
79 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
80 GMAC0_SWTQ00_FIN_INT_BIT)
81 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
82
83 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
84 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
85 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
86
87 /**
88 * struct gmac_queue_page - page buffer per-page info
89 */
90 struct gmac_queue_page {
91 struct page *page;
92 dma_addr_t mapping;
93 };
94
95 struct gmac_txq {
96 struct gmac_txdesc *ring;
97 struct sk_buff **skb;
98 unsigned int cptr;
99 unsigned int noirq_packets;
100 };
101
102 struct gemini_ethernet;
103
104 struct gemini_ethernet_port {
105 u8 id; /* 0 or 1 */
106
107 struct gemini_ethernet *geth;
108 struct net_device *netdev;
109 struct device *dev;
110 void __iomem *dma_base;
111 void __iomem *gmac_base;
112 struct clk *pclk;
113 struct reset_control *reset;
114 int irq;
115 __le32 mac_addr[3];
116
117 void __iomem *rxq_rwptr;
118 struct gmac_rxdesc *rxq_ring;
119 unsigned int rxq_order;
120
121 struct napi_struct napi;
122 struct hrtimer rx_coalesce_timer;
123 unsigned int rx_coalesce_nsecs;
124 unsigned int freeq_refill;
125 struct gmac_txq txq[TX_QUEUE_NUM];
126 unsigned int txq_order;
127 unsigned int irq_every_tx_packets;
128
129 dma_addr_t rxq_dma_base;
130 dma_addr_t txq_dma_base;
131
132 unsigned int msg_enable;
133 spinlock_t config_lock; /* Locks config register */
134
135 struct u64_stats_sync tx_stats_syncp;
136 struct u64_stats_sync rx_stats_syncp;
137 struct u64_stats_sync ir_stats_syncp;
138
139 struct rtnl_link_stats64 stats;
140 u64 hw_stats[RX_STATS_NUM];
141 u64 rx_stats[RX_STATUS_NUM];
142 u64 rx_csum_stats[RX_CHKSUM_NUM];
143 u64 rx_napi_exits;
144 u64 tx_frag_stats[TX_MAX_FRAGS];
145 u64 tx_frags_linearized;
146 u64 tx_hw_csummed;
147 };
148
149 struct gemini_ethernet {
150 struct device *dev;
151 void __iomem *base;
152 struct gemini_ethernet_port *port0;
153 struct gemini_ethernet_port *port1;
154 bool initialized;
155
156 spinlock_t irq_lock; /* Locks IRQ-related registers */
157 unsigned int freeq_order;
158 unsigned int freeq_frag_order;
159 struct gmac_rxdesc *freeq_ring;
160 dma_addr_t freeq_dma_base;
161 struct gmac_queue_page *freeq_pages;
162 unsigned int num_freeq_pages;
163 spinlock_t freeq_lock; /* Locks queue from reentrance */
164 };
165
166 #define GMAC_STATS_NUM ( \
167 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
168 TX_MAX_FRAGS + 2)
169
170 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
171 "GMAC_IN_DISCARDS",
172 "GMAC_IN_ERRORS",
173 "GMAC_IN_MCAST",
174 "GMAC_IN_BCAST",
175 "GMAC_IN_MAC1",
176 "GMAC_IN_MAC2",
177 "RX_STATUS_GOOD_FRAME",
178 "RX_STATUS_TOO_LONG_GOOD_CRC",
179 "RX_STATUS_RUNT_FRAME",
180 "RX_STATUS_SFD_NOT_FOUND",
181 "RX_STATUS_CRC_ERROR",
182 "RX_STATUS_TOO_LONG_BAD_CRC",
183 "RX_STATUS_ALIGNMENT_ERROR",
184 "RX_STATUS_TOO_LONG_BAD_ALIGN",
185 "RX_STATUS_RX_ERR",
186 "RX_STATUS_DA_FILTERED",
187 "RX_STATUS_BUFFER_FULL",
188 "RX_STATUS_11",
189 "RX_STATUS_12",
190 "RX_STATUS_13",
191 "RX_STATUS_14",
192 "RX_STATUS_15",
193 "RX_CHKSUM_IP_UDP_TCP_OK",
194 "RX_CHKSUM_IP_OK_ONLY",
195 "RX_CHKSUM_NONE",
196 "RX_CHKSUM_3",
197 "RX_CHKSUM_IP_ERR_UNKNOWN",
198 "RX_CHKSUM_IP_ERR",
199 "RX_CHKSUM_TCP_UDP_ERR",
200 "RX_CHKSUM_7",
201 "RX_NAPI_EXITS",
202 "TX_FRAGS[1]",
203 "TX_FRAGS[2]",
204 "TX_FRAGS[3]",
205 "TX_FRAGS[4]",
206 "TX_FRAGS[5]",
207 "TX_FRAGS[6]",
208 "TX_FRAGS[7]",
209 "TX_FRAGS[8]",
210 "TX_FRAGS[9]",
211 "TX_FRAGS[10]",
212 "TX_FRAGS[11]",
213 "TX_FRAGS[12]",
214 "TX_FRAGS[13]",
215 "TX_FRAGS[14]",
216 "TX_FRAGS[15]",
217 "TX_FRAGS[16+]",
218 "TX_FRAGS_LINEARIZED",
219 "TX_HW_CSUMMED",
220 };
221
222 static void gmac_dump_dma_state(struct net_device *netdev);
223
224 static void gmac_update_config0_reg(struct net_device *netdev,
225 u32 val, u32 vmask)
226 {
227 struct gemini_ethernet_port *port = netdev_priv(netdev);
228 unsigned long flags;
229 u32 reg;
230
231 spin_lock_irqsave(&port->config_lock, flags);
232
233 reg = readl(port->gmac_base + GMAC_CONFIG0);
234 reg = (reg & ~vmask) | val;
235 writel(reg, port->gmac_base + GMAC_CONFIG0);
236
237 spin_unlock_irqrestore(&port->config_lock, flags);
238 }
239
240 static void gmac_enable_tx_rx(struct net_device *netdev)
241 {
242 struct gemini_ethernet_port *port = netdev_priv(netdev);
243 unsigned long flags;
244 u32 reg;
245
246 spin_lock_irqsave(&port->config_lock, flags);
247
248 reg = readl(port->gmac_base + GMAC_CONFIG0);
249 reg &= ~CONFIG0_TX_RX_DISABLE;
250 writel(reg, port->gmac_base + GMAC_CONFIG0);
251
252 spin_unlock_irqrestore(&port->config_lock, flags);
253 }
254
255 static void gmac_disable_tx_rx(struct net_device *netdev)
256 {
257 struct gemini_ethernet_port *port = netdev_priv(netdev);
258 unsigned long flags;
259 u32 val;
260
261 spin_lock_irqsave(&port->config_lock, flags);
262
263 val = readl(port->gmac_base + GMAC_CONFIG0);
264 val |= CONFIG0_TX_RX_DISABLE;
265 writel(val, port->gmac_base + GMAC_CONFIG0);
266
267 spin_unlock_irqrestore(&port->config_lock, flags);
268
269 mdelay(10); /* let GMAC consume packet */
270 }
271
272 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
273 {
274 struct gemini_ethernet_port *port = netdev_priv(netdev);
275 unsigned long flags;
276 u32 val;
277
278 spin_lock_irqsave(&port->config_lock, flags);
279
280 val = readl(port->gmac_base + GMAC_CONFIG0);
281 val &= ~CONFIG0_FLOW_CTL;
282 if (tx)
283 val |= CONFIG0_FLOW_TX;
284 if (rx)
285 val |= CONFIG0_FLOW_RX;
286 writel(val, port->gmac_base + GMAC_CONFIG0);
287
288 spin_unlock_irqrestore(&port->config_lock, flags);
289 }
290
291 static void gmac_speed_set(struct net_device *netdev)
292 {
293 struct gemini_ethernet_port *port = netdev_priv(netdev);
294 struct phy_device *phydev = netdev->phydev;
295 union gmac_status status, old_status;
296 int pause_tx = 0;
297 int pause_rx = 0;
298
299 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
300 old_status.bits32 = status.bits32;
301 status.bits.link = phydev->link;
302 status.bits.duplex = phydev->duplex;
303
304 switch (phydev->speed) {
305 case 1000:
306 status.bits.speed = GMAC_SPEED_1000;
307 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
308 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
309 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
310 phydev_name(phydev));
311 break;
312 case 100:
313 status.bits.speed = GMAC_SPEED_100;
314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
315 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
316 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
317 phydev_name(phydev));
318 break;
319 case 10:
320 status.bits.speed = GMAC_SPEED_10;
321 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
322 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
323 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
324 phydev_name(phydev));
325 break;
326 default:
327 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
328 phydev->speed, phydev_name(phydev));
329 }
330
331 if (phydev->duplex == DUPLEX_FULL) {
332 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
333 u16 rmtadv = phy_read(phydev, MII_LPA);
334 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
335
336 if (cap & FLOW_CTRL_RX)
337 pause_rx = 1;
338 if (cap & FLOW_CTRL_TX)
339 pause_tx = 1;
340 }
341
342 gmac_set_flow_control(netdev, pause_tx, pause_rx);
343
344 if (old_status.bits32 == status.bits32)
345 return;
346
347 if (netif_msg_link(port)) {
348 phy_print_status(phydev);
349 netdev_info(netdev, "link flow control: %s\n",
350 phydev->pause
351 ? (phydev->asym_pause ? "tx" : "both")
352 : (phydev->asym_pause ? "rx" : "none")
353 );
354 }
355
356 gmac_disable_tx_rx(netdev);
357 writel(status.bits32, port->gmac_base + GMAC_STATUS);
358 gmac_enable_tx_rx(netdev);
359 }
360
361 static int gmac_setup_phy(struct net_device *netdev)
362 {
363 struct gemini_ethernet_port *port = netdev_priv(netdev);
364 union gmac_status status = { .bits32 = 0 };
365 struct device *dev = port->dev;
366 struct phy_device *phy;
367
368 phy = of_phy_get_and_connect(netdev,
369 dev->of_node,
370 gmac_speed_set);
371 if (!phy)
372 return -ENODEV;
373 netdev->phydev = phy;
374
375 phy_set_max_speed(phy, SPEED_1000);
376 phy_support_asym_pause(phy);
377
378 /* set PHY interface type */
379 switch (phy->interface) {
380 case PHY_INTERFACE_MODE_MII:
381 netdev_dbg(netdev,
382 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
383 status.bits.mii_rmii = GMAC_PHY_MII;
384 break;
385 case PHY_INTERFACE_MODE_GMII:
386 netdev_dbg(netdev,
387 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
388 status.bits.mii_rmii = GMAC_PHY_GMII;
389 break;
390 case PHY_INTERFACE_MODE_RGMII:
391 netdev_dbg(netdev,
392 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
393 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
394 break;
395 default:
396 netdev_err(netdev, "Unsupported MII interface\n");
397 phy_disconnect(phy);
398 netdev->phydev = NULL;
399 return -EINVAL;
400 }
401 writel(status.bits32, port->gmac_base + GMAC_STATUS);
402
403 if (netif_msg_link(port))
404 phy_attached_info(phy);
405
406 return 0;
407 }
408
409 /* The maximum frame length is not logically enumerated in the
410 * hardware, so we do a table lookup to find the applicable max
411 * frame length.
412 */
413 struct gmac_max_framelen {
414 unsigned int max_l3_len;
415 u8 val;
416 };
417
418 static const struct gmac_max_framelen gmac_maxlens[] = {
419 {
420 .max_l3_len = 1518,
421 .val = CONFIG0_MAXLEN_1518,
422 },
423 {
424 .max_l3_len = 1522,
425 .val = CONFIG0_MAXLEN_1522,
426 },
427 {
428 .max_l3_len = 1536,
429 .val = CONFIG0_MAXLEN_1536,
430 },
431 {
432 .max_l3_len = 1542,
433 .val = CONFIG0_MAXLEN_1542,
434 },
435 {
436 .max_l3_len = 9212,
437 .val = CONFIG0_MAXLEN_9k,
438 },
439 {
440 .max_l3_len = 10236,
441 .val = CONFIG0_MAXLEN_10k,
442 },
443 };
444
445 static int gmac_pick_rx_max_len(unsigned int max_l3_len)
446 {
447 const struct gmac_max_framelen *maxlen;
448 int maxtot;
449 int i;
450
451 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
452
453 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
454 maxlen = &gmac_maxlens[i];
455 if (maxtot <= maxlen->max_l3_len)
456 return maxlen->val;
457 }
458
459 return -1;
460 }
461
462 static int gmac_init(struct net_device *netdev)
463 {
464 struct gemini_ethernet_port *port = netdev_priv(netdev);
465 union gmac_config0 config0 = { .bits = {
466 .dis_tx = 1,
467 .dis_rx = 1,
468 .ipv4_rx_chksum = 1,
469 .ipv6_rx_chksum = 1,
470 .rx_err_detect = 1,
471 .rgmm_edge = 1,
472 .port0_chk_hwq = 1,
473 .port1_chk_hwq = 1,
474 .port0_chk_toeq = 1,
475 .port1_chk_toeq = 1,
476 .port0_chk_classq = 1,
477 .port1_chk_classq = 1,
478 } };
479 union gmac_ahb_weight ahb_weight = { .bits = {
480 .rx_weight = 1,
481 .tx_weight = 1,
482 .hash_weight = 1,
483 .pre_req = 0x1f,
484 .tq_dv_threshold = 0,
485 } };
486 union gmac_tx_wcr0 hw_weigh = { .bits = {
487 .hw_tq3 = 1,
488 .hw_tq2 = 1,
489 .hw_tq1 = 1,
490 .hw_tq0 = 1,
491 } };
492 union gmac_tx_wcr1 sw_weigh = { .bits = {
493 .sw_tq5 = 1,
494 .sw_tq4 = 1,
495 .sw_tq3 = 1,
496 .sw_tq2 = 1,
497 .sw_tq1 = 1,
498 .sw_tq0 = 1,
499 } };
500 union gmac_config1 config1 = { .bits = {
501 .set_threshold = 16,
502 .rel_threshold = 24,
503 } };
504 union gmac_config2 config2 = { .bits = {
505 .set_threshold = 16,
506 .rel_threshold = 32,
507 } };
508 union gmac_config3 config3 = { .bits = {
509 .set_threshold = 0,
510 .rel_threshold = 0,
511 } };
512 union gmac_config0 tmp;
513 u32 val;
514
515 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
516 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
517 config0.bits.reserved = tmp.bits.reserved;
518 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
519 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
520 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
521 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
522
523 val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
524 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
525
526 writel(hw_weigh.bits32,
527 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
528 writel(sw_weigh.bits32,
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
530
531 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
532 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
533 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
534
535 /* Mark every quarter of the queue a packet for interrupt
536 * in order to be able to wake up the queue if it was stopped
537 */
538 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
539
540 return 0;
541 }
542
543 static void gmac_uninit(struct net_device *netdev)
544 {
545 if (netdev->phydev)
546 phy_disconnect(netdev->phydev);
547 }
548
549 static int gmac_setup_txqs(struct net_device *netdev)
550 {
551 struct gemini_ethernet_port *port = netdev_priv(netdev);
552 unsigned int n_txq = netdev->num_tx_queues;
553 struct gemini_ethernet *geth = port->geth;
554 size_t entries = 1 << port->txq_order;
555 struct gmac_txq *txq = port->txq;
556 struct gmac_txdesc *desc_ring;
557 size_t len = n_txq * entries;
558 struct sk_buff **skb_tab;
559 void __iomem *rwptr_reg;
560 unsigned int r;
561 int i;
562
563 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
564
565 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
566 if (!skb_tab)
567 return -ENOMEM;
568
569 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
570 &port->txq_dma_base, GFP_KERNEL);
571
572 if (!desc_ring) {
573 kfree(skb_tab);
574 return -ENOMEM;
575 }
576
577 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
578 dev_warn(geth->dev, "TX queue base is not aligned\n");
579 kfree(skb_tab);
580 return -ENOMEM;
581 }
582
583 writel(port->txq_dma_base | port->txq_order,
584 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
585
586 for (i = 0; i < n_txq; i++) {
587 txq->ring = desc_ring;
588 txq->skb = skb_tab;
589 txq->noirq_packets = 0;
590
591 r = readw(rwptr_reg);
592 rwptr_reg += 2;
593 writew(r, rwptr_reg);
594 rwptr_reg += 2;
595 txq->cptr = r;
596
597 txq++;
598 desc_ring += entries;
599 skb_tab += entries;
600 }
601
602 return 0;
603 }
604
605 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
606 unsigned int r)
607 {
608 struct gemini_ethernet_port *port = netdev_priv(netdev);
609 unsigned int m = (1 << port->txq_order) - 1;
610 struct gemini_ethernet *geth = port->geth;
611 unsigned int c = txq->cptr;
612 union gmac_txdesc_0 word0;
613 union gmac_txdesc_1 word1;
614 unsigned int hwchksum = 0;
615 unsigned long bytes = 0;
616 struct gmac_txdesc *txd;
617 unsigned short nfrags;
618 unsigned int errs = 0;
619 unsigned int pkts = 0;
620 unsigned int word3;
621 dma_addr_t mapping;
622
623 if (c == r)
624 return;
625
626 while (c != r) {
627 txd = txq->ring + c;
628 word0 = txd->word0;
629 word1 = txd->word1;
630 mapping = txd->word2.buf_adr;
631 word3 = txd->word3.bits32;
632
633 dma_unmap_single(geth->dev, mapping,
634 word0.bits.buffer_size, DMA_TO_DEVICE);
635
636 if (word3 & EOF_BIT)
637 dev_kfree_skb(txq->skb[c]);
638
639 c++;
640 c &= m;
641
642 if (!(word3 & SOF_BIT))
643 continue;
644
645 if (!word0.bits.status_tx_ok) {
646 errs++;
647 continue;
648 }
649
650 pkts++;
651 bytes += txd->word1.bits.byte_count;
652
653 if (word1.bits32 & TSS_CHECKUM_ENABLE)
654 hwchksum++;
655
656 nfrags = word0.bits.desc_count - 1;
657 if (nfrags) {
658 if (nfrags >= TX_MAX_FRAGS)
659 nfrags = TX_MAX_FRAGS - 1;
660
661 u64_stats_update_begin(&port->tx_stats_syncp);
662 port->tx_frag_stats[nfrags]++;
663 u64_stats_update_end(&port->tx_stats_syncp);
664 }
665 }
666
667 u64_stats_update_begin(&port->ir_stats_syncp);
668 port->stats.tx_errors += errs;
669 port->stats.tx_packets += pkts;
670 port->stats.tx_bytes += bytes;
671 port->tx_hw_csummed += hwchksum;
672 u64_stats_update_end(&port->ir_stats_syncp);
673
674 txq->cptr = c;
675 }
676
677 static void gmac_cleanup_txqs(struct net_device *netdev)
678 {
679 struct gemini_ethernet_port *port = netdev_priv(netdev);
680 unsigned int n_txq = netdev->num_tx_queues;
681 struct gemini_ethernet *geth = port->geth;
682 void __iomem *rwptr_reg;
683 unsigned int r, i;
684
685 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
686
687 for (i = 0; i < n_txq; i++) {
688 r = readw(rwptr_reg);
689 rwptr_reg += 2;
690 writew(r, rwptr_reg);
691 rwptr_reg += 2;
692
693 gmac_clean_txq(netdev, port->txq + i, r);
694 }
695 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
696
697 kfree(port->txq->skb);
698 dma_free_coherent(geth->dev,
699 n_txq * sizeof(*port->txq->ring) << port->txq_order,
700 port->txq->ring, port->txq_dma_base);
701 }
702
703 static int gmac_setup_rxq(struct net_device *netdev)
704 {
705 struct gemini_ethernet_port *port = netdev_priv(netdev);
706 struct gemini_ethernet *geth = port->geth;
707 struct nontoe_qhdr __iomem *qhdr;
708
709 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
710 port->rxq_rwptr = &qhdr->word1;
711
712 /* Remap a slew of memory to use for the RX queue */
713 port->rxq_ring = dma_alloc_coherent(geth->dev,
714 sizeof(*port->rxq_ring) << port->rxq_order,
715 &port->rxq_dma_base, GFP_KERNEL);
716 if (!port->rxq_ring)
717 return -ENOMEM;
718 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
719 dev_warn(geth->dev, "RX queue base is not aligned\n");
720 return -ENOMEM;
721 }
722
723 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
724 writel(0, port->rxq_rwptr);
725 return 0;
726 }
727
728 static struct gmac_queue_page *
729 gmac_get_queue_page(struct gemini_ethernet *geth,
730 struct gemini_ethernet_port *port,
731 dma_addr_t addr)
732 {
733 struct gmac_queue_page *gpage;
734 dma_addr_t mapping;
735 int i;
736
737 /* Only look for even pages */
738 mapping = addr & PAGE_MASK;
739
740 if (!geth->freeq_pages) {
741 dev_err(geth->dev, "try to get page with no page list\n");
742 return NULL;
743 }
744
745 /* Look up a ring buffer page from virtual mapping */
746 for (i = 0; i < geth->num_freeq_pages; i++) {
747 gpage = &geth->freeq_pages[i];
748 if (gpage->mapping == mapping)
749 return gpage;
750 }
751
752 return NULL;
753 }
754
755 static void gmac_cleanup_rxq(struct net_device *netdev)
756 {
757 struct gemini_ethernet_port *port = netdev_priv(netdev);
758 struct gemini_ethernet *geth = port->geth;
759 struct gmac_rxdesc *rxd = port->rxq_ring;
760 static struct gmac_queue_page *gpage;
761 struct nontoe_qhdr __iomem *qhdr;
762 void __iomem *dma_reg;
763 void __iomem *ptr_reg;
764 dma_addr_t mapping;
765 union dma_rwptr rw;
766 unsigned int r, w;
767
768 qhdr = geth->base +
769 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
770 dma_reg = &qhdr->word0;
771 ptr_reg = &qhdr->word1;
772
773 rw.bits32 = readl(ptr_reg);
774 r = rw.bits.rptr;
775 w = rw.bits.wptr;
776 writew(r, ptr_reg + 2);
777
778 writel(0, dma_reg);
779
780 /* Loop from read pointer to write pointer of the RX queue
781 * and free up all pages by the queue.
782 */
783 while (r != w) {
784 mapping = rxd[r].word2.buf_adr;
785 r++;
786 r &= ((1 << port->rxq_order) - 1);
787
788 if (!mapping)
789 continue;
790
791 /* Freeq pointers are one page off */
792 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
793 if (!gpage) {
794 dev_err(geth->dev, "could not find page\n");
795 continue;
796 }
797 /* Release the RX queue reference to the page */
798 put_page(gpage->page);
799 }
800
801 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
802 port->rxq_ring, port->rxq_dma_base);
803 }
804
805 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
806 int pn)
807 {
808 struct gmac_rxdesc *freeq_entry;
809 struct gmac_queue_page *gpage;
810 unsigned int fpp_order;
811 unsigned int frag_len;
812 dma_addr_t mapping;
813 struct page *page;
814 int i;
815
816 /* First allocate and DMA map a single page */
817 page = alloc_page(GFP_ATOMIC);
818 if (!page)
819 return NULL;
820
821 mapping = dma_map_single(geth->dev, page_address(page),
822 PAGE_SIZE, DMA_FROM_DEVICE);
823 if (dma_mapping_error(geth->dev, mapping)) {
824 put_page(page);
825 return NULL;
826 }
827
828 /* The assign the page mapping (physical address) to the buffer address
829 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
830 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
831 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
832 * each page normally needs two entries in the queue.
833 */
834 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
835 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
836 freeq_entry = geth->freeq_ring + (pn << fpp_order);
837 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
838 pn, frag_len, (1 << fpp_order), freeq_entry);
839 for (i = (1 << fpp_order); i > 0; i--) {
840 freeq_entry->word2.buf_adr = mapping;
841 freeq_entry++;
842 mapping += frag_len;
843 }
844
845 /* If the freeq entry already has a page mapped, then unmap it. */
846 gpage = &geth->freeq_pages[pn];
847 if (gpage->page) {
848 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
849 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
850 /* This should be the last reference to the page so it gets
851 * released
852 */
853 put_page(gpage->page);
854 }
855
856 /* Then put our new mapping into the page table */
857 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
858 pn, (unsigned int)mapping, page);
859 gpage->mapping = mapping;
860 gpage->page = page;
861
862 return page;
863 }
864
865 /**
866 * geth_fill_freeq() - Fill the freeq with empty fragments to use
867 * @geth: the ethernet adapter
868 * @refill: whether to reset the queue by filling in all freeq entries or
869 * just refill it, usually the interrupt to refill the queue happens when
870 * the queue is half empty.
871 */
872 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
873 {
874 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
875 unsigned int count = 0;
876 unsigned int pn, epn;
877 unsigned long flags;
878 union dma_rwptr rw;
879 unsigned int m_pn;
880
881 /* Mask for page */
882 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
883
884 spin_lock_irqsave(&geth->freeq_lock, flags);
885
886 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
887 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
888 epn = (rw.bits.rptr >> fpp_order) - 1;
889 epn &= m_pn;
890
891 /* Loop over the freeq ring buffer entries */
892 while (pn != epn) {
893 struct gmac_queue_page *gpage;
894 struct page *page;
895
896 gpage = &geth->freeq_pages[pn];
897 page = gpage->page;
898
899 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
900 pn, page_ref_count(page), 1 << fpp_order);
901
902 if (page_ref_count(page) > 1) {
903 unsigned int fl = (pn - epn) & m_pn;
904
905 if (fl > 64 >> fpp_order)
906 break;
907
908 page = geth_freeq_alloc_map_page(geth, pn);
909 if (!page)
910 break;
911 }
912
913 /* Add one reference per fragment in the page */
914 page_ref_add(page, 1 << fpp_order);
915 count += 1 << fpp_order;
916 pn++;
917 pn &= m_pn;
918 }
919
920 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
921
922 spin_unlock_irqrestore(&geth->freeq_lock, flags);
923
924 return count;
925 }
926
927 static int geth_setup_freeq(struct gemini_ethernet *geth)
928 {
929 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
930 unsigned int frag_len = 1 << geth->freeq_frag_order;
931 unsigned int len = 1 << geth->freeq_order;
932 unsigned int pages = len >> fpp_order;
933 union queue_threshold qt;
934 union dma_skb_size skbsz;
935 unsigned int filled;
936 unsigned int pn;
937
938 geth->freeq_ring = dma_alloc_coherent(geth->dev,
939 sizeof(*geth->freeq_ring) << geth->freeq_order,
940 &geth->freeq_dma_base, GFP_KERNEL);
941 if (!geth->freeq_ring)
942 return -ENOMEM;
943 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
944 dev_warn(geth->dev, "queue ring base is not aligned\n");
945 goto err_freeq;
946 }
947
948 /* Allocate a mapping to page look-up index */
949 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
950 GFP_KERNEL);
951 if (!geth->freeq_pages)
952 goto err_freeq;
953 geth->num_freeq_pages = pages;
954
955 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
956 for (pn = 0; pn < pages; pn++)
957 if (!geth_freeq_alloc_map_page(geth, pn))
958 goto err_freeq_alloc;
959
960 filled = geth_fill_freeq(geth, false);
961 if (!filled)
962 goto err_freeq_alloc;
963
964 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
965 qt.bits.swfq_empty = 32;
966 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
967
968 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
969 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
970 writel(geth->freeq_dma_base | geth->freeq_order,
971 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
972
973 return 0;
974
975 err_freeq_alloc:
976 while (pn > 0) {
977 struct gmac_queue_page *gpage;
978 dma_addr_t mapping;
979
980 --pn;
981 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
982 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
983 gpage = &geth->freeq_pages[pn];
984 put_page(gpage->page);
985 }
986
987 kfree(geth->freeq_pages);
988 err_freeq:
989 dma_free_coherent(geth->dev,
990 sizeof(*geth->freeq_ring) << geth->freeq_order,
991 geth->freeq_ring, geth->freeq_dma_base);
992 geth->freeq_ring = NULL;
993 return -ENOMEM;
994 }
995
996 /**
997 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
998 * @geth: the Gemini global ethernet state
999 */
1000 static void geth_cleanup_freeq(struct gemini_ethernet *geth)
1001 {
1002 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
1003 unsigned int frag_len = 1 << geth->freeq_frag_order;
1004 unsigned int len = 1 << geth->freeq_order;
1005 unsigned int pages = len >> fpp_order;
1006 unsigned int pn;
1007
1008 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1009 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1010 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1011
1012 for (pn = 0; pn < pages; pn++) {
1013 struct gmac_queue_page *gpage;
1014 dma_addr_t mapping;
1015
1016 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1017 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1018
1019 gpage = &geth->freeq_pages[pn];
1020 while (page_ref_count(gpage->page) > 0)
1021 put_page(gpage->page);
1022 }
1023
1024 kfree(geth->freeq_pages);
1025
1026 dma_free_coherent(geth->dev,
1027 sizeof(*geth->freeq_ring) << geth->freeq_order,
1028 geth->freeq_ring, geth->freeq_dma_base);
1029 }
1030
1031 /**
1032 * geth_resize_freeq() - resize the software queue depth
1033 * @port: the port requesting the change
1034 *
1035 * This gets called at least once during probe() so the device queue gets
1036 * "resized" from the hardware defaults. Since both ports/net devices share
1037 * the same hardware queue, some synchronization between the ports is
1038 * needed.
1039 */
1040 static int geth_resize_freeq(struct gemini_ethernet_port *port)
1041 {
1042 struct gemini_ethernet *geth = port->geth;
1043 struct net_device *netdev = port->netdev;
1044 struct gemini_ethernet_port *other_port;
1045 struct net_device *other_netdev;
1046 unsigned int new_size = 0;
1047 unsigned int new_order;
1048 unsigned long flags;
1049 u32 en;
1050 int ret;
1051
1052 if (netdev->dev_id == 0)
1053 other_netdev = geth->port1->netdev;
1054 else
1055 other_netdev = geth->port0->netdev;
1056
1057 if (other_netdev && netif_running(other_netdev))
1058 return -EBUSY;
1059
1060 new_size = 1 << (port->rxq_order + 1);
1061 netdev_dbg(netdev, "port %d size: %d order %d\n",
1062 netdev->dev_id,
1063 new_size,
1064 port->rxq_order);
1065 if (other_netdev) {
1066 other_port = netdev_priv(other_netdev);
1067 new_size += 1 << (other_port->rxq_order + 1);
1068 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1069 other_netdev->dev_id,
1070 (1 << (other_port->rxq_order + 1)),
1071 other_port->rxq_order);
1072 }
1073
1074 new_order = min(15, ilog2(new_size - 1) + 1);
1075 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1076 new_size, new_order);
1077 if (geth->freeq_order == new_order)
1078 return 0;
1079
1080 spin_lock_irqsave(&geth->irq_lock, flags);
1081
1082 /* Disable the software queue IRQs */
1083 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1084 en &= ~SWFQ_EMPTY_INT_BIT;
1085 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1086 spin_unlock_irqrestore(&geth->irq_lock, flags);
1087
1088 /* Drop the old queue */
1089 if (geth->freeq_ring)
1090 geth_cleanup_freeq(geth);
1091
1092 /* Allocate a new queue with the desired order */
1093 geth->freeq_order = new_order;
1094 ret = geth_setup_freeq(geth);
1095
1096 /* Restart the interrupts - NOTE if this is the first resize
1097 * after probe(), this is where the interrupts get turned on
1098 * in the first place.
1099 */
1100 spin_lock_irqsave(&geth->irq_lock, flags);
1101 en |= SWFQ_EMPTY_INT_BIT;
1102 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1103 spin_unlock_irqrestore(&geth->irq_lock, flags);
1104
1105 return ret;
1106 }
1107
1108 static void gmac_tx_irq_enable(struct net_device *netdev,
1109 unsigned int txq, int en)
1110 {
1111 struct gemini_ethernet_port *port = netdev_priv(netdev);
1112 struct gemini_ethernet *geth = port->geth;
1113 u32 val, mask;
1114
1115 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1116
1117 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1118
1119 if (en)
1120 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1121
1122 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1123 val = en ? val | mask : val & ~mask;
1124 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1125 }
1126
1127 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1128 {
1129 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1130
1131 gmac_tx_irq_enable(netdev, txq_num, 0);
1132 netif_tx_wake_queue(ntxq);
1133 }
1134
1135 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1136 struct gmac_txq *txq, unsigned short *desc)
1137 {
1138 struct gemini_ethernet_port *port = netdev_priv(netdev);
1139 struct skb_shared_info *skb_si = skb_shinfo(skb);
1140 unsigned short m = (1 << port->txq_order) - 1;
1141 short frag, last_frag = skb_si->nr_frags - 1;
1142 struct gemini_ethernet *geth = port->geth;
1143 unsigned int word1, word3, buflen;
1144 unsigned short w = *desc;
1145 struct gmac_txdesc *txd;
1146 skb_frag_t *skb_frag;
1147 dma_addr_t mapping;
1148 unsigned short mtu;
1149 void *buffer;
1150
1151 mtu = ETH_HLEN;
1152 mtu += netdev->mtu;
1153 if (skb->protocol == htons(ETH_P_8021Q))
1154 mtu += VLAN_HLEN;
1155
1156 word1 = skb->len;
1157 word3 = SOF_BIT;
1158
1159 if (word1 > mtu) {
1160 word1 |= TSS_MTU_ENABLE_BIT;
1161 word3 |= mtu;
1162 }
1163
1164 if (skb->ip_summed != CHECKSUM_NONE) {
1165 int tcp = 0;
1166
1167 if (skb->protocol == htons(ETH_P_IP)) {
1168 word1 |= TSS_IP_CHKSUM_BIT;
1169 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1170 } else { /* IPv6 */
1171 word1 |= TSS_IPV6_ENABLE_BIT;
1172 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1173 }
1174
1175 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1176 }
1177
1178 frag = -1;
1179 while (frag <= last_frag) {
1180 if (frag == -1) {
1181 buffer = skb->data;
1182 buflen = skb_headlen(skb);
1183 } else {
1184 skb_frag = skb_si->frags + frag;
1185 buffer = page_address(skb_frag_page(skb_frag)) +
1186 skb_frag->page_offset;
1187 buflen = skb_frag->size;
1188 }
1189
1190 if (frag == last_frag) {
1191 word3 |= EOF_BIT;
1192 txq->skb[w] = skb;
1193 }
1194
1195 mapping = dma_map_single(geth->dev, buffer, buflen,
1196 DMA_TO_DEVICE);
1197 if (dma_mapping_error(geth->dev, mapping))
1198 goto map_error;
1199
1200 txd = txq->ring + w;
1201 txd->word0.bits32 = buflen;
1202 txd->word1.bits32 = word1;
1203 txd->word2.buf_adr = mapping;
1204 txd->word3.bits32 = word3;
1205
1206 word3 &= MTU_SIZE_BIT_MASK;
1207 w++;
1208 w &= m;
1209 frag++;
1210 }
1211
1212 *desc = w;
1213 return 0;
1214
1215 map_error:
1216 while (w != *desc) {
1217 w--;
1218 w &= m;
1219
1220 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1221 txq->ring[w].word0.bits.buffer_size,
1222 DMA_TO_DEVICE);
1223 }
1224 return -ENOMEM;
1225 }
1226
1227 static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1228 {
1229 struct gemini_ethernet_port *port = netdev_priv(netdev);
1230 unsigned short m = (1 << port->txq_order) - 1;
1231 struct netdev_queue *ntxq;
1232 unsigned short r, w, d;
1233 void __iomem *ptr_reg;
1234 struct gmac_txq *txq;
1235 int txq_num, nfrags;
1236 union dma_rwptr rw;
1237
1238 SKB_FRAG_ASSERT(skb);
1239
1240 if (skb->len >= 0x10000)
1241 goto out_drop_free;
1242
1243 txq_num = skb_get_queue_mapping(skb);
1244 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1245 txq = &port->txq[txq_num];
1246 ntxq = netdev_get_tx_queue(netdev, txq_num);
1247 nfrags = skb_shinfo(skb)->nr_frags;
1248
1249 rw.bits32 = readl(ptr_reg);
1250 r = rw.bits.rptr;
1251 w = rw.bits.wptr;
1252
1253 d = txq->cptr - w - 1;
1254 d &= m;
1255
1256 if (d < nfrags + 2) {
1257 gmac_clean_txq(netdev, txq, r);
1258 d = txq->cptr - w - 1;
1259 d &= m;
1260
1261 if (d < nfrags + 2) {
1262 netif_tx_stop_queue(ntxq);
1263
1264 d = txq->cptr + nfrags + 16;
1265 d &= m;
1266 txq->ring[d].word3.bits.eofie = 1;
1267 gmac_tx_irq_enable(netdev, txq_num, 1);
1268
1269 u64_stats_update_begin(&port->tx_stats_syncp);
1270 netdev->stats.tx_fifo_errors++;
1271 u64_stats_update_end(&port->tx_stats_syncp);
1272 return NETDEV_TX_BUSY;
1273 }
1274 }
1275
1276 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1277 if (skb_linearize(skb))
1278 goto out_drop;
1279
1280 u64_stats_update_begin(&port->tx_stats_syncp);
1281 port->tx_frags_linearized++;
1282 u64_stats_update_end(&port->tx_stats_syncp);
1283
1284 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1285 goto out_drop_free;
1286 }
1287
1288 writew(w, ptr_reg + 2);
1289
1290 gmac_clean_txq(netdev, txq, r);
1291 return NETDEV_TX_OK;
1292
1293 out_drop_free:
1294 dev_kfree_skb(skb);
1295 out_drop:
1296 u64_stats_update_begin(&port->tx_stats_syncp);
1297 port->stats.tx_dropped++;
1298 u64_stats_update_end(&port->tx_stats_syncp);
1299 return NETDEV_TX_OK;
1300 }
1301
1302 static void gmac_tx_timeout(struct net_device *netdev)
1303 {
1304 netdev_err(netdev, "Tx timeout\n");
1305 gmac_dump_dma_state(netdev);
1306 }
1307
1308 static void gmac_enable_irq(struct net_device *netdev, int enable)
1309 {
1310 struct gemini_ethernet_port *port = netdev_priv(netdev);
1311 struct gemini_ethernet *geth = port->geth;
1312 unsigned long flags;
1313 u32 val, mask;
1314
1315 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1316 netdev->dev_id, enable ? "enable" : "disable");
1317 spin_lock_irqsave(&geth->irq_lock, flags);
1318
1319 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1320 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1321 val = enable ? (val | mask) : (val & ~mask);
1322 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1323
1324 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1325 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1326 val = enable ? (val | mask) : (val & ~mask);
1327 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1328
1329 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1330 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1331 val = enable ? (val | mask) : (val & ~mask);
1332 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1333
1334 spin_unlock_irqrestore(&geth->irq_lock, flags);
1335 }
1336
1337 static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1338 {
1339 struct gemini_ethernet_port *port = netdev_priv(netdev);
1340 struct gemini_ethernet *geth = port->geth;
1341 unsigned long flags;
1342 u32 val, mask;
1343
1344 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1345 enable ? "enable" : "disable");
1346 spin_lock_irqsave(&geth->irq_lock, flags);
1347 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1348
1349 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1350 val = enable ? (val | mask) : (val & ~mask);
1351 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1352
1353 spin_unlock_irqrestore(&geth->irq_lock, flags);
1354 }
1355
1356 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1357 union gmac_rxdesc_0 word0,
1358 unsigned int frame_len)
1359 {
1360 unsigned int rx_csum = word0.bits.chksum_status;
1361 unsigned int rx_status = word0.bits.status;
1362 struct sk_buff *skb = NULL;
1363
1364 port->rx_stats[rx_status]++;
1365 port->rx_csum_stats[rx_csum]++;
1366
1367 if (word0.bits.derr || word0.bits.perr ||
1368 rx_status || frame_len < ETH_ZLEN ||
1369 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1370 port->stats.rx_errors++;
1371
1372 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1373 port->stats.rx_length_errors++;
1374 if (RX_ERROR_OVER(rx_status))
1375 port->stats.rx_over_errors++;
1376 if (RX_ERROR_CRC(rx_status))
1377 port->stats.rx_crc_errors++;
1378 if (RX_ERROR_FRAME(rx_status))
1379 port->stats.rx_frame_errors++;
1380 return NULL;
1381 }
1382
1383 skb = napi_get_frags(&port->napi);
1384 if (!skb)
1385 goto update_exit;
1386
1387 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1388 skb->ip_summed = CHECKSUM_UNNECESSARY;
1389
1390 update_exit:
1391 port->stats.rx_bytes += frame_len;
1392 port->stats.rx_packets++;
1393 return skb;
1394 }
1395
1396 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1397 {
1398 struct gemini_ethernet_port *port = netdev_priv(netdev);
1399 unsigned short m = (1 << port->rxq_order) - 1;
1400 struct gemini_ethernet *geth = port->geth;
1401 void __iomem *ptr_reg = port->rxq_rwptr;
1402 unsigned int frame_len, frag_len;
1403 struct gmac_rxdesc *rx = NULL;
1404 struct gmac_queue_page *gpage;
1405 static struct sk_buff *skb;
1406 union gmac_rxdesc_0 word0;
1407 union gmac_rxdesc_1 word1;
1408 union gmac_rxdesc_3 word3;
1409 struct page *page = NULL;
1410 unsigned int page_offs;
1411 unsigned short r, w;
1412 union dma_rwptr rw;
1413 dma_addr_t mapping;
1414 int frag_nr = 0;
1415
1416 rw.bits32 = readl(ptr_reg);
1417 /* Reset interrupt as all packages until here are taken into account */
1418 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1419 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1420 r = rw.bits.rptr;
1421 w = rw.bits.wptr;
1422
1423 while (budget && w != r) {
1424 rx = port->rxq_ring + r;
1425 word0 = rx->word0;
1426 word1 = rx->word1;
1427 mapping = rx->word2.buf_adr;
1428 word3 = rx->word3;
1429
1430 r++;
1431 r &= m;
1432
1433 frag_len = word0.bits.buffer_size;
1434 frame_len = word1.bits.byte_count;
1435 page_offs = mapping & ~PAGE_MASK;
1436
1437 if (!mapping) {
1438 netdev_err(netdev,
1439 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1440 goto err_drop;
1441 }
1442
1443 /* Freeq pointers are one page off */
1444 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1445 if (!gpage) {
1446 dev_err(geth->dev, "could not find mapping\n");
1447 continue;
1448 }
1449 page = gpage->page;
1450
1451 if (word3.bits32 & SOF_BIT) {
1452 if (skb) {
1453 napi_free_frags(&port->napi);
1454 port->stats.rx_dropped++;
1455 }
1456
1457 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1458 if (!skb)
1459 goto err_drop;
1460
1461 page_offs += NET_IP_ALIGN;
1462 frag_len -= NET_IP_ALIGN;
1463 frag_nr = 0;
1464
1465 } else if (!skb) {
1466 put_page(page);
1467 continue;
1468 }
1469
1470 if (word3.bits32 & EOF_BIT)
1471 frag_len = frame_len - skb->len;
1472
1473 /* append page frag to skb */
1474 if (frag_nr == MAX_SKB_FRAGS)
1475 goto err_drop;
1476
1477 if (frag_len == 0)
1478 netdev_err(netdev, "Received fragment with len = 0\n");
1479
1480 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1481 skb->len += frag_len;
1482 skb->data_len += frag_len;
1483 skb->truesize += frag_len;
1484 frag_nr++;
1485
1486 if (word3.bits32 & EOF_BIT) {
1487 napi_gro_frags(&port->napi);
1488 skb = NULL;
1489 --budget;
1490 }
1491 continue;
1492
1493 err_drop:
1494 if (skb) {
1495 napi_free_frags(&port->napi);
1496 skb = NULL;
1497 }
1498
1499 if (mapping)
1500 put_page(page);
1501
1502 port->stats.rx_dropped++;
1503 }
1504
1505 writew(r, ptr_reg);
1506 return budget;
1507 }
1508
1509 static int gmac_napi_poll(struct napi_struct *napi, int budget)
1510 {
1511 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1512 struct gemini_ethernet *geth = port->geth;
1513 unsigned int freeq_threshold;
1514 unsigned int received;
1515
1516 freeq_threshold = 1 << (geth->freeq_order - 1);
1517 u64_stats_update_begin(&port->rx_stats_syncp);
1518
1519 received = gmac_rx(napi->dev, budget);
1520 if (received < budget) {
1521 napi_gro_flush(napi, false);
1522 napi_complete_done(napi, received);
1523 gmac_enable_rx_irq(napi->dev, 1);
1524 ++port->rx_napi_exits;
1525 }
1526
1527 port->freeq_refill += (budget - received);
1528 if (port->freeq_refill > freeq_threshold) {
1529 port->freeq_refill -= freeq_threshold;
1530 geth_fill_freeq(geth, true);
1531 }
1532
1533 u64_stats_update_end(&port->rx_stats_syncp);
1534 return received;
1535 }
1536
1537 static void gmac_dump_dma_state(struct net_device *netdev)
1538 {
1539 struct gemini_ethernet_port *port = netdev_priv(netdev);
1540 struct gemini_ethernet *geth = port->geth;
1541 void __iomem *ptr_reg;
1542 u32 reg[5];
1543
1544 /* Interrupt status */
1545 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1546 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1547 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1548 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1549 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1550 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1551 reg[0], reg[1], reg[2], reg[3], reg[4]);
1552
1553 /* Interrupt enable */
1554 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1555 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1556 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1557 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1558 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1559 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1560 reg[0], reg[1], reg[2], reg[3], reg[4]);
1561
1562 /* RX DMA status */
1563 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1564 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1565 reg[2] = GET_RPTR(port->rxq_rwptr);
1566 reg[3] = GET_WPTR(port->rxq_rwptr);
1567 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1568 reg[0], reg[1], reg[2], reg[3]);
1569
1570 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1571 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1572 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1573 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1574 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1575 reg[0], reg[1], reg[2], reg[3]);
1576
1577 /* TX DMA status */
1578 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1579
1580 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1581 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1582 reg[2] = GET_RPTR(ptr_reg);
1583 reg[3] = GET_WPTR(ptr_reg);
1584 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1585 reg[0], reg[1], reg[2], reg[3]);
1586
1587 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1588 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1589 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1590 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1591 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1592 reg[0], reg[1], reg[2], reg[3]);
1593
1594 /* FREE queues status */
1595 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1596
1597 reg[0] = GET_RPTR(ptr_reg);
1598 reg[1] = GET_WPTR(ptr_reg);
1599
1600 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1601
1602 reg[2] = GET_RPTR(ptr_reg);
1603 reg[3] = GET_WPTR(ptr_reg);
1604 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1605 reg[0], reg[1], reg[2], reg[3]);
1606 }
1607
1608 static void gmac_update_hw_stats(struct net_device *netdev)
1609 {
1610 struct gemini_ethernet_port *port = netdev_priv(netdev);
1611 unsigned int rx_discards, rx_mcast, rx_bcast;
1612 struct gemini_ethernet *geth = port->geth;
1613 unsigned long flags;
1614
1615 spin_lock_irqsave(&geth->irq_lock, flags);
1616 u64_stats_update_begin(&port->ir_stats_syncp);
1617
1618 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1619 port->hw_stats[0] += rx_discards;
1620 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1621 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1622 port->hw_stats[2] += rx_mcast;
1623 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1624 port->hw_stats[3] += rx_bcast;
1625 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1626 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1627
1628 port->stats.rx_missed_errors += rx_discards;
1629 port->stats.multicast += rx_mcast;
1630 port->stats.multicast += rx_bcast;
1631
1632 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1633 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1634
1635 u64_stats_update_end(&port->ir_stats_syncp);
1636 spin_unlock_irqrestore(&geth->irq_lock, flags);
1637 }
1638
1639 /**
1640 * gmac_get_intr_flags() - get interrupt status flags for a port from
1641 * @netdev: the net device for the port to get flags from
1642 * @i: the interrupt status register 0..4
1643 */
1644 static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1645 {
1646 struct gemini_ethernet_port *port = netdev_priv(netdev);
1647 struct gemini_ethernet *geth = port->geth;
1648 void __iomem *irqif_reg, *irqen_reg;
1649 unsigned int offs, val;
1650
1651 /* Calculate the offset using the stride of the status registers */
1652 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1653 GLOBAL_INTERRUPT_STATUS_0_REG);
1654
1655 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1656 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1657
1658 val = readl(irqif_reg) & readl(irqen_reg);
1659 return val;
1660 }
1661
1662 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1663 {
1664 struct gemini_ethernet_port *port =
1665 container_of(timer, struct gemini_ethernet_port,
1666 rx_coalesce_timer);
1667
1668 napi_schedule(&port->napi);
1669 return HRTIMER_NORESTART;
1670 }
1671
1672 static irqreturn_t gmac_irq(int irq, void *data)
1673 {
1674 struct gemini_ethernet_port *port;
1675 struct net_device *netdev = data;
1676 struct gemini_ethernet *geth;
1677 u32 val, orr = 0;
1678
1679 port = netdev_priv(netdev);
1680 geth = port->geth;
1681
1682 val = gmac_get_intr_flags(netdev, 0);
1683 orr |= val;
1684
1685 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1686 /* Oh, crap */
1687 netdev_err(netdev, "hw failure/sw bug\n");
1688 gmac_dump_dma_state(netdev);
1689
1690 /* don't know how to recover, just reduce losses */
1691 gmac_enable_irq(netdev, 0);
1692 return IRQ_HANDLED;
1693 }
1694
1695 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1696 gmac_tx_irq(netdev, 0);
1697
1698 val = gmac_get_intr_flags(netdev, 1);
1699 orr |= val;
1700
1701 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1702 gmac_enable_rx_irq(netdev, 0);
1703
1704 if (!port->rx_coalesce_nsecs) {
1705 napi_schedule(&port->napi);
1706 } else {
1707 ktime_t ktime;
1708
1709 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1710 hrtimer_start(&port->rx_coalesce_timer, ktime,
1711 HRTIMER_MODE_REL);
1712 }
1713 }
1714
1715 val = gmac_get_intr_flags(netdev, 4);
1716 orr |= val;
1717
1718 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1719 gmac_update_hw_stats(netdev);
1720
1721 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1722 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1723 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1724
1725 spin_lock(&geth->irq_lock);
1726 u64_stats_update_begin(&port->ir_stats_syncp);
1727 ++port->stats.rx_fifo_errors;
1728 u64_stats_update_end(&port->ir_stats_syncp);
1729 spin_unlock(&geth->irq_lock);
1730 }
1731
1732 return orr ? IRQ_HANDLED : IRQ_NONE;
1733 }
1734
1735 static void gmac_start_dma(struct gemini_ethernet_port *port)
1736 {
1737 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1738 union gmac_dma_ctrl dma_ctrl;
1739
1740 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1741 dma_ctrl.bits.rd_enable = 1;
1742 dma_ctrl.bits.td_enable = 1;
1743 dma_ctrl.bits.loopback = 0;
1744 dma_ctrl.bits.drop_small_ack = 0;
1745 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1746 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1747 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1748 dma_ctrl.bits.rd_bus = HSIZE_8;
1749 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1750 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1751 dma_ctrl.bits.td_bus = HSIZE_8;
1752
1753 writel(dma_ctrl.bits32, dma_ctrl_reg);
1754 }
1755
1756 static void gmac_stop_dma(struct gemini_ethernet_port *port)
1757 {
1758 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1759 union gmac_dma_ctrl dma_ctrl;
1760
1761 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1762 dma_ctrl.bits.rd_enable = 0;
1763 dma_ctrl.bits.td_enable = 0;
1764 writel(dma_ctrl.bits32, dma_ctrl_reg);
1765 }
1766
1767 static int gmac_open(struct net_device *netdev)
1768 {
1769 struct gemini_ethernet_port *port = netdev_priv(netdev);
1770 int err;
1771
1772 if (!netdev->phydev) {
1773 err = gmac_setup_phy(netdev);
1774 if (err) {
1775 netif_err(port, ifup, netdev,
1776 "PHY init failed: %d\n", err);
1777 return err;
1778 }
1779 }
1780
1781 err = request_irq(netdev->irq, gmac_irq,
1782 IRQF_SHARED, netdev->name, netdev);
1783 if (err) {
1784 netdev_err(netdev, "no IRQ\n");
1785 return err;
1786 }
1787
1788 netif_carrier_off(netdev);
1789 phy_start(netdev->phydev);
1790
1791 err = geth_resize_freeq(port);
1792 /* It's fine if it's just busy, the other port has set up
1793 * the freeq in that case.
1794 */
1795 if (err && (err != -EBUSY)) {
1796 netdev_err(netdev, "could not resize freeq\n");
1797 goto err_stop_phy;
1798 }
1799
1800 err = gmac_setup_rxq(netdev);
1801 if (err) {
1802 netdev_err(netdev, "could not setup RXQ\n");
1803 goto err_stop_phy;
1804 }
1805
1806 err = gmac_setup_txqs(netdev);
1807 if (err) {
1808 netdev_err(netdev, "could not setup TXQs\n");
1809 gmac_cleanup_rxq(netdev);
1810 goto err_stop_phy;
1811 }
1812
1813 napi_enable(&port->napi);
1814
1815 gmac_start_dma(port);
1816 gmac_enable_irq(netdev, 1);
1817 gmac_enable_tx_rx(netdev);
1818 netif_tx_start_all_queues(netdev);
1819
1820 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1821 HRTIMER_MODE_REL);
1822 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1823
1824 netdev_dbg(netdev, "opened\n");
1825
1826 return 0;
1827
1828 err_stop_phy:
1829 phy_stop(netdev->phydev);
1830 free_irq(netdev->irq, netdev);
1831 return err;
1832 }
1833
1834 static int gmac_stop(struct net_device *netdev)
1835 {
1836 struct gemini_ethernet_port *port = netdev_priv(netdev);
1837
1838 hrtimer_cancel(&port->rx_coalesce_timer);
1839 netif_tx_stop_all_queues(netdev);
1840 gmac_disable_tx_rx(netdev);
1841 gmac_stop_dma(port);
1842 napi_disable(&port->napi);
1843
1844 gmac_enable_irq(netdev, 0);
1845 gmac_cleanup_rxq(netdev);
1846 gmac_cleanup_txqs(netdev);
1847
1848 phy_stop(netdev->phydev);
1849 free_irq(netdev->irq, netdev);
1850
1851 gmac_update_hw_stats(netdev);
1852 return 0;
1853 }
1854
1855 static void gmac_set_rx_mode(struct net_device *netdev)
1856 {
1857 struct gemini_ethernet_port *port = netdev_priv(netdev);
1858 union gmac_rx_fltr filter = { .bits = {
1859 .broadcast = 1,
1860 .multicast = 1,
1861 .unicast = 1,
1862 } };
1863 struct netdev_hw_addr *ha;
1864 unsigned int bit_nr;
1865 u32 mc_filter[2];
1866
1867 mc_filter[1] = 0;
1868 mc_filter[0] = 0;
1869
1870 if (netdev->flags & IFF_PROMISC) {
1871 filter.bits.error = 1;
1872 filter.bits.promiscuous = 1;
1873 mc_filter[1] = ~0;
1874 mc_filter[0] = ~0;
1875 } else if (netdev->flags & IFF_ALLMULTI) {
1876 mc_filter[1] = ~0;
1877 mc_filter[0] = ~0;
1878 } else {
1879 netdev_for_each_mc_addr(ha, netdev) {
1880 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1881 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1882 }
1883 }
1884
1885 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1886 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1887 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1888 }
1889
1890 static void gmac_write_mac_address(struct net_device *netdev)
1891 {
1892 struct gemini_ethernet_port *port = netdev_priv(netdev);
1893 __le32 addr[3];
1894
1895 memset(addr, 0, sizeof(addr));
1896 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1897
1898 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1899 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1900 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1901 }
1902
1903 static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1904 {
1905 struct sockaddr *sa = addr;
1906
1907 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1908 gmac_write_mac_address(netdev);
1909
1910 return 0;
1911 }
1912
1913 static void gmac_clear_hw_stats(struct net_device *netdev)
1914 {
1915 struct gemini_ethernet_port *port = netdev_priv(netdev);
1916
1917 readl(port->gmac_base + GMAC_IN_DISCARDS);
1918 readl(port->gmac_base + GMAC_IN_ERRORS);
1919 readl(port->gmac_base + GMAC_IN_MCAST);
1920 readl(port->gmac_base + GMAC_IN_BCAST);
1921 readl(port->gmac_base + GMAC_IN_MAC1);
1922 readl(port->gmac_base + GMAC_IN_MAC2);
1923 }
1924
1925 static void gmac_get_stats64(struct net_device *netdev,
1926 struct rtnl_link_stats64 *stats)
1927 {
1928 struct gemini_ethernet_port *port = netdev_priv(netdev);
1929 unsigned int start;
1930
1931 gmac_update_hw_stats(netdev);
1932
1933 /* Racing with RX NAPI */
1934 do {
1935 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1936
1937 stats->rx_packets = port->stats.rx_packets;
1938 stats->rx_bytes = port->stats.rx_bytes;
1939 stats->rx_errors = port->stats.rx_errors;
1940 stats->rx_dropped = port->stats.rx_dropped;
1941
1942 stats->rx_length_errors = port->stats.rx_length_errors;
1943 stats->rx_over_errors = port->stats.rx_over_errors;
1944 stats->rx_crc_errors = port->stats.rx_crc_errors;
1945 stats->rx_frame_errors = port->stats.rx_frame_errors;
1946
1947 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1948
1949 /* Racing with MIB and TX completion interrupts */
1950 do {
1951 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1952
1953 stats->tx_errors = port->stats.tx_errors;
1954 stats->tx_packets = port->stats.tx_packets;
1955 stats->tx_bytes = port->stats.tx_bytes;
1956
1957 stats->multicast = port->stats.multicast;
1958 stats->rx_missed_errors = port->stats.rx_missed_errors;
1959 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1960
1961 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1962
1963 /* Racing with hard_start_xmit */
1964 do {
1965 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1966
1967 stats->tx_dropped = port->stats.tx_dropped;
1968
1969 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1970
1971 stats->rx_dropped += stats->rx_missed_errors;
1972 }
1973
1974 static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1975 {
1976 int max_len = gmac_pick_rx_max_len(new_mtu);
1977
1978 if (max_len < 0)
1979 return -EINVAL;
1980
1981 gmac_disable_tx_rx(netdev);
1982
1983 netdev->mtu = new_mtu;
1984 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1985 CONFIG0_MAXLEN_MASK);
1986
1987 netdev_update_features(netdev);
1988
1989 gmac_enable_tx_rx(netdev);
1990
1991 return 0;
1992 }
1993
1994 static netdev_features_t gmac_fix_features(struct net_device *netdev,
1995 netdev_features_t features)
1996 {
1997 if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1998 features &= ~GMAC_OFFLOAD_FEATURES;
1999
2000 return features;
2001 }
2002
2003 static int gmac_set_features(struct net_device *netdev,
2004 netdev_features_t features)
2005 {
2006 struct gemini_ethernet_port *port = netdev_priv(netdev);
2007 int enable = features & NETIF_F_RXCSUM;
2008 unsigned long flags;
2009 u32 reg;
2010
2011 spin_lock_irqsave(&port->config_lock, flags);
2012
2013 reg = readl(port->gmac_base + GMAC_CONFIG0);
2014 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2015 writel(reg, port->gmac_base + GMAC_CONFIG0);
2016
2017 spin_unlock_irqrestore(&port->config_lock, flags);
2018 return 0;
2019 }
2020
2021 static int gmac_get_sset_count(struct net_device *netdev, int sset)
2022 {
2023 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2024 }
2025
2026 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2027 {
2028 if (stringset != ETH_SS_STATS)
2029 return;
2030
2031 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2032 }
2033
2034 static void gmac_get_ethtool_stats(struct net_device *netdev,
2035 struct ethtool_stats *estats, u64 *values)
2036 {
2037 struct gemini_ethernet_port *port = netdev_priv(netdev);
2038 unsigned int start;
2039 u64 *p;
2040 int i;
2041
2042 gmac_update_hw_stats(netdev);
2043
2044 /* Racing with MIB interrupt */
2045 do {
2046 p = values;
2047 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2048
2049 for (i = 0; i < RX_STATS_NUM; i++)
2050 *p++ = port->hw_stats[i];
2051
2052 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2053 values = p;
2054
2055 /* Racing with RX NAPI */
2056 do {
2057 p = values;
2058 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2059
2060 for (i = 0; i < RX_STATUS_NUM; i++)
2061 *p++ = port->rx_stats[i];
2062 for (i = 0; i < RX_CHKSUM_NUM; i++)
2063 *p++ = port->rx_csum_stats[i];
2064 *p++ = port->rx_napi_exits;
2065
2066 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2067 values = p;
2068
2069 /* Racing with TX start_xmit */
2070 do {
2071 p = values;
2072 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2073
2074 for (i = 0; i < TX_MAX_FRAGS; i++) {
2075 *values++ = port->tx_frag_stats[i];
2076 port->tx_frag_stats[i] = 0;
2077 }
2078 *values++ = port->tx_frags_linearized;
2079 *values++ = port->tx_hw_csummed;
2080
2081 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2082 }
2083
2084 static int gmac_get_ksettings(struct net_device *netdev,
2085 struct ethtool_link_ksettings *cmd)
2086 {
2087 if (!netdev->phydev)
2088 return -ENXIO;
2089 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2090
2091 return 0;
2092 }
2093
2094 static int gmac_set_ksettings(struct net_device *netdev,
2095 const struct ethtool_link_ksettings *cmd)
2096 {
2097 if (!netdev->phydev)
2098 return -ENXIO;
2099 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2100 }
2101
2102 static int gmac_nway_reset(struct net_device *netdev)
2103 {
2104 if (!netdev->phydev)
2105 return -ENXIO;
2106 return phy_start_aneg(netdev->phydev);
2107 }
2108
2109 static void gmac_get_pauseparam(struct net_device *netdev,
2110 struct ethtool_pauseparam *pparam)
2111 {
2112 struct gemini_ethernet_port *port = netdev_priv(netdev);
2113 union gmac_config0 config0;
2114
2115 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2116
2117 pparam->rx_pause = config0.bits.rx_fc_en;
2118 pparam->tx_pause = config0.bits.tx_fc_en;
2119 pparam->autoneg = true;
2120 }
2121
2122 static void gmac_get_ringparam(struct net_device *netdev,
2123 struct ethtool_ringparam *rp)
2124 {
2125 struct gemini_ethernet_port *port = netdev_priv(netdev);
2126 union gmac_config0 config0;
2127
2128 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2129
2130 rp->rx_max_pending = 1 << 15;
2131 rp->rx_mini_max_pending = 0;
2132 rp->rx_jumbo_max_pending = 0;
2133 rp->tx_max_pending = 1 << 15;
2134
2135 rp->rx_pending = 1 << port->rxq_order;
2136 rp->rx_mini_pending = 0;
2137 rp->rx_jumbo_pending = 0;
2138 rp->tx_pending = 1 << port->txq_order;
2139 }
2140
2141 static int gmac_set_ringparam(struct net_device *netdev,
2142 struct ethtool_ringparam *rp)
2143 {
2144 struct gemini_ethernet_port *port = netdev_priv(netdev);
2145 int err = 0;
2146
2147 if (netif_running(netdev))
2148 return -EBUSY;
2149
2150 if (rp->rx_pending) {
2151 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2152 err = geth_resize_freeq(port);
2153 }
2154 if (rp->tx_pending) {
2155 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2156 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2157 }
2158
2159 return err;
2160 }
2161
2162 static int gmac_get_coalesce(struct net_device *netdev,
2163 struct ethtool_coalesce *ecmd)
2164 {
2165 struct gemini_ethernet_port *port = netdev_priv(netdev);
2166
2167 ecmd->rx_max_coalesced_frames = 1;
2168 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2169 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2170
2171 return 0;
2172 }
2173
2174 static int gmac_set_coalesce(struct net_device *netdev,
2175 struct ethtool_coalesce *ecmd)
2176 {
2177 struct gemini_ethernet_port *port = netdev_priv(netdev);
2178
2179 if (ecmd->tx_max_coalesced_frames < 1)
2180 return -EINVAL;
2181 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2182 return -EINVAL;
2183
2184 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2185 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2186
2187 return 0;
2188 }
2189
2190 static u32 gmac_get_msglevel(struct net_device *netdev)
2191 {
2192 struct gemini_ethernet_port *port = netdev_priv(netdev);
2193
2194 return port->msg_enable;
2195 }
2196
2197 static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2198 {
2199 struct gemini_ethernet_port *port = netdev_priv(netdev);
2200
2201 port->msg_enable = level;
2202 }
2203
2204 static void gmac_get_drvinfo(struct net_device *netdev,
2205 struct ethtool_drvinfo *info)
2206 {
2207 strcpy(info->driver, DRV_NAME);
2208 strcpy(info->version, DRV_VERSION);
2209 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2210 }
2211
2212 static const struct net_device_ops gmac_351x_ops = {
2213 .ndo_init = gmac_init,
2214 .ndo_uninit = gmac_uninit,
2215 .ndo_open = gmac_open,
2216 .ndo_stop = gmac_stop,
2217 .ndo_start_xmit = gmac_start_xmit,
2218 .ndo_tx_timeout = gmac_tx_timeout,
2219 .ndo_set_rx_mode = gmac_set_rx_mode,
2220 .ndo_set_mac_address = gmac_set_mac_address,
2221 .ndo_get_stats64 = gmac_get_stats64,
2222 .ndo_change_mtu = gmac_change_mtu,
2223 .ndo_fix_features = gmac_fix_features,
2224 .ndo_set_features = gmac_set_features,
2225 };
2226
2227 static const struct ethtool_ops gmac_351x_ethtool_ops = {
2228 .get_sset_count = gmac_get_sset_count,
2229 .get_strings = gmac_get_strings,
2230 .get_ethtool_stats = gmac_get_ethtool_stats,
2231 .get_link = ethtool_op_get_link,
2232 .get_link_ksettings = gmac_get_ksettings,
2233 .set_link_ksettings = gmac_set_ksettings,
2234 .nway_reset = gmac_nway_reset,
2235 .get_pauseparam = gmac_get_pauseparam,
2236 .get_ringparam = gmac_get_ringparam,
2237 .set_ringparam = gmac_set_ringparam,
2238 .get_coalesce = gmac_get_coalesce,
2239 .set_coalesce = gmac_set_coalesce,
2240 .get_msglevel = gmac_get_msglevel,
2241 .set_msglevel = gmac_set_msglevel,
2242 .get_drvinfo = gmac_get_drvinfo,
2243 };
2244
2245 static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2246 {
2247 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2248 struct gemini_ethernet_port *port = data;
2249 struct gemini_ethernet *geth;
2250 unsigned long flags;
2251
2252 geth = port->geth;
2253 /* The queue is half empty so refill it */
2254 geth_fill_freeq(geth, true);
2255
2256 spin_lock_irqsave(&geth->irq_lock, flags);
2257 /* ACK queue interrupt */
2258 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2259 /* Enable queue interrupt again */
2260 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2261 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2262 spin_unlock_irqrestore(&geth->irq_lock, flags);
2263
2264 return IRQ_HANDLED;
2265 }
2266
2267 static irqreturn_t gemini_port_irq(int irq, void *data)
2268 {
2269 struct gemini_ethernet_port *port = data;
2270 struct gemini_ethernet *geth;
2271 irqreturn_t ret = IRQ_NONE;
2272 u32 val, en;
2273
2274 geth = port->geth;
2275 spin_lock(&geth->irq_lock);
2276
2277 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2278 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2279
2280 if (val & en & SWFQ_EMPTY_INT_BIT) {
2281 /* Disable the queue empty interrupt while we work on
2282 * processing the queue. Also disable overrun interrupts
2283 * as there is not much we can do about it here.
2284 */
2285 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2286 | GMAC1_RX_OVERRUN_INT_BIT);
2287 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2288 ret = IRQ_WAKE_THREAD;
2289 }
2290
2291 spin_unlock(&geth->irq_lock);
2292
2293 return ret;
2294 }
2295
2296 static void gemini_port_remove(struct gemini_ethernet_port *port)
2297 {
2298 if (port->netdev)
2299 unregister_netdev(port->netdev);
2300 clk_disable_unprepare(port->pclk);
2301 geth_cleanup_freeq(port->geth);
2302 }
2303
2304 static void gemini_ethernet_init(struct gemini_ethernet *geth)
2305 {
2306 /* Only do this once both ports are online */
2307 if (geth->initialized)
2308 return;
2309 if (geth->port0 && geth->port1)
2310 geth->initialized = true;
2311 else
2312 return;
2313
2314 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2315 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2316 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2317 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2318 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2319
2320 /* Interrupt config:
2321 *
2322 * GMAC0 intr bits ------> int0 ----> eth0
2323 * GMAC1 intr bits ------> int1 ----> eth1
2324 * TOE intr -------------> int1 ----> eth1
2325 * Classification Intr --> int0 ----> eth0
2326 * Default Q0 -----------> int0 ----> eth0
2327 * Default Q1 -----------> int1 ----> eth1
2328 * FreeQ intr -----------> int1 ----> eth1
2329 */
2330 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2331 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2332 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2333 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2334 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2335
2336 /* edge-triggered interrupts packed to level-triggered one... */
2337 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2338 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2339 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2340 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2341 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2342
2343 /* Set up queue */
2344 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2345 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2346 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2347 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2348
2349 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2350 /* This makes the queue resize on probe() so that we
2351 * set up and enable the queue IRQ. FIXME: fragile.
2352 */
2353 geth->freeq_order = 1;
2354 }
2355
2356 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2357 {
2358 port->mac_addr[0] =
2359 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2360 port->mac_addr[1] =
2361 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2362 port->mac_addr[2] =
2363 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2364 }
2365
2366 static int gemini_ethernet_port_probe(struct platform_device *pdev)
2367 {
2368 char *port_names[2] = { "ethernet0", "ethernet1" };
2369 struct gemini_ethernet_port *port;
2370 struct device *dev = &pdev->dev;
2371 struct gemini_ethernet *geth;
2372 struct net_device *netdev;
2373 struct resource *gmacres;
2374 struct resource *dmares;
2375 struct device *parent;
2376 unsigned int id;
2377 int irq;
2378 int ret;
2379
2380 parent = dev->parent;
2381 geth = dev_get_drvdata(parent);
2382
2383 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2384 id = 0;
2385 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2386 id = 1;
2387 else
2388 return -ENODEV;
2389
2390 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2391
2392 netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
2393 if (!netdev) {
2394 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2395 return -ENOMEM;
2396 }
2397
2398 port = netdev_priv(netdev);
2399 SET_NETDEV_DEV(netdev, dev);
2400 port->netdev = netdev;
2401 port->id = id;
2402 port->geth = geth;
2403 port->dev = dev;
2404 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2405
2406 /* DMA memory */
2407 dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2408 if (!dmares) {
2409 dev_err(dev, "no DMA resource\n");
2410 return -ENODEV;
2411 }
2412 port->dma_base = devm_ioremap_resource(dev, dmares);
2413 if (IS_ERR(port->dma_base))
2414 return PTR_ERR(port->dma_base);
2415
2416 /* GMAC config memory */
2417 gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2418 if (!gmacres) {
2419 dev_err(dev, "no GMAC resource\n");
2420 return -ENODEV;
2421 }
2422 port->gmac_base = devm_ioremap_resource(dev, gmacres);
2423 if (IS_ERR(port->gmac_base))
2424 return PTR_ERR(port->gmac_base);
2425
2426 /* Interrupt */
2427 irq = platform_get_irq(pdev, 0);
2428 if (irq <= 0) {
2429 dev_err(dev, "no IRQ\n");
2430 return irq ? irq : -ENODEV;
2431 }
2432 port->irq = irq;
2433
2434 /* Clock the port */
2435 port->pclk = devm_clk_get(dev, "PCLK");
2436 if (IS_ERR(port->pclk)) {
2437 dev_err(dev, "no PCLK\n");
2438 return PTR_ERR(port->pclk);
2439 }
2440 ret = clk_prepare_enable(port->pclk);
2441 if (ret)
2442 return ret;
2443
2444 /* Maybe there is a nice ethernet address we should use */
2445 gemini_port_save_mac_addr(port);
2446
2447 /* Reset the port */
2448 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2449 if (IS_ERR(port->reset)) {
2450 dev_err(dev, "no reset\n");
2451 return PTR_ERR(port->reset);
2452 }
2453 reset_control_reset(port->reset);
2454 usleep_range(100, 500);
2455
2456 /* Assign pointer in the main state container */
2457 if (!id)
2458 geth->port0 = port;
2459 else
2460 geth->port1 = port;
2461
2462 /* This will just be done once both ports are up and reset */
2463 gemini_ethernet_init(geth);
2464
2465 platform_set_drvdata(pdev, port);
2466
2467 /* Set up and register the netdev */
2468 netdev->dev_id = port->id;
2469 netdev->irq = irq;
2470 netdev->netdev_ops = &gmac_351x_ops;
2471 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2472
2473 spin_lock_init(&port->config_lock);
2474 gmac_clear_hw_stats(netdev);
2475
2476 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2477 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2478 /* We can handle jumbo frames up to 10236 bytes so, let's accept
2479 * payloads of 10236 bytes minus VLAN and ethernet header
2480 */
2481 netdev->min_mtu = ETH_MIN_MTU;
2482 netdev->max_mtu = 10236 - VLAN_ETH_HLEN;
2483
2484 port->freeq_refill = 0;
2485 netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2486 DEFAULT_NAPI_WEIGHT);
2487
2488 if (is_valid_ether_addr((void *)port->mac_addr)) {
2489 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2490 } else {
2491 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2492 port->mac_addr[0], port->mac_addr[1],
2493 port->mac_addr[2]);
2494 dev_info(dev, "using a random ethernet address\n");
2495 eth_random_addr(netdev->dev_addr);
2496 }
2497 gmac_write_mac_address(netdev);
2498
2499 ret = devm_request_threaded_irq(port->dev,
2500 port->irq,
2501 gemini_port_irq,
2502 gemini_port_irq_thread,
2503 IRQF_SHARED,
2504 port_names[port->id],
2505 port);
2506 if (ret)
2507 return ret;
2508
2509 ret = register_netdev(netdev);
2510 if (!ret) {
2511 netdev_info(netdev,
2512 "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
2513 port->irq, &dmares->start,
2514 &gmacres->start);
2515 ret = gmac_setup_phy(netdev);
2516 if (ret)
2517 netdev_info(netdev,
2518 "PHY init failed, deferring to ifup time\n");
2519 return 0;
2520 }
2521
2522 port->netdev = NULL;
2523 free_netdev(netdev);
2524 return ret;
2525 }
2526
2527 static int gemini_ethernet_port_remove(struct platform_device *pdev)
2528 {
2529 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2530
2531 gemini_port_remove(port);
2532 return 0;
2533 }
2534
2535 static const struct of_device_id gemini_ethernet_port_of_match[] = {
2536 {
2537 .compatible = "cortina,gemini-ethernet-port",
2538 },
2539 {},
2540 };
2541 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2542
2543 static struct platform_driver gemini_ethernet_port_driver = {
2544 .driver = {
2545 .name = "gemini-ethernet-port",
2546 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2547 },
2548 .probe = gemini_ethernet_port_probe,
2549 .remove = gemini_ethernet_port_remove,
2550 };
2551
2552 static int gemini_ethernet_probe(struct platform_device *pdev)
2553 {
2554 struct device *dev = &pdev->dev;
2555 struct gemini_ethernet *geth;
2556 unsigned int retry = 5;
2557 struct resource *res;
2558 u32 val;
2559
2560 /* Global registers */
2561 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2562 if (!geth)
2563 return -ENOMEM;
2564 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2565 if (!res)
2566 return -ENODEV;
2567 geth->base = devm_ioremap_resource(dev, res);
2568 if (IS_ERR(geth->base))
2569 return PTR_ERR(geth->base);
2570 geth->dev = dev;
2571
2572 /* Wait for ports to stabilize */
2573 do {
2574 udelay(2);
2575 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2576 barrier();
2577 } while (!val && --retry);
2578 if (!retry) {
2579 dev_err(dev, "failed to reset ethernet\n");
2580 return -EIO;
2581 }
2582 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2583 (val >> 4) & 0xFFFU, val & 0xFU);
2584
2585 spin_lock_init(&geth->irq_lock);
2586 spin_lock_init(&geth->freeq_lock);
2587
2588 /* The children will use this */
2589 platform_set_drvdata(pdev, geth);
2590
2591 /* Spawn child devices for the two ports */
2592 return devm_of_platform_populate(dev);
2593 }
2594
2595 static int gemini_ethernet_remove(struct platform_device *pdev)
2596 {
2597 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2598
2599 geth_cleanup_freeq(geth);
2600 geth->initialized = false;
2601
2602 return 0;
2603 }
2604
2605 static const struct of_device_id gemini_ethernet_of_match[] = {
2606 {
2607 .compatible = "cortina,gemini-ethernet",
2608 },
2609 {},
2610 };
2611 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2612
2613 static struct platform_driver gemini_ethernet_driver = {
2614 .driver = {
2615 .name = DRV_NAME,
2616 .of_match_table = of_match_ptr(gemini_ethernet_of_match),
2617 },
2618 .probe = gemini_ethernet_probe,
2619 .remove = gemini_ethernet_remove,
2620 };
2621
2622 static int __init gemini_ethernet_module_init(void)
2623 {
2624 int ret;
2625
2626 ret = platform_driver_register(&gemini_ethernet_port_driver);
2627 if (ret)
2628 return ret;
2629
2630 ret = platform_driver_register(&gemini_ethernet_driver);
2631 if (ret) {
2632 platform_driver_unregister(&gemini_ethernet_port_driver);
2633 return ret;
2634 }
2635
2636 return 0;
2637 }
2638 module_init(gemini_ethernet_module_init);
2639
2640 static void __exit gemini_ethernet_module_exit(void)
2641 {
2642 platform_driver_unregister(&gemini_ethernet_driver);
2643 platform_driver_unregister(&gemini_ethernet_port_driver);
2644 }
2645 module_exit(gemini_ethernet_module_exit);
2646
2647 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2648 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2649 MODULE_LICENSE("GPL");
2650 MODULE_ALIAS("platform:" DRV_NAME);
Linux with added FPC-III support