?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / ethernet / sun / niu.c
blob6f99437a696203849344de81e381c7839ca4c0ee
1 // SPDX-License-Identifier: GPL-2.0
2 /* niu.c: Neptune ethernet driver.
3 *
4 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/netdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/bitops.h>
20 #include <linux/mii.h>
21 #include <linux/if.h>
22 #include <linux/if_ether.h>
23 #include <linux/if_vlan.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/ipv6.h>
27 #include <linux/log2.h>
28 #include <linux/jiffies.h>
29 #include <linux/crc32.h>
30 #include <linux/list.h>
31 #include <linux/slab.h>
32
33 #include <linux/io.h>
34 #include <linux/of_device.h>
35
36 #include "niu.h"
37
38 #define DRV_MODULE_NAME "niu"
39 #define DRV_MODULE_VERSION "1.1"
40 #define DRV_MODULE_RELDATE "Apr 22, 2010"
41
42 static char version[] =
43 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44
45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
46 MODULE_DESCRIPTION("NIU ethernet driver");
47 MODULE_LICENSE("GPL");
48 MODULE_VERSION(DRV_MODULE_VERSION);
49
50 #ifndef readq
51 static u64 readq(void __iomem *reg)
52 {
53 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
54 }
55
56 static void writeq(u64 val, void __iomem *reg)
57 {
58 writel(val & 0xffffffff, reg);
59 writel(val >> 32, reg + 0x4UL);
60 }
61 #endif
62
63 static const struct pci_device_id niu_pci_tbl[] = {
64 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
65 {}
66 };
67
68 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69
70 #define NIU_TX_TIMEOUT (5 * HZ)
71
72 #define nr64(reg) readq(np->regs + (reg))
73 #define nw64(reg, val) writeq((val), np->regs + (reg))
74
75 #define nr64_mac(reg) readq(np->mac_regs + (reg))
76 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77
78 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
79 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80
81 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
82 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83
84 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
85 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86
87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
88
89 static int niu_debug;
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "NIU debug level");
93
94 #define niu_lock_parent(np, flags) \
95 spin_lock_irqsave(&np->parent->lock, flags)
96 #define niu_unlock_parent(np, flags) \
97 spin_unlock_irqrestore(&np->parent->lock, flags)
98
99 static int serdes_init_10g_serdes(struct niu *np);
100
101 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
102 u64 bits, int limit, int delay)
103 {
104 while (--limit >= 0) {
105 u64 val = nr64_mac(reg);
106
107 if (!(val & bits))
108 break;
109 udelay(delay);
110 }
111 if (limit < 0)
112 return -ENODEV;
113 return 0;
114 }
115
116 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay,
118 const char *reg_name)
119 {
120 int err;
121
122 nw64_mac(reg, bits);
123 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 if (err)
125 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
126 (unsigned long long)bits, reg_name,
127 (unsigned long long)nr64_mac(reg));
128 return err;
129 }
130
131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
132 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
133 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
134 })
135
136 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
137 u64 bits, int limit, int delay)
138 {
139 while (--limit >= 0) {
140 u64 val = nr64_ipp(reg);
141
142 if (!(val & bits))
143 break;
144 udelay(delay);
145 }
146 if (limit < 0)
147 return -ENODEV;
148 return 0;
149 }
150
151 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
152 u64 bits, int limit, int delay,
153 const char *reg_name)
154 {
155 int err;
156 u64 val;
157
158 val = nr64_ipp(reg);
159 val |= bits;
160 nw64_ipp(reg, val);
161
162 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 if (err)
164 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
165 (unsigned long long)bits, reg_name,
166 (unsigned long long)nr64_ipp(reg));
167 return err;
168 }
169
170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
171 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
172 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
173 })
174
175 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
176 u64 bits, int limit, int delay)
177 {
178 while (--limit >= 0) {
179 u64 val = nr64(reg);
180
181 if (!(val & bits))
182 break;
183 udelay(delay);
184 }
185 if (limit < 0)
186 return -ENODEV;
187 return 0;
188 }
189
190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
191 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
192 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
193 })
194
195 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
196 u64 bits, int limit, int delay,
197 const char *reg_name)
198 {
199 int err;
200
201 nw64(reg, bits);
202 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 if (err)
204 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
205 (unsigned long long)bits, reg_name,
206 (unsigned long long)nr64(reg));
207 return err;
208 }
209
210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
211 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
212 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
213 })
214
215 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216 {
217 u64 val = (u64) lp->timer;
218
219 if (on)
220 val |= LDG_IMGMT_ARM;
221
222 nw64(LDG_IMGMT(lp->ldg_num), val);
223 }
224
225 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226 {
227 unsigned long mask_reg, bits;
228 u64 val;
229
230 if (ldn < 0 || ldn > LDN_MAX)
231 return -EINVAL;
232
233 if (ldn < 64) {
234 mask_reg = LD_IM0(ldn);
235 bits = LD_IM0_MASK;
236 } else {
237 mask_reg = LD_IM1(ldn - 64);
238 bits = LD_IM1_MASK;
239 }
240
241 val = nr64(mask_reg);
242 if (on)
243 val &= ~bits;
244 else
245 val |= bits;
246 nw64(mask_reg, val);
247
248 return 0;
249 }
250
251 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252 {
253 struct niu_parent *parent = np->parent;
254 int i;
255
256 for (i = 0; i <= LDN_MAX; i++) {
257 int err;
258
259 if (parent->ldg_map[i] != lp->ldg_num)
260 continue;
261
262 err = niu_ldn_irq_enable(np, i, on);
263 if (err)
264 return err;
265 }
266 return 0;
267 }
268
269 static int niu_enable_interrupts(struct niu *np, int on)
270 {
271 int i;
272
273 for (i = 0; i < np->num_ldg; i++) {
274 struct niu_ldg *lp = &np->ldg[i];
275 int err;
276
277 err = niu_enable_ldn_in_ldg(np, lp, on);
278 if (err)
279 return err;
280 }
281 for (i = 0; i < np->num_ldg; i++)
282 niu_ldg_rearm(np, &np->ldg[i], on);
283
284 return 0;
285 }
286
287 static u32 phy_encode(u32 type, int port)
288 {
289 return type << (port * 2);
290 }
291
292 static u32 phy_decode(u32 val, int port)
293 {
294 return (val >> (port * 2)) & PORT_TYPE_MASK;
295 }
296
297 static int mdio_wait(struct niu *np)
298 {
299 int limit = 1000;
300 u64 val;
301
302 while (--limit > 0) {
303 val = nr64(MIF_FRAME_OUTPUT);
304 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
305 return val & MIF_FRAME_OUTPUT_DATA;
306
307 udelay(10);
308 }
309
310 return -ENODEV;
311 }
312
313 static int mdio_read(struct niu *np, int port, int dev, int reg)
314 {
315 int err;
316
317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
318 err = mdio_wait(np);
319 if (err < 0)
320 return err;
321
322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
323 return mdio_wait(np);
324 }
325
326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
327 {
328 int err;
329
330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
331 err = mdio_wait(np);
332 if (err < 0)
333 return err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 return 0;
341 }
342
343 static int mii_read(struct niu *np, int port, int reg)
344 {
345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
346 return mdio_wait(np);
347 }
348
349 static int mii_write(struct niu *np, int port, int reg, int data)
350 {
351 int err;
352
353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359 }
360
361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
362 {
363 int err;
364
365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
366 ESR2_TI_PLL_TX_CFG_L(channel),
367 val & 0xffff);
368 if (!err)
369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
370 ESR2_TI_PLL_TX_CFG_H(channel),
371 val >> 16);
372 return err;
373 }
374
375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
376 {
377 int err;
378
379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
380 ESR2_TI_PLL_RX_CFG_L(channel),
381 val & 0xffff);
382 if (!err)
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_RX_CFG_H(channel),
385 val >> 16);
386 return err;
387 }
388
389 /* Mode is always 10G fiber. */
390 static int serdes_init_niu_10g_fiber(struct niu *np)
391 {
392 struct niu_link_config *lp = &np->link_config;
393 u32 tx_cfg, rx_cfg;
394 unsigned long i;
395
396 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
397 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
398 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
399 PLL_RX_CFG_EQ_LP_ADAPTIVE);
400
401 if (lp->loopback_mode == LOOPBACK_PHY) {
402 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403
404 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
405 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406
407 tx_cfg |= PLL_TX_CFG_ENTEST;
408 rx_cfg |= PLL_RX_CFG_ENTEST;
409 }
410
411 /* Initialize all 4 lanes of the SERDES. */
412 for (i = 0; i < 4; i++) {
413 int err = esr2_set_tx_cfg(np, i, tx_cfg);
414 if (err)
415 return err;
416 }
417
418 for (i = 0; i < 4; i++) {
419 int err = esr2_set_rx_cfg(np, i, rx_cfg);
420 if (err)
421 return err;
422 }
423
424 return 0;
425 }
426
427 static int serdes_init_niu_1g_serdes(struct niu *np)
428 {
429 struct niu_link_config *lp = &np->link_config;
430 u16 pll_cfg, pll_sts;
431 int max_retry = 100;
432 u64 uninitialized_var(sig), mask, val;
433 u32 tx_cfg, rx_cfg;
434 unsigned long i;
435 int err;
436
437 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
438 PLL_TX_CFG_RATE_HALF);
439 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
440 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
441 PLL_RX_CFG_RATE_HALF);
442
443 if (np->port == 0)
444 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445
446 if (lp->loopback_mode == LOOPBACK_PHY) {
447 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448
449 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
450 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451
452 tx_cfg |= PLL_TX_CFG_ENTEST;
453 rx_cfg |= PLL_RX_CFG_ENTEST;
454 }
455
456 /* Initialize PLL for 1G */
457 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458
459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
460 ESR2_TI_PLL_CFG_L, pll_cfg);
461 if (err) {
462 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
463 np->port, __func__);
464 return err;
465 }
466
467 pll_sts = PLL_CFG_ENPLL;
468
469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
470 ESR2_TI_PLL_STS_L, pll_sts);
471 if (err) {
472 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
473 np->port, __func__);
474 return err;
475 }
476
477 udelay(200);
478
479 /* Initialize all 4 lanes of the SERDES. */
480 for (i = 0; i < 4; i++) {
481 err = esr2_set_tx_cfg(np, i, tx_cfg);
482 if (err)
483 return err;
484 }
485
486 for (i = 0; i < 4; i++) {
487 err = esr2_set_rx_cfg(np, i, rx_cfg);
488 if (err)
489 return err;
490 }
491
492 switch (np->port) {
493 case 0:
494 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
495 mask = val;
496 break;
497
498 case 1:
499 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
500 mask = val;
501 break;
502
503 default:
504 return -EINVAL;
505 }
506
507 while (max_retry--) {
508 sig = nr64(ESR_INT_SIGNALS);
509 if ((sig & mask) == val)
510 break;
511
512 mdelay(500);
513 }
514
515 if ((sig & mask) != val) {
516 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
517 np->port, (int)(sig & mask), (int)val);
518 return -ENODEV;
519 }
520
521 return 0;
522 }
523
524 static int serdes_init_niu_10g_serdes(struct niu *np)
525 {
526 struct niu_link_config *lp = &np->link_config;
527 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528 int max_retry = 100;
529 u64 uninitialized_var(sig), mask, val;
530 unsigned long i;
531 int err;
532
533 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
534 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
535 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
536 PLL_RX_CFG_EQ_LP_ADAPTIVE);
537
538 if (lp->loopback_mode == LOOPBACK_PHY) {
539 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540
541 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
542 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543
544 tx_cfg |= PLL_TX_CFG_ENTEST;
545 rx_cfg |= PLL_RX_CFG_ENTEST;
546 }
547
548 /* Initialize PLL for 10G */
549 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550
551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
552 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553 if (err) {
554 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
555 np->port, __func__);
556 return err;
557 }
558
559 pll_sts = PLL_CFG_ENPLL;
560
561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
562 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563 if (err) {
564 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
565 np->port, __func__);
566 return err;
567 }
568
569 udelay(200);
570
571 /* Initialize all 4 lanes of the SERDES. */
572 for (i = 0; i < 4; i++) {
573 err = esr2_set_tx_cfg(np, i, tx_cfg);
574 if (err)
575 return err;
576 }
577
578 for (i = 0; i < 4; i++) {
579 err = esr2_set_rx_cfg(np, i, rx_cfg);
580 if (err)
581 return err;
582 }
583
584 /* check if serdes is ready */
585
586 switch (np->port) {
587 case 0:
588 mask = ESR_INT_SIGNALS_P0_BITS;
589 val = (ESR_INT_SRDY0_P0 |
590 ESR_INT_DET0_P0 |
591 ESR_INT_XSRDY_P0 |
592 ESR_INT_XDP_P0_CH3 |
593 ESR_INT_XDP_P0_CH2 |
594 ESR_INT_XDP_P0_CH1 |
595 ESR_INT_XDP_P0_CH0);
596 break;
597
598 case 1:
599 mask = ESR_INT_SIGNALS_P1_BITS;
600 val = (ESR_INT_SRDY0_P1 |
601 ESR_INT_DET0_P1 |
602 ESR_INT_XSRDY_P1 |
603 ESR_INT_XDP_P1_CH3 |
604 ESR_INT_XDP_P1_CH2 |
605 ESR_INT_XDP_P1_CH1 |
606 ESR_INT_XDP_P1_CH0);
607 break;
608
609 default:
610 return -EINVAL;
611 }
612
613 while (max_retry--) {
614 sig = nr64(ESR_INT_SIGNALS);
615 if ((sig & mask) == val)
616 break;
617
618 mdelay(500);
619 }
620
621 if ((sig & mask) != val) {
622 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
623 np->port, (int)(sig & mask), (int)val);
624
625 /* 10G failed, try initializing at 1G */
626 err = serdes_init_niu_1g_serdes(np);
627 if (!err) {
628 np->flags &= ~NIU_FLAGS_10G;
629 np->mac_xcvr = MAC_XCVR_PCS;
630 } else {
631 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
632 np->port);
633 return -ENODEV;
634 }
635 }
636 return 0;
637 }
638
639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
640 {
641 int err;
642
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 if (err >= 0) {
645 *val = (err & 0xffff);
646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
647 ESR_RXTX_CTRL_H(chan));
648 if (err >= 0)
649 *val |= ((err & 0xffff) << 16);
650 err = 0;
651 }
652 return err;
653 }
654
655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
656 {
657 int err;
658
659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
660 ESR_GLUE_CTRL0_L(chan));
661 if (err >= 0) {
662 *val = (err & 0xffff);
663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
664 ESR_GLUE_CTRL0_H(chan));
665 if (err >= 0) {
666 *val |= ((err & 0xffff) << 16);
667 err = 0;
668 }
669 }
670 return err;
671 }
672
673 static int esr_read_reset(struct niu *np, u32 *val)
674 {
675 int err;
676
677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
678 ESR_RXTX_RESET_CTRL_L);
679 if (err >= 0) {
680 *val = (err & 0xffff);
681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
682 ESR_RXTX_RESET_CTRL_H);
683 if (err >= 0) {
684 *val |= ((err & 0xffff) << 16);
685 err = 0;
686 }
687 }
688 return err;
689 }
690
691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
692 {
693 int err;
694
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_L(chan), val & 0xffff);
697 if (!err)
698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
699 ESR_RXTX_CTRL_H(chan), (val >> 16));
700 return err;
701 }
702
703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
704 {
705 int err;
706
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709 if (!err)
710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
711 ESR_GLUE_CTRL0_H(chan), (val >> 16));
712 return err;
713 }
714
715 static int esr_reset(struct niu *np)
716 {
717 u32 uninitialized_var(reset);
718 int err;
719
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
721 ESR_RXTX_RESET_CTRL_L, 0x0000);
722 if (err)
723 return err;
724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
725 ESR_RXTX_RESET_CTRL_H, 0xffff);
726 if (err)
727 return err;
728 udelay(200);
729
730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
731 ESR_RXTX_RESET_CTRL_L, 0xffff);
732 if (err)
733 return err;
734 udelay(200);
735
736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
737 ESR_RXTX_RESET_CTRL_H, 0x0000);
738 if (err)
739 return err;
740 udelay(200);
741
742 err = esr_read_reset(np, &reset);
743 if (err)
744 return err;
745 if (reset != 0) {
746 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
747 np->port, reset);
748 return -ENODEV;
749 }
750
751 return 0;
752 }
753
754 static int serdes_init_10g(struct niu *np)
755 {
756 struct niu_link_config *lp = &np->link_config;
757 unsigned long ctrl_reg, test_cfg_reg, i;
758 u64 ctrl_val, test_cfg_val, sig, mask, val;
759 int err;
760
761 switch (np->port) {
762 case 0:
763 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
764 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
765 break;
766 case 1:
767 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
768 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
769 break;
770
771 default:
772 return -EINVAL;
773 }
774 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
775 ENET_SERDES_CTRL_SDET_1 |
776 ENET_SERDES_CTRL_SDET_2 |
777 ENET_SERDES_CTRL_SDET_3 |
778 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
781 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
785 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
786 test_cfg_val = 0;
787
788 if (lp->loopback_mode == LOOPBACK_PHY) {
789 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
790 ENET_SERDES_TEST_MD_0_SHIFT) |
791 (ENET_TEST_MD_PAD_LOOPBACK <<
792 ENET_SERDES_TEST_MD_1_SHIFT) |
793 (ENET_TEST_MD_PAD_LOOPBACK <<
794 ENET_SERDES_TEST_MD_2_SHIFT) |
795 (ENET_TEST_MD_PAD_LOOPBACK <<
796 ENET_SERDES_TEST_MD_3_SHIFT));
797 }
798
799 nw64(ctrl_reg, ctrl_val);
800 nw64(test_cfg_reg, test_cfg_val);
801
802 /* Initialize all 4 lanes of the SERDES. */
803 for (i = 0; i < 4; i++) {
804 u32 rxtx_ctrl, glue0;
805
806 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807 if (err)
808 return err;
809 err = esr_read_glue0(np, i, &glue0);
810 if (err)
811 return err;
812
813 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
814 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
815 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816
817 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
818 ESR_GLUE_CTRL0_THCNT |
819 ESR_GLUE_CTRL0_BLTIME);
820 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
821 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
822 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
823 (BLTIME_300_CYCLES <<
824 ESR_GLUE_CTRL0_BLTIME_SHIFT));
825
826 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827 if (err)
828 return err;
829 err = esr_write_glue0(np, i, glue0);
830 if (err)
831 return err;
832 }
833
834 err = esr_reset(np);
835 if (err)
836 return err;
837
838 sig = nr64(ESR_INT_SIGNALS);
839 switch (np->port) {
840 case 0:
841 mask = ESR_INT_SIGNALS_P0_BITS;
842 val = (ESR_INT_SRDY0_P0 |
843 ESR_INT_DET0_P0 |
844 ESR_INT_XSRDY_P0 |
845 ESR_INT_XDP_P0_CH3 |
846 ESR_INT_XDP_P0_CH2 |
847 ESR_INT_XDP_P0_CH1 |
848 ESR_INT_XDP_P0_CH0);
849 break;
850
851 case 1:
852 mask = ESR_INT_SIGNALS_P1_BITS;
853 val = (ESR_INT_SRDY0_P1 |
854 ESR_INT_DET0_P1 |
855 ESR_INT_XSRDY_P1 |
856 ESR_INT_XDP_P1_CH3 |
857 ESR_INT_XDP_P1_CH2 |
858 ESR_INT_XDP_P1_CH1 |
859 ESR_INT_XDP_P1_CH0);
860 break;
861
862 default:
863 return -EINVAL;
864 }
865
866 if ((sig & mask) != val) {
867 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
868 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
869 return 0;
870 }
871 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
872 np->port, (int)(sig & mask), (int)val);
873 return -ENODEV;
874 }
875 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
876 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
877 return 0;
878 }
879
880 static int serdes_init_1g(struct niu *np)
881 {
882 u64 val;
883
884 val = nr64(ENET_SERDES_1_PLL_CFG);
885 val &= ~ENET_SERDES_PLL_FBDIV2;
886 switch (np->port) {
887 case 0:
888 val |= ENET_SERDES_PLL_HRATE0;
889 break;
890 case 1:
891 val |= ENET_SERDES_PLL_HRATE1;
892 break;
893 case 2:
894 val |= ENET_SERDES_PLL_HRATE2;
895 break;
896 case 3:
897 val |= ENET_SERDES_PLL_HRATE3;
898 break;
899 default:
900 return -EINVAL;
901 }
902 nw64(ENET_SERDES_1_PLL_CFG, val);
903
904 return 0;
905 }
906
907 static int serdes_init_1g_serdes(struct niu *np)
908 {
909 struct niu_link_config *lp = &np->link_config;
910 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
911 u64 ctrl_val, test_cfg_val, sig, mask, val;
912 int err;
913 u64 reset_val, val_rd;
914
915 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
916 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
917 ENET_SERDES_PLL_FBDIV0;
918 switch (np->port) {
919 case 0:
920 reset_val = ENET_SERDES_RESET_0;
921 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
922 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
923 pll_cfg = ENET_SERDES_0_PLL_CFG;
924 break;
925 case 1:
926 reset_val = ENET_SERDES_RESET_1;
927 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
928 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
929 pll_cfg = ENET_SERDES_1_PLL_CFG;
930 break;
931
932 default:
933 return -EINVAL;
934 }
935 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
936 ENET_SERDES_CTRL_SDET_1 |
937 ENET_SERDES_CTRL_SDET_2 |
938 ENET_SERDES_CTRL_SDET_3 |
939 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
942 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
946 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
947 test_cfg_val = 0;
948
949 if (lp->loopback_mode == LOOPBACK_PHY) {
950 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
951 ENET_SERDES_TEST_MD_0_SHIFT) |
952 (ENET_TEST_MD_PAD_LOOPBACK <<
953 ENET_SERDES_TEST_MD_1_SHIFT) |
954 (ENET_TEST_MD_PAD_LOOPBACK <<
955 ENET_SERDES_TEST_MD_2_SHIFT) |
956 (ENET_TEST_MD_PAD_LOOPBACK <<
957 ENET_SERDES_TEST_MD_3_SHIFT));
958 }
959
960 nw64(ENET_SERDES_RESET, reset_val);
961 mdelay(20);
962 val_rd = nr64(ENET_SERDES_RESET);
963 val_rd &= ~reset_val;
964 nw64(pll_cfg, val);
965 nw64(ctrl_reg, ctrl_val);
966 nw64(test_cfg_reg, test_cfg_val);
967 nw64(ENET_SERDES_RESET, val_rd);
968 mdelay(2000);
969
970 /* Initialize all 4 lanes of the SERDES. */
971 for (i = 0; i < 4; i++) {
972 u32 rxtx_ctrl, glue0;
973
974 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975 if (err)
976 return err;
977 err = esr_read_glue0(np, i, &glue0);
978 if (err)
979 return err;
980
981 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
982 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
983 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984
985 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
986 ESR_GLUE_CTRL0_THCNT |
987 ESR_GLUE_CTRL0_BLTIME);
988 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
989 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
990 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
991 (BLTIME_300_CYCLES <<
992 ESR_GLUE_CTRL0_BLTIME_SHIFT));
993
994 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995 if (err)
996 return err;
997 err = esr_write_glue0(np, i, glue0);
998 if (err)
999 return err;
1000 }
1001
1002
1003 sig = nr64(ESR_INT_SIGNALS);
1004 switch (np->port) {
1005 case 0:
1006 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007 mask = val;
1008 break;
1009
1010 case 1:
1011 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012 mask = val;
1013 break;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 if ((sig & mask) != val) {
1020 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021 np->port, (int)(sig & mask), (int)val);
1022 return -ENODEV;
1023 }
1024
1025 return 0;
1026 }
1027
1028 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 {
1030 struct niu_link_config *lp = &np->link_config;
1031 int link_up;
1032 u64 val;
1033 u16 current_speed;
1034 unsigned long flags;
1035 u8 current_duplex;
1036
1037 link_up = 0;
1038 current_speed = SPEED_INVALID;
1039 current_duplex = DUPLEX_INVALID;
1040
1041 spin_lock_irqsave(&np->lock, flags);
1042
1043 val = nr64_pcs(PCS_MII_STAT);
1044
1045 if (val & PCS_MII_STAT_LINK_STATUS) {
1046 link_up = 1;
1047 current_speed = SPEED_1000;
1048 current_duplex = DUPLEX_FULL;
1049 }
1050
1051 lp->active_speed = current_speed;
1052 lp->active_duplex = current_duplex;
1053 spin_unlock_irqrestore(&np->lock, flags);
1054
1055 *link_up_p = link_up;
1056 return 0;
1057 }
1058
1059 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 {
1061 unsigned long flags;
1062 struct niu_link_config *lp = &np->link_config;
1063 int link_up = 0;
1064 int link_ok = 1;
1065 u64 val, val2;
1066 u16 current_speed;
1067 u8 current_duplex;
1068
1069 if (!(np->flags & NIU_FLAGS_10G))
1070 return link_status_1g_serdes(np, link_up_p);
1071
1072 current_speed = SPEED_INVALID;
1073 current_duplex = DUPLEX_INVALID;
1074 spin_lock_irqsave(&np->lock, flags);
1075
1076 val = nr64_xpcs(XPCS_STATUS(0));
1077 val2 = nr64_mac(XMAC_INTER2);
1078 if (val2 & 0x01000000)
1079 link_ok = 0;
1080
1081 if ((val & 0x1000ULL) && link_ok) {
1082 link_up = 1;
1083 current_speed = SPEED_10000;
1084 current_duplex = DUPLEX_FULL;
1085 }
1086 lp->active_speed = current_speed;
1087 lp->active_duplex = current_duplex;
1088 spin_unlock_irqrestore(&np->lock, flags);
1089 *link_up_p = link_up;
1090 return 0;
1091 }
1092
1093 static int link_status_mii(struct niu *np, int *link_up_p)
1094 {
1095 struct niu_link_config *lp = &np->link_config;
1096 int err;
1097 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098 int supported, advertising, active_speed, active_duplex;
1099
1100 err = mii_read(np, np->phy_addr, MII_BMCR);
1101 if (unlikely(err < 0))
1102 return err;
1103 bmcr = err;
1104
1105 err = mii_read(np, np->phy_addr, MII_BMSR);
1106 if (unlikely(err < 0))
1107 return err;
1108 bmsr = err;
1109
1110 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111 if (unlikely(err < 0))
1112 return err;
1113 advert = err;
1114
1115 err = mii_read(np, np->phy_addr, MII_LPA);
1116 if (unlikely(err < 0))
1117 return err;
1118 lpa = err;
1119
1120 if (likely(bmsr & BMSR_ESTATEN)) {
1121 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122 if (unlikely(err < 0))
1123 return err;
1124 estatus = err;
1125
1126 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127 if (unlikely(err < 0))
1128 return err;
1129 ctrl1000 = err;
1130
1131 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132 if (unlikely(err < 0))
1133 return err;
1134 stat1000 = err;
1135 } else
1136 estatus = ctrl1000 = stat1000 = 0;
1137
1138 supported = 0;
1139 if (bmsr & BMSR_ANEGCAPABLE)
1140 supported |= SUPPORTED_Autoneg;
1141 if (bmsr & BMSR_10HALF)
1142 supported |= SUPPORTED_10baseT_Half;
1143 if (bmsr & BMSR_10FULL)
1144 supported |= SUPPORTED_10baseT_Full;
1145 if (bmsr & BMSR_100HALF)
1146 supported |= SUPPORTED_100baseT_Half;
1147 if (bmsr & BMSR_100FULL)
1148 supported |= SUPPORTED_100baseT_Full;
1149 if (estatus & ESTATUS_1000_THALF)
1150 supported |= SUPPORTED_1000baseT_Half;
1151 if (estatus & ESTATUS_1000_TFULL)
1152 supported |= SUPPORTED_1000baseT_Full;
1153 lp->supported = supported;
1154
1155 advertising = mii_adv_to_ethtool_adv_t(advert);
1156 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1157
1158 if (bmcr & BMCR_ANENABLE) {
1159 int neg, neg1000;
1160
1161 lp->active_autoneg = 1;
1162 advertising |= ADVERTISED_Autoneg;
1163
1164 neg = advert & lpa;
1165 neg1000 = (ctrl1000 << 2) & stat1000;
1166
1167 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1168 active_speed = SPEED_1000;
1169 else if (neg & LPA_100)
1170 active_speed = SPEED_100;
1171 else if (neg & (LPA_10HALF | LPA_10FULL))
1172 active_speed = SPEED_10;
1173 else
1174 active_speed = SPEED_INVALID;
1175
1176 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1177 active_duplex = DUPLEX_FULL;
1178 else if (active_speed != SPEED_INVALID)
1179 active_duplex = DUPLEX_HALF;
1180 else
1181 active_duplex = DUPLEX_INVALID;
1182 } else {
1183 lp->active_autoneg = 0;
1184
1185 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1186 active_speed = SPEED_1000;
1187 else if (bmcr & BMCR_SPEED100)
1188 active_speed = SPEED_100;
1189 else
1190 active_speed = SPEED_10;
1191
1192 if (bmcr & BMCR_FULLDPLX)
1193 active_duplex = DUPLEX_FULL;
1194 else
1195 active_duplex = DUPLEX_HALF;
1196 }
1197
1198 lp->active_advertising = advertising;
1199 lp->active_speed = active_speed;
1200 lp->active_duplex = active_duplex;
1201 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1202
1203 return 0;
1204 }
1205
1206 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1207 {
1208 struct niu_link_config *lp = &np->link_config;
1209 u16 current_speed, bmsr;
1210 unsigned long flags;
1211 u8 current_duplex;
1212 int err, link_up;
1213
1214 link_up = 0;
1215 current_speed = SPEED_INVALID;
1216 current_duplex = DUPLEX_INVALID;
1217
1218 spin_lock_irqsave(&np->lock, flags);
1219
1220 err = -EINVAL;
1221
1222 err = mii_read(np, np->phy_addr, MII_BMSR);
1223 if (err < 0)
1224 goto out;
1225
1226 bmsr = err;
1227 if (bmsr & BMSR_LSTATUS) {
1228 link_up = 1;
1229 current_speed = SPEED_1000;
1230 current_duplex = DUPLEX_FULL;
1231 }
1232 lp->active_speed = current_speed;
1233 lp->active_duplex = current_duplex;
1234 err = 0;
1235
1236 out:
1237 spin_unlock_irqrestore(&np->lock, flags);
1238
1239 *link_up_p = link_up;
1240 return err;
1241 }
1242
1243 static int link_status_1g(struct niu *np, int *link_up_p)
1244 {
1245 struct niu_link_config *lp = &np->link_config;
1246 unsigned long flags;
1247 int err;
1248
1249 spin_lock_irqsave(&np->lock, flags);
1250
1251 err = link_status_mii(np, link_up_p);
1252 lp->supported |= SUPPORTED_TP;
1253 lp->active_advertising |= ADVERTISED_TP;
1254
1255 spin_unlock_irqrestore(&np->lock, flags);
1256 return err;
1257 }
1258
1259 static int bcm8704_reset(struct niu *np)
1260 {
1261 int err, limit;
1262
1263 err = mdio_read(np, np->phy_addr,
1264 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1265 if (err < 0 || err == 0xffff)
1266 return err;
1267 err |= BMCR_RESET;
1268 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1269 MII_BMCR, err);
1270 if (err)
1271 return err;
1272
1273 limit = 1000;
1274 while (--limit >= 0) {
1275 err = mdio_read(np, np->phy_addr,
1276 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1277 if (err < 0)
1278 return err;
1279 if (!(err & BMCR_RESET))
1280 break;
1281 }
1282 if (limit < 0) {
1283 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1284 np->port, (err & 0xffff));
1285 return -ENODEV;
1286 }
1287 return 0;
1288 }
1289
1290 /* When written, certain PHY registers need to be read back twice
1291 * in order for the bits to settle properly.
1292 */
1293 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1294 {
1295 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1296 if (err < 0)
1297 return err;
1298 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1299 if (err < 0)
1300 return err;
1301 return 0;
1302 }
1303
1304 static int bcm8706_init_user_dev3(struct niu *np)
1305 {
1306 int err;
1307
1308
1309 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1310 BCM8704_USER_OPT_DIGITAL_CTRL);
1311 if (err < 0)
1312 return err;
1313 err &= ~USER_ODIG_CTRL_GPIOS;
1314 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1315 err |= USER_ODIG_CTRL_RESV2;
1316 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1317 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1318 if (err)
1319 return err;
1320
1321 mdelay(1000);
1322
1323 return 0;
1324 }
1325
1326 static int bcm8704_init_user_dev3(struct niu *np)
1327 {
1328 int err;
1329
1330 err = mdio_write(np, np->phy_addr,
1331 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1332 (USER_CONTROL_OPTXRST_LVL |
1333 USER_CONTROL_OPBIASFLT_LVL |
1334 USER_CONTROL_OBTMPFLT_LVL |
1335 USER_CONTROL_OPPRFLT_LVL |
1336 USER_CONTROL_OPTXFLT_LVL |
1337 USER_CONTROL_OPRXLOS_LVL |
1338 USER_CONTROL_OPRXFLT_LVL |
1339 USER_CONTROL_OPTXON_LVL |
1340 (0x3f << USER_CONTROL_RES1_SHIFT)));
1341 if (err)
1342 return err;
1343
1344 err = mdio_write(np, np->phy_addr,
1345 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1346 (USER_PMD_TX_CTL_XFP_CLKEN |
1347 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1348 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1349 USER_PMD_TX_CTL_TSCK_LPWREN));
1350 if (err)
1351 return err;
1352
1353 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1354 if (err)
1355 return err;
1356 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1357 if (err)
1358 return err;
1359
1360 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1361 BCM8704_USER_OPT_DIGITAL_CTRL);
1362 if (err < 0)
1363 return err;
1364 err &= ~USER_ODIG_CTRL_GPIOS;
1365 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1366 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1367 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1368 if (err)
1369 return err;
1370
1371 mdelay(1000);
1372
1373 return 0;
1374 }
1375
1376 static int mrvl88x2011_act_led(struct niu *np, int val)
1377 {
1378 int err;
1379
1380 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1381 MRVL88X2011_LED_8_TO_11_CTL);
1382 if (err < 0)
1383 return err;
1384
1385 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1386 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1387
1388 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1389 MRVL88X2011_LED_8_TO_11_CTL, err);
1390 }
1391
1392 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1393 {
1394 int err;
1395
1396 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1397 MRVL88X2011_LED_BLINK_CTL);
1398 if (err >= 0) {
1399 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1400 err |= (rate << 4);
1401
1402 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1403 MRVL88X2011_LED_BLINK_CTL, err);
1404 }
1405
1406 return err;
1407 }
1408
1409 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1410 {
1411 int err;
1412
1413 /* Set LED functions */
1414 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1415 if (err)
1416 return err;
1417
1418 /* led activity */
1419 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1420 if (err)
1421 return err;
1422
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1424 MRVL88X2011_GENERAL_CTL);
1425 if (err < 0)
1426 return err;
1427
1428 err |= MRVL88X2011_ENA_XFPREFCLK;
1429
1430 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1431 MRVL88X2011_GENERAL_CTL, err);
1432 if (err < 0)
1433 return err;
1434
1435 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1436 MRVL88X2011_PMA_PMD_CTL_1);
1437 if (err < 0)
1438 return err;
1439
1440 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1441 err |= MRVL88X2011_LOOPBACK;
1442 else
1443 err &= ~MRVL88X2011_LOOPBACK;
1444
1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1446 MRVL88X2011_PMA_PMD_CTL_1, err);
1447 if (err < 0)
1448 return err;
1449
1450 /* Enable PMD */
1451 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1452 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1453 }
1454
1455
1456 static int xcvr_diag_bcm870x(struct niu *np)
1457 {
1458 u16 analog_stat0, tx_alarm_status;
1459 int err = 0;
1460
1461 #if 1
1462 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1463 MII_STAT1000);
1464 if (err < 0)
1465 return err;
1466 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1467
1468 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1469 if (err < 0)
1470 return err;
1471 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1472
1473 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1474 MII_NWAYTEST);
1475 if (err < 0)
1476 return err;
1477 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1478 #endif
1479
1480 /* XXX dig this out it might not be so useful XXX */
1481 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1482 BCM8704_USER_ANALOG_STATUS0);
1483 if (err < 0)
1484 return err;
1485 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1486 BCM8704_USER_ANALOG_STATUS0);
1487 if (err < 0)
1488 return err;
1489 analog_stat0 = err;
1490
1491 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1492 BCM8704_USER_TX_ALARM_STATUS);
1493 if (err < 0)
1494 return err;
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1496 BCM8704_USER_TX_ALARM_STATUS);
1497 if (err < 0)
1498 return err;
1499 tx_alarm_status = err;
1500
1501 if (analog_stat0 != 0x03fc) {
1502 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1503 pr_info("Port %u cable not connected or bad cable\n",
1504 np->port);
1505 } else if (analog_stat0 == 0x639c) {
1506 pr_info("Port %u optical module is bad or missing\n",
1507 np->port);
1508 }
1509 }
1510
1511 return 0;
1512 }
1513
1514 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1515 {
1516 struct niu_link_config *lp = &np->link_config;
1517 int err;
1518
1519 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1520 MII_BMCR);
1521 if (err < 0)
1522 return err;
1523
1524 err &= ~BMCR_LOOPBACK;
1525
1526 if (lp->loopback_mode == LOOPBACK_MAC)
1527 err |= BMCR_LOOPBACK;
1528
1529 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1530 MII_BMCR, err);
1531 if (err)
1532 return err;
1533
1534 return 0;
1535 }
1536
1537 static int xcvr_init_10g_bcm8706(struct niu *np)
1538 {
1539 int err = 0;
1540 u64 val;
1541
1542 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1543 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1544 return err;
1545
1546 val = nr64_mac(XMAC_CONFIG);
1547 val &= ~XMAC_CONFIG_LED_POLARITY;
1548 val |= XMAC_CONFIG_FORCE_LED_ON;
1549 nw64_mac(XMAC_CONFIG, val);
1550
1551 val = nr64(MIF_CONFIG);
1552 val |= MIF_CONFIG_INDIRECT_MODE;
1553 nw64(MIF_CONFIG, val);
1554
1555 err = bcm8704_reset(np);
1556 if (err)
1557 return err;
1558
1559 err = xcvr_10g_set_lb_bcm870x(np);
1560 if (err)
1561 return err;
1562
1563 err = bcm8706_init_user_dev3(np);
1564 if (err)
1565 return err;
1566
1567 err = xcvr_diag_bcm870x(np);
1568 if (err)
1569 return err;
1570
1571 return 0;
1572 }
1573
1574 static int xcvr_init_10g_bcm8704(struct niu *np)
1575 {
1576 int err;
1577
1578 err = bcm8704_reset(np);
1579 if (err)
1580 return err;
1581
1582 err = bcm8704_init_user_dev3(np);
1583 if (err)
1584 return err;
1585
1586 err = xcvr_10g_set_lb_bcm870x(np);
1587 if (err)
1588 return err;
1589
1590 err = xcvr_diag_bcm870x(np);
1591 if (err)
1592 return err;
1593
1594 return 0;
1595 }
1596
1597 static int xcvr_init_10g(struct niu *np)
1598 {
1599 int phy_id, err;
1600 u64 val;
1601
1602 val = nr64_mac(XMAC_CONFIG);
1603 val &= ~XMAC_CONFIG_LED_POLARITY;
1604 val |= XMAC_CONFIG_FORCE_LED_ON;
1605 nw64_mac(XMAC_CONFIG, val);
1606
1607 /* XXX shared resource, lock parent XXX */
1608 val = nr64(MIF_CONFIG);
1609 val |= MIF_CONFIG_INDIRECT_MODE;
1610 nw64(MIF_CONFIG, val);
1611
1612 phy_id = phy_decode(np->parent->port_phy, np->port);
1613 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1614
1615 /* handle different phy types */
1616 switch (phy_id & NIU_PHY_ID_MASK) {
1617 case NIU_PHY_ID_MRVL88X2011:
1618 err = xcvr_init_10g_mrvl88x2011(np);
1619 break;
1620
1621 default: /* bcom 8704 */
1622 err = xcvr_init_10g_bcm8704(np);
1623 break;
1624 }
1625
1626 return err;
1627 }
1628
1629 static int mii_reset(struct niu *np)
1630 {
1631 int limit, err;
1632
1633 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1634 if (err)
1635 return err;
1636
1637 limit = 1000;
1638 while (--limit >= 0) {
1639 udelay(500);
1640 err = mii_read(np, np->phy_addr, MII_BMCR);
1641 if (err < 0)
1642 return err;
1643 if (!(err & BMCR_RESET))
1644 break;
1645 }
1646 if (limit < 0) {
1647 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1648 np->port, err);
1649 return -ENODEV;
1650 }
1651
1652 return 0;
1653 }
1654
1655 static int xcvr_init_1g_rgmii(struct niu *np)
1656 {
1657 int err;
1658 u64 val;
1659 u16 bmcr, bmsr, estat;
1660
1661 val = nr64(MIF_CONFIG);
1662 val &= ~MIF_CONFIG_INDIRECT_MODE;
1663 nw64(MIF_CONFIG, val);
1664
1665 err = mii_reset(np);
1666 if (err)
1667 return err;
1668
1669 err = mii_read(np, np->phy_addr, MII_BMSR);
1670 if (err < 0)
1671 return err;
1672 bmsr = err;
1673
1674 estat = 0;
1675 if (bmsr & BMSR_ESTATEN) {
1676 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1677 if (err < 0)
1678 return err;
1679 estat = err;
1680 }
1681
1682 bmcr = 0;
1683 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1684 if (err)
1685 return err;
1686
1687 if (bmsr & BMSR_ESTATEN) {
1688 u16 ctrl1000 = 0;
1689
1690 if (estat & ESTATUS_1000_TFULL)
1691 ctrl1000 |= ADVERTISE_1000FULL;
1692 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1693 if (err)
1694 return err;
1695 }
1696
1697 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1698
1699 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1700 if (err)
1701 return err;
1702
1703 err = mii_read(np, np->phy_addr, MII_BMCR);
1704 if (err < 0)
1705 return err;
1706 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1707
1708 err = mii_read(np, np->phy_addr, MII_BMSR);
1709 if (err < 0)
1710 return err;
1711
1712 return 0;
1713 }
1714
1715 static int mii_init_common(struct niu *np)
1716 {
1717 struct niu_link_config *lp = &np->link_config;
1718 u16 bmcr, bmsr, adv, estat;
1719 int err;
1720
1721 err = mii_reset(np);
1722 if (err)
1723 return err;
1724
1725 err = mii_read(np, np->phy_addr, MII_BMSR);
1726 if (err < 0)
1727 return err;
1728 bmsr = err;
1729
1730 estat = 0;
1731 if (bmsr & BMSR_ESTATEN) {
1732 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1733 if (err < 0)
1734 return err;
1735 estat = err;
1736 }
1737
1738 bmcr = 0;
1739 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1740 if (err)
1741 return err;
1742
1743 if (lp->loopback_mode == LOOPBACK_MAC) {
1744 bmcr |= BMCR_LOOPBACK;
1745 if (lp->active_speed == SPEED_1000)
1746 bmcr |= BMCR_SPEED1000;
1747 if (lp->active_duplex == DUPLEX_FULL)
1748 bmcr |= BMCR_FULLDPLX;
1749 }
1750
1751 if (lp->loopback_mode == LOOPBACK_PHY) {
1752 u16 aux;
1753
1754 aux = (BCM5464R_AUX_CTL_EXT_LB |
1755 BCM5464R_AUX_CTL_WRITE_1);
1756 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1757 if (err)
1758 return err;
1759 }
1760
1761 if (lp->autoneg) {
1762 u16 ctrl1000;
1763
1764 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1765 if ((bmsr & BMSR_10HALF) &&
1766 (lp->advertising & ADVERTISED_10baseT_Half))
1767 adv |= ADVERTISE_10HALF;
1768 if ((bmsr & BMSR_10FULL) &&
1769 (lp->advertising & ADVERTISED_10baseT_Full))
1770 adv |= ADVERTISE_10FULL;
1771 if ((bmsr & BMSR_100HALF) &&
1772 (lp->advertising & ADVERTISED_100baseT_Half))
1773 adv |= ADVERTISE_100HALF;
1774 if ((bmsr & BMSR_100FULL) &&
1775 (lp->advertising & ADVERTISED_100baseT_Full))
1776 adv |= ADVERTISE_100FULL;
1777 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1778 if (err)
1779 return err;
1780
1781 if (likely(bmsr & BMSR_ESTATEN)) {
1782 ctrl1000 = 0;
1783 if ((estat & ESTATUS_1000_THALF) &&
1784 (lp->advertising & ADVERTISED_1000baseT_Half))
1785 ctrl1000 |= ADVERTISE_1000HALF;
1786 if ((estat & ESTATUS_1000_TFULL) &&
1787 (lp->advertising & ADVERTISED_1000baseT_Full))
1788 ctrl1000 |= ADVERTISE_1000FULL;
1789 err = mii_write(np, np->phy_addr,
1790 MII_CTRL1000, ctrl1000);
1791 if (err)
1792 return err;
1793 }
1794
1795 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1796 } else {
1797 /* !lp->autoneg */
1798 int fulldpx;
1799
1800 if (lp->duplex == DUPLEX_FULL) {
1801 bmcr |= BMCR_FULLDPLX;
1802 fulldpx = 1;
1803 } else if (lp->duplex == DUPLEX_HALF)
1804 fulldpx = 0;
1805 else
1806 return -EINVAL;
1807
1808 if (lp->speed == SPEED_1000) {
1809 /* if X-full requested while not supported, or
1810 X-half requested while not supported... */
1811 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1812 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1813 return -EINVAL;
1814 bmcr |= BMCR_SPEED1000;
1815 } else if (lp->speed == SPEED_100) {
1816 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1817 (!fulldpx && !(bmsr & BMSR_100HALF)))
1818 return -EINVAL;
1819 bmcr |= BMCR_SPEED100;
1820 } else if (lp->speed == SPEED_10) {
1821 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1822 (!fulldpx && !(bmsr & BMSR_10HALF)))
1823 return -EINVAL;
1824 } else
1825 return -EINVAL;
1826 }
1827
1828 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1829 if (err)
1830 return err;
1831
1832 #if 0
1833 err = mii_read(np, np->phy_addr, MII_BMCR);
1834 if (err < 0)
1835 return err;
1836 bmcr = err;
1837
1838 err = mii_read(np, np->phy_addr, MII_BMSR);
1839 if (err < 0)
1840 return err;
1841 bmsr = err;
1842
1843 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1844 np->port, bmcr, bmsr);
1845 #endif
1846
1847 return 0;
1848 }
1849
1850 static int xcvr_init_1g(struct niu *np)
1851 {
1852 u64 val;
1853
1854 /* XXX shared resource, lock parent XXX */
1855 val = nr64(MIF_CONFIG);
1856 val &= ~MIF_CONFIG_INDIRECT_MODE;
1857 nw64(MIF_CONFIG, val);
1858
1859 return mii_init_common(np);
1860 }
1861
1862 static int niu_xcvr_init(struct niu *np)
1863 {
1864 const struct niu_phy_ops *ops = np->phy_ops;
1865 int err;
1866
1867 err = 0;
1868 if (ops->xcvr_init)
1869 err = ops->xcvr_init(np);
1870
1871 return err;
1872 }
1873
1874 static int niu_serdes_init(struct niu *np)
1875 {
1876 const struct niu_phy_ops *ops = np->phy_ops;
1877 int err;
1878
1879 err = 0;
1880 if (ops->serdes_init)
1881 err = ops->serdes_init(np);
1882
1883 return err;
1884 }
1885
1886 static void niu_init_xif(struct niu *);
1887 static void niu_handle_led(struct niu *, int status);
1888
1889 static int niu_link_status_common(struct niu *np, int link_up)
1890 {
1891 struct niu_link_config *lp = &np->link_config;
1892 struct net_device *dev = np->dev;
1893 unsigned long flags;
1894
1895 if (!netif_carrier_ok(dev) && link_up) {
1896 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1897 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1898 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1899 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1900 "10Mbit/sec",
1901 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1902
1903 spin_lock_irqsave(&np->lock, flags);
1904 niu_init_xif(np);
1905 niu_handle_led(np, 1);
1906 spin_unlock_irqrestore(&np->lock, flags);
1907
1908 netif_carrier_on(dev);
1909 } else if (netif_carrier_ok(dev) && !link_up) {
1910 netif_warn(np, link, dev, "Link is down\n");
1911 spin_lock_irqsave(&np->lock, flags);
1912 niu_handle_led(np, 0);
1913 spin_unlock_irqrestore(&np->lock, flags);
1914 netif_carrier_off(dev);
1915 }
1916
1917 return 0;
1918 }
1919
1920 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1921 {
1922 int err, link_up, pma_status, pcs_status;
1923
1924 link_up = 0;
1925
1926 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1927 MRVL88X2011_10G_PMD_STATUS_2);
1928 if (err < 0)
1929 goto out;
1930
1931 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1932 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1933 MRVL88X2011_PMA_PMD_STATUS_1);
1934 if (err < 0)
1935 goto out;
1936
1937 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1938
1939 /* Check PMC Register : 3.0001.2 == 1: read twice */
1940 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1941 MRVL88X2011_PMA_PMD_STATUS_1);
1942 if (err < 0)
1943 goto out;
1944
1945 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1946 MRVL88X2011_PMA_PMD_STATUS_1);
1947 if (err < 0)
1948 goto out;
1949
1950 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1951
1952 /* Check XGXS Register : 4.0018.[0-3,12] */
1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1954 MRVL88X2011_10G_XGXS_LANE_STAT);
1955 if (err < 0)
1956 goto out;
1957
1958 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1959 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1960 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1961 0x800))
1962 link_up = (pma_status && pcs_status) ? 1 : 0;
1963
1964 np->link_config.active_speed = SPEED_10000;
1965 np->link_config.active_duplex = DUPLEX_FULL;
1966 err = 0;
1967 out:
1968 mrvl88x2011_act_led(np, (link_up ?
1969 MRVL88X2011_LED_CTL_PCS_ACT :
1970 MRVL88X2011_LED_CTL_OFF));
1971
1972 *link_up_p = link_up;
1973 return err;
1974 }
1975
1976 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1977 {
1978 int err, link_up;
1979 link_up = 0;
1980
1981 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1982 BCM8704_PMD_RCV_SIGDET);
1983 if (err < 0 || err == 0xffff)
1984 goto out;
1985 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1986 err = 0;
1987 goto out;
1988 }
1989
1990 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1991 BCM8704_PCS_10G_R_STATUS);
1992 if (err < 0)
1993 goto out;
1994
1995 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1996 err = 0;
1997 goto out;
1998 }
1999
2000 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2001 BCM8704_PHYXS_XGXS_LANE_STAT);
2002 if (err < 0)
2003 goto out;
2004 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2005 PHYXS_XGXS_LANE_STAT_MAGIC |
2006 PHYXS_XGXS_LANE_STAT_PATTEST |
2007 PHYXS_XGXS_LANE_STAT_LANE3 |
2008 PHYXS_XGXS_LANE_STAT_LANE2 |
2009 PHYXS_XGXS_LANE_STAT_LANE1 |
2010 PHYXS_XGXS_LANE_STAT_LANE0)) {
2011 err = 0;
2012 np->link_config.active_speed = SPEED_INVALID;
2013 np->link_config.active_duplex = DUPLEX_INVALID;
2014 goto out;
2015 }
2016
2017 link_up = 1;
2018 np->link_config.active_speed = SPEED_10000;
2019 np->link_config.active_duplex = DUPLEX_FULL;
2020 err = 0;
2021
2022 out:
2023 *link_up_p = link_up;
2024 return err;
2025 }
2026
2027 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2028 {
2029 int err, link_up;
2030
2031 link_up = 0;
2032
2033 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2034 BCM8704_PMD_RCV_SIGDET);
2035 if (err < 0)
2036 goto out;
2037 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2038 err = 0;
2039 goto out;
2040 }
2041
2042 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2043 BCM8704_PCS_10G_R_STATUS);
2044 if (err < 0)
2045 goto out;
2046 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2047 err = 0;
2048 goto out;
2049 }
2050
2051 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2052 BCM8704_PHYXS_XGXS_LANE_STAT);
2053 if (err < 0)
2054 goto out;
2055
2056 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2057 PHYXS_XGXS_LANE_STAT_MAGIC |
2058 PHYXS_XGXS_LANE_STAT_LANE3 |
2059 PHYXS_XGXS_LANE_STAT_LANE2 |
2060 PHYXS_XGXS_LANE_STAT_LANE1 |
2061 PHYXS_XGXS_LANE_STAT_LANE0)) {
2062 err = 0;
2063 goto out;
2064 }
2065
2066 link_up = 1;
2067 np->link_config.active_speed = SPEED_10000;
2068 np->link_config.active_duplex = DUPLEX_FULL;
2069 err = 0;
2070
2071 out:
2072 *link_up_p = link_up;
2073 return err;
2074 }
2075
2076 static int link_status_10g(struct niu *np, int *link_up_p)
2077 {
2078 unsigned long flags;
2079 int err = -EINVAL;
2080
2081 spin_lock_irqsave(&np->lock, flags);
2082
2083 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2084 int phy_id;
2085
2086 phy_id = phy_decode(np->parent->port_phy, np->port);
2087 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2088
2089 /* handle different phy types */
2090 switch (phy_id & NIU_PHY_ID_MASK) {
2091 case NIU_PHY_ID_MRVL88X2011:
2092 err = link_status_10g_mrvl(np, link_up_p);
2093 break;
2094
2095 default: /* bcom 8704 */
2096 err = link_status_10g_bcom(np, link_up_p);
2097 break;
2098 }
2099 }
2100
2101 spin_unlock_irqrestore(&np->lock, flags);
2102
2103 return err;
2104 }
2105
2106 static int niu_10g_phy_present(struct niu *np)
2107 {
2108 u64 sig, mask, val;
2109
2110 sig = nr64(ESR_INT_SIGNALS);
2111 switch (np->port) {
2112 case 0:
2113 mask = ESR_INT_SIGNALS_P0_BITS;
2114 val = (ESR_INT_SRDY0_P0 |
2115 ESR_INT_DET0_P0 |
2116 ESR_INT_XSRDY_P0 |
2117 ESR_INT_XDP_P0_CH3 |
2118 ESR_INT_XDP_P0_CH2 |
2119 ESR_INT_XDP_P0_CH1 |
2120 ESR_INT_XDP_P0_CH0);
2121 break;
2122
2123 case 1:
2124 mask = ESR_INT_SIGNALS_P1_BITS;
2125 val = (ESR_INT_SRDY0_P1 |
2126 ESR_INT_DET0_P1 |
2127 ESR_INT_XSRDY_P1 |
2128 ESR_INT_XDP_P1_CH3 |
2129 ESR_INT_XDP_P1_CH2 |
2130 ESR_INT_XDP_P1_CH1 |
2131 ESR_INT_XDP_P1_CH0);
2132 break;
2133
2134 default:
2135 return 0;
2136 }
2137
2138 if ((sig & mask) != val)
2139 return 0;
2140 return 1;
2141 }
2142
2143 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2144 {
2145 unsigned long flags;
2146 int err = 0;
2147 int phy_present;
2148 int phy_present_prev;
2149
2150 spin_lock_irqsave(&np->lock, flags);
2151
2152 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2153 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2154 1 : 0;
2155 phy_present = niu_10g_phy_present(np);
2156 if (phy_present != phy_present_prev) {
2157 /* state change */
2158 if (phy_present) {
2159 /* A NEM was just plugged in */
2160 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2161 if (np->phy_ops->xcvr_init)
2162 err = np->phy_ops->xcvr_init(np);
2163 if (err) {
2164 err = mdio_read(np, np->phy_addr,
2165 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2166 if (err == 0xffff) {
2167 /* No mdio, back-to-back XAUI */
2168 goto out;
2169 }
2170 /* debounce */
2171 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2172 }
2173 } else {
2174 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2175 *link_up_p = 0;
2176 netif_warn(np, link, np->dev,
2177 "Hotplug PHY Removed\n");
2178 }
2179 }
2180 out:
2181 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2182 err = link_status_10g_bcm8706(np, link_up_p);
2183 if (err == 0xffff) {
2184 /* No mdio, back-to-back XAUI: it is C10NEM */
2185 *link_up_p = 1;
2186 np->link_config.active_speed = SPEED_10000;
2187 np->link_config.active_duplex = DUPLEX_FULL;
2188 }
2189 }
2190 }
2191
2192 spin_unlock_irqrestore(&np->lock, flags);
2193
2194 return 0;
2195 }
2196
2197 static int niu_link_status(struct niu *np, int *link_up_p)
2198 {
2199 const struct niu_phy_ops *ops = np->phy_ops;
2200 int err;
2201
2202 err = 0;
2203 if (ops->link_status)
2204 err = ops->link_status(np, link_up_p);
2205
2206 return err;
2207 }
2208
2209 static void niu_timer(struct timer_list *t)
2210 {
2211 struct niu *np = from_timer(np, t, timer);
2212 unsigned long off;
2213 int err, link_up;
2214
2215 err = niu_link_status(np, &link_up);
2216 if (!err)
2217 niu_link_status_common(np, link_up);
2218
2219 if (netif_carrier_ok(np->dev))
2220 off = 5 * HZ;
2221 else
2222 off = 1 * HZ;
2223 np->timer.expires = jiffies + off;
2224
2225 add_timer(&np->timer);
2226 }
2227
2228 static const struct niu_phy_ops phy_ops_10g_serdes = {
2229 .serdes_init = serdes_init_10g_serdes,
2230 .link_status = link_status_10g_serdes,
2231 };
2232
2233 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2234 .serdes_init = serdes_init_niu_10g_serdes,
2235 .link_status = link_status_10g_serdes,
2236 };
2237
2238 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2239 .serdes_init = serdes_init_niu_1g_serdes,
2240 .link_status = link_status_1g_serdes,
2241 };
2242
2243 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2244 .xcvr_init = xcvr_init_1g_rgmii,
2245 .link_status = link_status_1g_rgmii,
2246 };
2247
2248 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2249 .serdes_init = serdes_init_niu_10g_fiber,
2250 .xcvr_init = xcvr_init_10g,
2251 .link_status = link_status_10g,
2252 };
2253
2254 static const struct niu_phy_ops phy_ops_10g_fiber = {
2255 .serdes_init = serdes_init_10g,
2256 .xcvr_init = xcvr_init_10g,
2257 .link_status = link_status_10g,
2258 };
2259
2260 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2261 .serdes_init = serdes_init_10g,
2262 .xcvr_init = xcvr_init_10g_bcm8706,
2263 .link_status = link_status_10g_hotplug,
2264 };
2265
2266 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2267 .serdes_init = serdes_init_niu_10g_fiber,
2268 .xcvr_init = xcvr_init_10g_bcm8706,
2269 .link_status = link_status_10g_hotplug,
2270 };
2271
2272 static const struct niu_phy_ops phy_ops_10g_copper = {
2273 .serdes_init = serdes_init_10g,
2274 .link_status = link_status_10g, /* XXX */
2275 };
2276
2277 static const struct niu_phy_ops phy_ops_1g_fiber = {
2278 .serdes_init = serdes_init_1g,
2279 .xcvr_init = xcvr_init_1g,
2280 .link_status = link_status_1g,
2281 };
2282
2283 static const struct niu_phy_ops phy_ops_1g_copper = {
2284 .xcvr_init = xcvr_init_1g,
2285 .link_status = link_status_1g,
2286 };
2287
2288 struct niu_phy_template {
2289 const struct niu_phy_ops *ops;
2290 u32 phy_addr_base;
2291 };
2292
2293 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2294 .ops = &phy_ops_10g_fiber_niu,
2295 .phy_addr_base = 16,
2296 };
2297
2298 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2299 .ops = &phy_ops_10g_serdes_niu,
2300 .phy_addr_base = 0,
2301 };
2302
2303 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2304 .ops = &phy_ops_1g_serdes_niu,
2305 .phy_addr_base = 0,
2306 };
2307
2308 static const struct niu_phy_template phy_template_10g_fiber = {
2309 .ops = &phy_ops_10g_fiber,
2310 .phy_addr_base = 8,
2311 };
2312
2313 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2314 .ops = &phy_ops_10g_fiber_hotplug,
2315 .phy_addr_base = 8,
2316 };
2317
2318 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2319 .ops = &phy_ops_niu_10g_hotplug,
2320 .phy_addr_base = 8,
2321 };
2322
2323 static const struct niu_phy_template phy_template_10g_copper = {
2324 .ops = &phy_ops_10g_copper,
2325 .phy_addr_base = 10,
2326 };
2327
2328 static const struct niu_phy_template phy_template_1g_fiber = {
2329 .ops = &phy_ops_1g_fiber,
2330 .phy_addr_base = 0,
2331 };
2332
2333 static const struct niu_phy_template phy_template_1g_copper = {
2334 .ops = &phy_ops_1g_copper,
2335 .phy_addr_base = 0,
2336 };
2337
2338 static const struct niu_phy_template phy_template_1g_rgmii = {
2339 .ops = &phy_ops_1g_rgmii,
2340 .phy_addr_base = 0,
2341 };
2342
2343 static const struct niu_phy_template phy_template_10g_serdes = {
2344 .ops = &phy_ops_10g_serdes,
2345 .phy_addr_base = 0,
2346 };
2347
2348 static int niu_atca_port_num[4] = {
2349 0, 0, 11, 10
2350 };
2351
2352 static int serdes_init_10g_serdes(struct niu *np)
2353 {
2354 struct niu_link_config *lp = &np->link_config;
2355 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2356 u64 ctrl_val, test_cfg_val, sig, mask, val;
2357
2358 switch (np->port) {
2359 case 0:
2360 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2361 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2362 pll_cfg = ENET_SERDES_0_PLL_CFG;
2363 break;
2364 case 1:
2365 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2366 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2367 pll_cfg = ENET_SERDES_1_PLL_CFG;
2368 break;
2369
2370 default:
2371 return -EINVAL;
2372 }
2373 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2374 ENET_SERDES_CTRL_SDET_1 |
2375 ENET_SERDES_CTRL_SDET_2 |
2376 ENET_SERDES_CTRL_SDET_3 |
2377 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2378 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2379 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2380 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2381 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2382 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2383 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2384 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2385 test_cfg_val = 0;
2386
2387 if (lp->loopback_mode == LOOPBACK_PHY) {
2388 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2389 ENET_SERDES_TEST_MD_0_SHIFT) |
2390 (ENET_TEST_MD_PAD_LOOPBACK <<
2391 ENET_SERDES_TEST_MD_1_SHIFT) |
2392 (ENET_TEST_MD_PAD_LOOPBACK <<
2393 ENET_SERDES_TEST_MD_2_SHIFT) |
2394 (ENET_TEST_MD_PAD_LOOPBACK <<
2395 ENET_SERDES_TEST_MD_3_SHIFT));
2396 }
2397
2398 esr_reset(np);
2399 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2400 nw64(ctrl_reg, ctrl_val);
2401 nw64(test_cfg_reg, test_cfg_val);
2402
2403 /* Initialize all 4 lanes of the SERDES. */
2404 for (i = 0; i < 4; i++) {
2405 u32 rxtx_ctrl, glue0;
2406 int err;
2407
2408 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2409 if (err)
2410 return err;
2411 err = esr_read_glue0(np, i, &glue0);
2412 if (err)
2413 return err;
2414
2415 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2416 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2417 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2418
2419 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2420 ESR_GLUE_CTRL0_THCNT |
2421 ESR_GLUE_CTRL0_BLTIME);
2422 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2423 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2424 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2425 (BLTIME_300_CYCLES <<
2426 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2427
2428 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2429 if (err)
2430 return err;
2431 err = esr_write_glue0(np, i, glue0);
2432 if (err)
2433 return err;
2434 }
2435
2436
2437 sig = nr64(ESR_INT_SIGNALS);
2438 switch (np->port) {
2439 case 0:
2440 mask = ESR_INT_SIGNALS_P0_BITS;
2441 val = (ESR_INT_SRDY0_P0 |
2442 ESR_INT_DET0_P0 |
2443 ESR_INT_XSRDY_P0 |
2444 ESR_INT_XDP_P0_CH3 |
2445 ESR_INT_XDP_P0_CH2 |
2446 ESR_INT_XDP_P0_CH1 |
2447 ESR_INT_XDP_P0_CH0);
2448 break;
2449
2450 case 1:
2451 mask = ESR_INT_SIGNALS_P1_BITS;
2452 val = (ESR_INT_SRDY0_P1 |
2453 ESR_INT_DET0_P1 |
2454 ESR_INT_XSRDY_P1 |
2455 ESR_INT_XDP_P1_CH3 |
2456 ESR_INT_XDP_P1_CH2 |
2457 ESR_INT_XDP_P1_CH1 |
2458 ESR_INT_XDP_P1_CH0);
2459 break;
2460
2461 default:
2462 return -EINVAL;
2463 }
2464
2465 if ((sig & mask) != val) {
2466 int err;
2467 err = serdes_init_1g_serdes(np);
2468 if (!err) {
2469 np->flags &= ~NIU_FLAGS_10G;
2470 np->mac_xcvr = MAC_XCVR_PCS;
2471 } else {
2472 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2473 np->port);
2474 return -ENODEV;
2475 }
2476 }
2477
2478 return 0;
2479 }
2480
2481 static int niu_determine_phy_disposition(struct niu *np)
2482 {
2483 struct niu_parent *parent = np->parent;
2484 u8 plat_type = parent->plat_type;
2485 const struct niu_phy_template *tp;
2486 u32 phy_addr_off = 0;
2487
2488 if (plat_type == PLAT_TYPE_NIU) {
2489 switch (np->flags &
2490 (NIU_FLAGS_10G |
2491 NIU_FLAGS_FIBER |
2492 NIU_FLAGS_XCVR_SERDES)) {
2493 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2494 /* 10G Serdes */
2495 tp = &phy_template_niu_10g_serdes;
2496 break;
2497 case NIU_FLAGS_XCVR_SERDES:
2498 /* 1G Serdes */
2499 tp = &phy_template_niu_1g_serdes;
2500 break;
2501 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2502 /* 10G Fiber */
2503 default:
2504 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2505 tp = &phy_template_niu_10g_hotplug;
2506 if (np->port == 0)
2507 phy_addr_off = 8;
2508 if (np->port == 1)
2509 phy_addr_off = 12;
2510 } else {
2511 tp = &phy_template_niu_10g_fiber;
2512 phy_addr_off += np->port;
2513 }
2514 break;
2515 }
2516 } else {
2517 switch (np->flags &
2518 (NIU_FLAGS_10G |
2519 NIU_FLAGS_FIBER |
2520 NIU_FLAGS_XCVR_SERDES)) {
2521 case 0:
2522 /* 1G copper */
2523 tp = &phy_template_1g_copper;
2524 if (plat_type == PLAT_TYPE_VF_P0)
2525 phy_addr_off = 10;
2526 else if (plat_type == PLAT_TYPE_VF_P1)
2527 phy_addr_off = 26;
2528
2529 phy_addr_off += (np->port ^ 0x3);
2530 break;
2531
2532 case NIU_FLAGS_10G:
2533 /* 10G copper */
2534 tp = &phy_template_10g_copper;
2535 break;
2536
2537 case NIU_FLAGS_FIBER:
2538 /* 1G fiber */
2539 tp = &phy_template_1g_fiber;
2540 break;
2541
2542 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2543 /* 10G fiber */
2544 tp = &phy_template_10g_fiber;
2545 if (plat_type == PLAT_TYPE_VF_P0 ||
2546 plat_type == PLAT_TYPE_VF_P1)
2547 phy_addr_off = 8;
2548 phy_addr_off += np->port;
2549 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2550 tp = &phy_template_10g_fiber_hotplug;
2551 if (np->port == 0)
2552 phy_addr_off = 8;
2553 if (np->port == 1)
2554 phy_addr_off = 12;
2555 }
2556 break;
2557
2558 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2559 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2560 case NIU_FLAGS_XCVR_SERDES:
2561 switch(np->port) {
2562 case 0:
2563 case 1:
2564 tp = &phy_template_10g_serdes;
2565 break;
2566 case 2:
2567 case 3:
2568 tp = &phy_template_1g_rgmii;
2569 break;
2570 default:
2571 return -EINVAL;
2572 }
2573 phy_addr_off = niu_atca_port_num[np->port];
2574 break;
2575
2576 default:
2577 return -EINVAL;
2578 }
2579 }
2580
2581 np->phy_ops = tp->ops;
2582 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2583
2584 return 0;
2585 }
2586
2587 static int niu_init_link(struct niu *np)
2588 {
2589 struct niu_parent *parent = np->parent;
2590 int err, ignore;
2591
2592 if (parent->plat_type == PLAT_TYPE_NIU) {
2593 err = niu_xcvr_init(np);
2594 if (err)
2595 return err;
2596 msleep(200);
2597 }
2598 err = niu_serdes_init(np);
2599 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2600 return err;
2601 msleep(200);
2602 err = niu_xcvr_init(np);
2603 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2604 niu_link_status(np, &ignore);
2605 return 0;
2606 }
2607
2608 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2609 {
2610 u16 reg0 = addr[4] << 8 | addr[5];
2611 u16 reg1 = addr[2] << 8 | addr[3];
2612 u16 reg2 = addr[0] << 8 | addr[1];
2613
2614 if (np->flags & NIU_FLAGS_XMAC) {
2615 nw64_mac(XMAC_ADDR0, reg0);
2616 nw64_mac(XMAC_ADDR1, reg1);
2617 nw64_mac(XMAC_ADDR2, reg2);
2618 } else {
2619 nw64_mac(BMAC_ADDR0, reg0);
2620 nw64_mac(BMAC_ADDR1, reg1);
2621 nw64_mac(BMAC_ADDR2, reg2);
2622 }
2623 }
2624
2625 static int niu_num_alt_addr(struct niu *np)
2626 {
2627 if (np->flags & NIU_FLAGS_XMAC)
2628 return XMAC_NUM_ALT_ADDR;
2629 else
2630 return BMAC_NUM_ALT_ADDR;
2631 }
2632
2633 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2634 {
2635 u16 reg0 = addr[4] << 8 | addr[5];
2636 u16 reg1 = addr[2] << 8 | addr[3];
2637 u16 reg2 = addr[0] << 8 | addr[1];
2638
2639 if (index >= niu_num_alt_addr(np))
2640 return -EINVAL;
2641
2642 if (np->flags & NIU_FLAGS_XMAC) {
2643 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2644 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2645 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2646 } else {
2647 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2648 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2649 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2650 }
2651
2652 return 0;
2653 }
2654
2655 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2656 {
2657 unsigned long reg;
2658 u64 val, mask;
2659
2660 if (index >= niu_num_alt_addr(np))
2661 return -EINVAL;
2662
2663 if (np->flags & NIU_FLAGS_XMAC) {
2664 reg = XMAC_ADDR_CMPEN;
2665 mask = 1 << index;
2666 } else {
2667 reg = BMAC_ADDR_CMPEN;
2668 mask = 1 << (index + 1);
2669 }
2670
2671 val = nr64_mac(reg);
2672 if (on)
2673 val |= mask;
2674 else
2675 val &= ~mask;
2676 nw64_mac(reg, val);
2677
2678 return 0;
2679 }
2680
2681 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2682 int num, int mac_pref)
2683 {
2684 u64 val = nr64_mac(reg);
2685 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2686 val |= num;
2687 if (mac_pref)
2688 val |= HOST_INFO_MPR;
2689 nw64_mac(reg, val);
2690 }
2691
2692 static int __set_rdc_table_num(struct niu *np,
2693 int xmac_index, int bmac_index,
2694 int rdc_table_num, int mac_pref)
2695 {
2696 unsigned long reg;
2697
2698 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2699 return -EINVAL;
2700 if (np->flags & NIU_FLAGS_XMAC)
2701 reg = XMAC_HOST_INFO(xmac_index);
2702 else
2703 reg = BMAC_HOST_INFO(bmac_index);
2704 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2705 return 0;
2706 }
2707
2708 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2709 int mac_pref)
2710 {
2711 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2712 }
2713
2714 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2715 int mac_pref)
2716 {
2717 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2718 }
2719
2720 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2721 int table_num, int mac_pref)
2722 {
2723 if (idx >= niu_num_alt_addr(np))
2724 return -EINVAL;
2725 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2726 }
2727
2728 static u64 vlan_entry_set_parity(u64 reg_val)
2729 {
2730 u64 port01_mask;
2731 u64 port23_mask;
2732
2733 port01_mask = 0x00ff;
2734 port23_mask = 0xff00;
2735
2736 if (hweight64(reg_val & port01_mask) & 1)
2737 reg_val |= ENET_VLAN_TBL_PARITY0;
2738 else
2739 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2740
2741 if (hweight64(reg_val & port23_mask) & 1)
2742 reg_val |= ENET_VLAN_TBL_PARITY1;
2743 else
2744 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2745
2746 return reg_val;
2747 }
2748
2749 static void vlan_tbl_write(struct niu *np, unsigned long index,
2750 int port, int vpr, int rdc_table)
2751 {
2752 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2753
2754 reg_val &= ~((ENET_VLAN_TBL_VPR |
2755 ENET_VLAN_TBL_VLANRDCTBLN) <<
2756 ENET_VLAN_TBL_SHIFT(port));
2757 if (vpr)
2758 reg_val |= (ENET_VLAN_TBL_VPR <<
2759 ENET_VLAN_TBL_SHIFT(port));
2760 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2761
2762 reg_val = vlan_entry_set_parity(reg_val);
2763
2764 nw64(ENET_VLAN_TBL(index), reg_val);
2765 }
2766
2767 static void vlan_tbl_clear(struct niu *np)
2768 {
2769 int i;
2770
2771 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2772 nw64(ENET_VLAN_TBL(i), 0);
2773 }
2774
2775 static int tcam_wait_bit(struct niu *np, u64 bit)
2776 {
2777 int limit = 1000;
2778
2779 while (--limit > 0) {
2780 if (nr64(TCAM_CTL) & bit)
2781 break;
2782 udelay(1);
2783 }
2784 if (limit <= 0)
2785 return -ENODEV;
2786
2787 return 0;
2788 }
2789
2790 static int tcam_flush(struct niu *np, int index)
2791 {
2792 nw64(TCAM_KEY_0, 0x00);
2793 nw64(TCAM_KEY_MASK_0, 0xff);
2794 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2795
2796 return tcam_wait_bit(np, TCAM_CTL_STAT);
2797 }
2798
2799 #if 0
2800 static int tcam_read(struct niu *np, int index,
2801 u64 *key, u64 *mask)
2802 {
2803 int err;
2804
2805 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2806 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2807 if (!err) {
2808 key[0] = nr64(TCAM_KEY_0);
2809 key[1] = nr64(TCAM_KEY_1);
2810 key[2] = nr64(TCAM_KEY_2);
2811 key[3] = nr64(TCAM_KEY_3);
2812 mask[0] = nr64(TCAM_KEY_MASK_0);
2813 mask[1] = nr64(TCAM_KEY_MASK_1);
2814 mask[2] = nr64(TCAM_KEY_MASK_2);
2815 mask[3] = nr64(TCAM_KEY_MASK_3);
2816 }
2817 return err;
2818 }
2819 #endif
2820
2821 static int tcam_write(struct niu *np, int index,
2822 u64 *key, u64 *mask)
2823 {
2824 nw64(TCAM_KEY_0, key[0]);
2825 nw64(TCAM_KEY_1, key[1]);
2826 nw64(TCAM_KEY_2, key[2]);
2827 nw64(TCAM_KEY_3, key[3]);
2828 nw64(TCAM_KEY_MASK_0, mask[0]);
2829 nw64(TCAM_KEY_MASK_1, mask[1]);
2830 nw64(TCAM_KEY_MASK_2, mask[2]);
2831 nw64(TCAM_KEY_MASK_3, mask[3]);
2832 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2833
2834 return tcam_wait_bit(np, TCAM_CTL_STAT);
2835 }
2836
2837 #if 0
2838 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2839 {
2840 int err;
2841
2842 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2843 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2844 if (!err)
2845 *data = nr64(TCAM_KEY_1);
2846
2847 return err;
2848 }
2849 #endif
2850
2851 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2852 {
2853 nw64(TCAM_KEY_1, assoc_data);
2854 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2855
2856 return tcam_wait_bit(np, TCAM_CTL_STAT);
2857 }
2858
2859 static void tcam_enable(struct niu *np, int on)
2860 {
2861 u64 val = nr64(FFLP_CFG_1);
2862
2863 if (on)
2864 val &= ~FFLP_CFG_1_TCAM_DIS;
2865 else
2866 val |= FFLP_CFG_1_TCAM_DIS;
2867 nw64(FFLP_CFG_1, val);
2868 }
2869
2870 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2871 {
2872 u64 val = nr64(FFLP_CFG_1);
2873
2874 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2875 FFLP_CFG_1_CAMLAT |
2876 FFLP_CFG_1_CAMRATIO);
2877 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2878 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2879 nw64(FFLP_CFG_1, val);
2880
2881 val = nr64(FFLP_CFG_1);
2882 val |= FFLP_CFG_1_FFLPINITDONE;
2883 nw64(FFLP_CFG_1, val);
2884 }
2885
2886 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2887 int on)
2888 {
2889 unsigned long reg;
2890 u64 val;
2891
2892 if (class < CLASS_CODE_ETHERTYPE1 ||
2893 class > CLASS_CODE_ETHERTYPE2)
2894 return -EINVAL;
2895
2896 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2897 val = nr64(reg);
2898 if (on)
2899 val |= L2_CLS_VLD;
2900 else
2901 val &= ~L2_CLS_VLD;
2902 nw64(reg, val);
2903
2904 return 0;
2905 }
2906
2907 #if 0
2908 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2909 u64 ether_type)
2910 {
2911 unsigned long reg;
2912 u64 val;
2913
2914 if (class < CLASS_CODE_ETHERTYPE1 ||
2915 class > CLASS_CODE_ETHERTYPE2 ||
2916 (ether_type & ~(u64)0xffff) != 0)
2917 return -EINVAL;
2918
2919 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2920 val = nr64(reg);
2921 val &= ~L2_CLS_ETYPE;
2922 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2923 nw64(reg, val);
2924
2925 return 0;
2926 }
2927 #endif
2928
2929 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2930 int on)
2931 {
2932 unsigned long reg;
2933 u64 val;
2934
2935 if (class < CLASS_CODE_USER_PROG1 ||
2936 class > CLASS_CODE_USER_PROG4)
2937 return -EINVAL;
2938
2939 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2940 val = nr64(reg);
2941 if (on)
2942 val |= L3_CLS_VALID;
2943 else
2944 val &= ~L3_CLS_VALID;
2945 nw64(reg, val);
2946
2947 return 0;
2948 }
2949
2950 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2951 int ipv6, u64 protocol_id,
2952 u64 tos_mask, u64 tos_val)
2953 {
2954 unsigned long reg;
2955 u64 val;
2956
2957 if (class < CLASS_CODE_USER_PROG1 ||
2958 class > CLASS_CODE_USER_PROG4 ||
2959 (protocol_id & ~(u64)0xff) != 0 ||
2960 (tos_mask & ~(u64)0xff) != 0 ||
2961 (tos_val & ~(u64)0xff) != 0)
2962 return -EINVAL;
2963
2964 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2965 val = nr64(reg);
2966 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2967 L3_CLS_TOSMASK | L3_CLS_TOS);
2968 if (ipv6)
2969 val |= L3_CLS_IPVER;
2970 val |= (protocol_id << L3_CLS_PID_SHIFT);
2971 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2972 val |= (tos_val << L3_CLS_TOS_SHIFT);
2973 nw64(reg, val);
2974
2975 return 0;
2976 }
2977
2978 static int tcam_early_init(struct niu *np)
2979 {
2980 unsigned long i;
2981 int err;
2982
2983 tcam_enable(np, 0);
2984 tcam_set_lat_and_ratio(np,
2985 DEFAULT_TCAM_LATENCY,
2986 DEFAULT_TCAM_ACCESS_RATIO);
2987 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2988 err = tcam_user_eth_class_enable(np, i, 0);
2989 if (err)
2990 return err;
2991 }
2992 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2993 err = tcam_user_ip_class_enable(np, i, 0);
2994 if (err)
2995 return err;
2996 }
2997
2998 return 0;
2999 }
3000
3001 static int tcam_flush_all(struct niu *np)
3002 {
3003 unsigned long i;
3004
3005 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3006 int err = tcam_flush(np, i);
3007 if (err)
3008 return err;
3009 }
3010 return 0;
3011 }
3012
3013 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3014 {
3015 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3016 }
3017
3018 #if 0
3019 static int hash_read(struct niu *np, unsigned long partition,
3020 unsigned long index, unsigned long num_entries,
3021 u64 *data)
3022 {
3023 u64 val = hash_addr_regval(index, num_entries);
3024 unsigned long i;
3025
3026 if (partition >= FCRAM_NUM_PARTITIONS ||
3027 index + num_entries > FCRAM_SIZE)
3028 return -EINVAL;
3029
3030 nw64(HASH_TBL_ADDR(partition), val);
3031 for (i = 0; i < num_entries; i++)
3032 data[i] = nr64(HASH_TBL_DATA(partition));
3033
3034 return 0;
3035 }
3036 #endif
3037
3038 static int hash_write(struct niu *np, unsigned long partition,
3039 unsigned long index, unsigned long num_entries,
3040 u64 *data)
3041 {
3042 u64 val = hash_addr_regval(index, num_entries);
3043 unsigned long i;
3044
3045 if (partition >= FCRAM_NUM_PARTITIONS ||
3046 index + (num_entries * 8) > FCRAM_SIZE)
3047 return -EINVAL;
3048
3049 nw64(HASH_TBL_ADDR(partition), val);
3050 for (i = 0; i < num_entries; i++)
3051 nw64(HASH_TBL_DATA(partition), data[i]);
3052
3053 return 0;
3054 }
3055
3056 static void fflp_reset(struct niu *np)
3057 {
3058 u64 val;
3059
3060 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3061 udelay(10);
3062 nw64(FFLP_CFG_1, 0);
3063
3064 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3065 nw64(FFLP_CFG_1, val);
3066 }
3067
3068 static void fflp_set_timings(struct niu *np)
3069 {
3070 u64 val = nr64(FFLP_CFG_1);
3071
3072 val &= ~FFLP_CFG_1_FFLPINITDONE;
3073 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3074 nw64(FFLP_CFG_1, val);
3075
3076 val = nr64(FFLP_CFG_1);
3077 val |= FFLP_CFG_1_FFLPINITDONE;
3078 nw64(FFLP_CFG_1, val);
3079
3080 val = nr64(FCRAM_REF_TMR);
3081 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3082 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3083 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3084 nw64(FCRAM_REF_TMR, val);
3085 }
3086
3087 static int fflp_set_partition(struct niu *np, u64 partition,
3088 u64 mask, u64 base, int enable)
3089 {
3090 unsigned long reg;
3091 u64 val;
3092
3093 if (partition >= FCRAM_NUM_PARTITIONS ||
3094 (mask & ~(u64)0x1f) != 0 ||
3095 (base & ~(u64)0x1f) != 0)
3096 return -EINVAL;
3097
3098 reg = FLW_PRT_SEL(partition);
3099
3100 val = nr64(reg);
3101 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3102 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3103 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3104 if (enable)
3105 val |= FLW_PRT_SEL_EXT;
3106 nw64(reg, val);
3107
3108 return 0;
3109 }
3110
3111 static int fflp_disable_all_partitions(struct niu *np)
3112 {
3113 unsigned long i;
3114
3115 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3116 int err = fflp_set_partition(np, 0, 0, 0, 0);
3117 if (err)
3118 return err;
3119 }
3120 return 0;
3121 }
3122
3123 static void fflp_llcsnap_enable(struct niu *np, int on)
3124 {
3125 u64 val = nr64(FFLP_CFG_1);
3126
3127 if (on)
3128 val |= FFLP_CFG_1_LLCSNAP;
3129 else
3130 val &= ~FFLP_CFG_1_LLCSNAP;
3131 nw64(FFLP_CFG_1, val);
3132 }
3133
3134 static void fflp_errors_enable(struct niu *np, int on)
3135 {
3136 u64 val = nr64(FFLP_CFG_1);
3137
3138 if (on)
3139 val &= ~FFLP_CFG_1_ERRORDIS;
3140 else
3141 val |= FFLP_CFG_1_ERRORDIS;
3142 nw64(FFLP_CFG_1, val);
3143 }
3144
3145 static int fflp_hash_clear(struct niu *np)
3146 {
3147 struct fcram_hash_ipv4 ent;
3148 unsigned long i;
3149
3150 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3151 memset(&ent, 0, sizeof(ent));
3152 ent.header = HASH_HEADER_EXT;
3153
3154 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3155 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3156 if (err)
3157 return err;
3158 }
3159 return 0;
3160 }
3161
3162 static int fflp_early_init(struct niu *np)
3163 {
3164 struct niu_parent *parent;
3165 unsigned long flags;
3166 int err;
3167
3168 niu_lock_parent(np, flags);
3169
3170 parent = np->parent;
3171 err = 0;
3172 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3173 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3174 fflp_reset(np);
3175 fflp_set_timings(np);
3176 err = fflp_disable_all_partitions(np);
3177 if (err) {
3178 netif_printk(np, probe, KERN_DEBUG, np->dev,
3179 "fflp_disable_all_partitions failed, err=%d\n",
3180 err);
3181 goto out;
3182 }
3183 }
3184
3185 err = tcam_early_init(np);
3186 if (err) {
3187 netif_printk(np, probe, KERN_DEBUG, np->dev,
3188 "tcam_early_init failed, err=%d\n", err);
3189 goto out;
3190 }
3191 fflp_llcsnap_enable(np, 1);
3192 fflp_errors_enable(np, 0);
3193 nw64(H1POLY, 0);
3194 nw64(H2POLY, 0);
3195
3196 err = tcam_flush_all(np);
3197 if (err) {
3198 netif_printk(np, probe, KERN_DEBUG, np->dev,
3199 "tcam_flush_all failed, err=%d\n", err);
3200 goto out;
3201 }
3202 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3203 err = fflp_hash_clear(np);
3204 if (err) {
3205 netif_printk(np, probe, KERN_DEBUG, np->dev,
3206 "fflp_hash_clear failed, err=%d\n",
3207 err);
3208 goto out;
3209 }
3210 }
3211
3212 vlan_tbl_clear(np);
3213
3214 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3215 }
3216 out:
3217 niu_unlock_parent(np, flags);
3218 return err;
3219 }
3220
3221 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3222 {
3223 if (class_code < CLASS_CODE_USER_PROG1 ||
3224 class_code > CLASS_CODE_SCTP_IPV6)
3225 return -EINVAL;
3226
3227 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3228 return 0;
3229 }
3230
3231 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3232 {
3233 if (class_code < CLASS_CODE_USER_PROG1 ||
3234 class_code > CLASS_CODE_SCTP_IPV6)
3235 return -EINVAL;
3236
3237 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3238 return 0;
3239 }
3240
3241 /* Entries for the ports are interleaved in the TCAM */
3242 static u16 tcam_get_index(struct niu *np, u16 idx)
3243 {
3244 /* One entry reserved for IP fragment rule */
3245 if (idx >= (np->clas.tcam_sz - 1))
3246 idx = 0;
3247 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3248 }
3249
3250 static u16 tcam_get_size(struct niu *np)
3251 {
3252 /* One entry reserved for IP fragment rule */
3253 return np->clas.tcam_sz - 1;
3254 }
3255
3256 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3257 {
3258 /* One entry reserved for IP fragment rule */
3259 return np->clas.tcam_valid_entries - 1;
3260 }
3261
3262 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3263 u32 offset, u32 size, u32 truesize)
3264 {
3265 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3266
3267 skb->len += size;
3268 skb->data_len += size;
3269 skb->truesize += truesize;
3270 }
3271
3272 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3273 {
3274 a >>= PAGE_SHIFT;
3275 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3276
3277 return a & (MAX_RBR_RING_SIZE - 1);
3278 }
3279
3280 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3281 struct page ***link)
3282 {
3283 unsigned int h = niu_hash_rxaddr(rp, addr);
3284 struct page *p, **pp;
3285
3286 addr &= PAGE_MASK;
3287 pp = &rp->rxhash[h];
3288 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3289 if (p->index == addr) {
3290 *link = pp;
3291 goto found;
3292 }
3293 }
3294 BUG();
3295
3296 found:
3297 return p;
3298 }
3299
3300 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3301 {
3302 unsigned int h = niu_hash_rxaddr(rp, base);
3303
3304 page->index = base;
3305 page->mapping = (struct address_space *) rp->rxhash[h];
3306 rp->rxhash[h] = page;
3307 }
3308
3309 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3310 gfp_t mask, int start_index)
3311 {
3312 struct page *page;
3313 u64 addr;
3314 int i;
3315
3316 page = alloc_page(mask);
3317 if (!page)
3318 return -ENOMEM;
3319
3320 addr = np->ops->map_page(np->device, page, 0,
3321 PAGE_SIZE, DMA_FROM_DEVICE);
3322 if (!addr) {
3323 __free_page(page);
3324 return -ENOMEM;
3325 }
3326
3327 niu_hash_page(rp, page, addr);
3328 if (rp->rbr_blocks_per_page > 1)
3329 page_ref_add(page, rp->rbr_blocks_per_page - 1);
3330
3331 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3332 __le32 *rbr = &rp->rbr[start_index + i];
3333
3334 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3335 addr += rp->rbr_block_size;
3336 }
3337
3338 return 0;
3339 }
3340
3341 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3342 {
3343 int index = rp->rbr_index;
3344
3345 rp->rbr_pending++;
3346 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3347 int err = niu_rbr_add_page(np, rp, mask, index);
3348
3349 if (unlikely(err)) {
3350 rp->rbr_pending--;
3351 return;
3352 }
3353
3354 rp->rbr_index += rp->rbr_blocks_per_page;
3355 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3356 if (rp->rbr_index == rp->rbr_table_size)
3357 rp->rbr_index = 0;
3358
3359 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3360 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3361 rp->rbr_pending = 0;
3362 }
3363 }
3364 }
3365
3366 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3367 {
3368 unsigned int index = rp->rcr_index;
3369 int num_rcr = 0;
3370
3371 rp->rx_dropped++;
3372 while (1) {
3373 struct page *page, **link;
3374 u64 addr, val;
3375 u32 rcr_size;
3376
3377 num_rcr++;
3378
3379 val = le64_to_cpup(&rp->rcr[index]);
3380 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3381 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3382 page = niu_find_rxpage(rp, addr, &link);
3383
3384 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3385 RCR_ENTRY_PKTBUFSZ_SHIFT];
3386 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3387 *link = (struct page *) page->mapping;
3388 np->ops->unmap_page(np->device, page->index,
3389 PAGE_SIZE, DMA_FROM_DEVICE);
3390 page->index = 0;
3391 page->mapping = NULL;
3392 __free_page(page);
3393 rp->rbr_refill_pending++;
3394 }
3395
3396 index = NEXT_RCR(rp, index);
3397 if (!(val & RCR_ENTRY_MULTI))
3398 break;
3399
3400 }
3401 rp->rcr_index = index;
3402
3403 return num_rcr;
3404 }
3405
3406 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3407 struct rx_ring_info *rp)
3408 {
3409 unsigned int index = rp->rcr_index;
3410 struct rx_pkt_hdr1 *rh;
3411 struct sk_buff *skb;
3412 int len, num_rcr;
3413
3414 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3415 if (unlikely(!skb))
3416 return niu_rx_pkt_ignore(np, rp);
3417
3418 num_rcr = 0;
3419 while (1) {
3420 struct page *page, **link;
3421 u32 rcr_size, append_size;
3422 u64 addr, val, off;
3423
3424 num_rcr++;
3425
3426 val = le64_to_cpup(&rp->rcr[index]);
3427
3428 len = (val & RCR_ENTRY_L2_LEN) >>
3429 RCR_ENTRY_L2_LEN_SHIFT;
3430 append_size = len + ETH_HLEN + ETH_FCS_LEN;
3431
3432 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3433 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3434 page = niu_find_rxpage(rp, addr, &link);
3435
3436 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3437 RCR_ENTRY_PKTBUFSZ_SHIFT];
3438
3439 off = addr & ~PAGE_MASK;
3440 if (num_rcr == 1) {
3441 int ptype;
3442
3443 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3444 if ((ptype == RCR_PKT_TYPE_TCP ||
3445 ptype == RCR_PKT_TYPE_UDP) &&
3446 !(val & (RCR_ENTRY_NOPORT |
3447 RCR_ENTRY_ERROR)))
3448 skb->ip_summed = CHECKSUM_UNNECESSARY;
3449 else
3450 skb_checksum_none_assert(skb);
3451 } else if (!(val & RCR_ENTRY_MULTI))
3452 append_size = append_size - skb->len;
3453
3454 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3455 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3456 *link = (struct page *) page->mapping;
3457 np->ops->unmap_page(np->device, page->index,
3458 PAGE_SIZE, DMA_FROM_DEVICE);
3459 page->index = 0;
3460 page->mapping = NULL;
3461 rp->rbr_refill_pending++;
3462 } else
3463 get_page(page);
3464
3465 index = NEXT_RCR(rp, index);
3466 if (!(val & RCR_ENTRY_MULTI))
3467 break;
3468
3469 }
3470 rp->rcr_index = index;
3471
3472 len += sizeof(*rh);
3473 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3474 __pskb_pull_tail(skb, len);
3475
3476 rh = (struct rx_pkt_hdr1 *) skb->data;
3477 if (np->dev->features & NETIF_F_RXHASH)
3478 skb_set_hash(skb,
3479 ((u32)rh->hashval2_0 << 24 |
3480 (u32)rh->hashval2_1 << 16 |
3481 (u32)rh->hashval1_1 << 8 |
3482 (u32)rh->hashval1_2 << 0),
3483 PKT_HASH_TYPE_L3);
3484 skb_pull(skb, sizeof(*rh));
3485
3486 rp->rx_packets++;
3487 rp->rx_bytes += skb->len;
3488
3489 skb->protocol = eth_type_trans(skb, np->dev);
3490 skb_record_rx_queue(skb, rp->rx_channel);
3491 napi_gro_receive(napi, skb);
3492
3493 return num_rcr;
3494 }
3495
3496 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3497 {
3498 int blocks_per_page = rp->rbr_blocks_per_page;
3499 int err, index = rp->rbr_index;
3500
3501 err = 0;
3502 while (index < (rp->rbr_table_size - blocks_per_page)) {
3503 err = niu_rbr_add_page(np, rp, mask, index);
3504 if (unlikely(err))
3505 break;
3506
3507 index += blocks_per_page;
3508 }
3509
3510 rp->rbr_index = index;
3511 return err;
3512 }
3513
3514 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3515 {
3516 int i;
3517
3518 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3519 struct page *page;
3520
3521 page = rp->rxhash[i];
3522 while (page) {
3523 struct page *next = (struct page *) page->mapping;
3524 u64 base = page->index;
3525
3526 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3527 DMA_FROM_DEVICE);
3528 page->index = 0;
3529 page->mapping = NULL;
3530
3531 __free_page(page);
3532
3533 page = next;
3534 }
3535 }
3536
3537 for (i = 0; i < rp->rbr_table_size; i++)
3538 rp->rbr[i] = cpu_to_le32(0);
3539 rp->rbr_index = 0;
3540 }
3541
3542 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3543 {
3544 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3545 struct sk_buff *skb = tb->skb;
3546 struct tx_pkt_hdr *tp;
3547 u64 tx_flags;
3548 int i, len;
3549
3550 tp = (struct tx_pkt_hdr *) skb->data;
3551 tx_flags = le64_to_cpup(&tp->flags);
3552
3553 rp->tx_packets++;
3554 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3555 ((tx_flags & TXHDR_PAD) / 2));
3556
3557 len = skb_headlen(skb);
3558 np->ops->unmap_single(np->device, tb->mapping,
3559 len, DMA_TO_DEVICE);
3560
3561 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3562 rp->mark_pending--;
3563
3564 tb->skb = NULL;
3565 do {
3566 idx = NEXT_TX(rp, idx);
3567 len -= MAX_TX_DESC_LEN;
3568 } while (len > 0);
3569
3570 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3571 tb = &rp->tx_buffs[idx];
3572 BUG_ON(tb->skb != NULL);
3573 np->ops->unmap_page(np->device, tb->mapping,
3574 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3575 DMA_TO_DEVICE);
3576 idx = NEXT_TX(rp, idx);
3577 }
3578
3579 dev_kfree_skb(skb);
3580
3581 return idx;
3582 }
3583
3584 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3585
3586 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3587 {
3588 struct netdev_queue *txq;
3589 u16 pkt_cnt, tmp;
3590 int cons, index;
3591 u64 cs;
3592
3593 index = (rp - np->tx_rings);
3594 txq = netdev_get_tx_queue(np->dev, index);
3595
3596 cs = rp->tx_cs;
3597 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3598 goto out;
3599
3600 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3601 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3602 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3603
3604 rp->last_pkt_cnt = tmp;
3605
3606 cons = rp->cons;
3607
3608 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3609 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3610
3611 while (pkt_cnt--)
3612 cons = release_tx_packet(np, rp, cons);
3613
3614 rp->cons = cons;
3615 smp_mb();
3616
3617 out:
3618 if (unlikely(netif_tx_queue_stopped(txq) &&
3619 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3620 __netif_tx_lock(txq, smp_processor_id());
3621 if (netif_tx_queue_stopped(txq) &&
3622 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3623 netif_tx_wake_queue(txq);
3624 __netif_tx_unlock(txq);
3625 }
3626 }
3627
3628 static inline void niu_sync_rx_discard_stats(struct niu *np,
3629 struct rx_ring_info *rp,
3630 const int limit)
3631 {
3632 /* This elaborate scheme is needed for reading the RX discard
3633 * counters, as they are only 16-bit and can overflow quickly,
3634 * and because the overflow indication bit is not usable as
3635 * the counter value does not wrap, but remains at max value
3636 * 0xFFFF.
3637 *
3638 * In theory and in practice counters can be lost in between
3639 * reading nr64() and clearing the counter nw64(). For this
3640 * reason, the number of counter clearings nw64() is
3641 * limited/reduced though the limit parameter.
3642 */
3643 int rx_channel = rp->rx_channel;
3644 u32 misc, wred;
3645
3646 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3647 * following discard events: IPP (Input Port Process),
3648 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3649 * Block Ring) prefetch buffer is empty.
3650 */
3651 misc = nr64(RXMISC(rx_channel));
3652 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3653 nw64(RXMISC(rx_channel), 0);
3654 rp->rx_errors += misc & RXMISC_COUNT;
3655
3656 if (unlikely(misc & RXMISC_OFLOW))
3657 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3658 rx_channel);
3659
3660 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3661 "rx-%d: MISC drop=%u over=%u\n",
3662 rx_channel, misc, misc-limit);
3663 }
3664
3665 /* WRED (Weighted Random Early Discard) by hardware */
3666 wred = nr64(RED_DIS_CNT(rx_channel));
3667 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3668 nw64(RED_DIS_CNT(rx_channel), 0);
3669 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3670
3671 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3672 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3673
3674 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3675 "rx-%d: WRED drop=%u over=%u\n",
3676 rx_channel, wred, wred-limit);
3677 }
3678 }
3679
3680 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3681 struct rx_ring_info *rp, int budget)
3682 {
3683 int qlen, rcr_done = 0, work_done = 0;
3684 struct rxdma_mailbox *mbox = rp->mbox;
3685 u64 stat;
3686
3687 #if 1
3688 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3689 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3690 #else
3691 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3692 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3693 #endif
3694 mbox->rx_dma_ctl_stat = 0;
3695 mbox->rcrstat_a = 0;
3696
3697 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3698 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3699 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3700
3701 rcr_done = work_done = 0;
3702 qlen = min(qlen, budget);
3703 while (work_done < qlen) {
3704 rcr_done += niu_process_rx_pkt(napi, np, rp);
3705 work_done++;
3706 }
3707
3708 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3709 unsigned int i;
3710
3711 for (i = 0; i < rp->rbr_refill_pending; i++)
3712 niu_rbr_refill(np, rp, GFP_ATOMIC);
3713 rp->rbr_refill_pending = 0;
3714 }
3715
3716 stat = (RX_DMA_CTL_STAT_MEX |
3717 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3718 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3719
3720 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3721
3722 /* Only sync discards stats when qlen indicate potential for drops */
3723 if (qlen > 10)
3724 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3725
3726 return work_done;
3727 }
3728
3729 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3730 {
3731 u64 v0 = lp->v0;
3732 u32 tx_vec = (v0 >> 32);
3733 u32 rx_vec = (v0 & 0xffffffff);
3734 int i, work_done = 0;
3735
3736 netif_printk(np, intr, KERN_DEBUG, np->dev,
3737 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3738
3739 for (i = 0; i < np->num_tx_rings; i++) {
3740 struct tx_ring_info *rp = &np->tx_rings[i];
3741 if (tx_vec & (1 << rp->tx_channel))
3742 niu_tx_work(np, rp);
3743 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3744 }
3745
3746 for (i = 0; i < np->num_rx_rings; i++) {
3747 struct rx_ring_info *rp = &np->rx_rings[i];
3748
3749 if (rx_vec & (1 << rp->rx_channel)) {
3750 int this_work_done;
3751
3752 this_work_done = niu_rx_work(&lp->napi, np, rp,
3753 budget);
3754
3755 budget -= this_work_done;
3756 work_done += this_work_done;
3757 }
3758 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3759 }
3760
3761 return work_done;
3762 }
3763
3764 static int niu_poll(struct napi_struct *napi, int budget)
3765 {
3766 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3767 struct niu *np = lp->np;
3768 int work_done;
3769
3770 work_done = niu_poll_core(np, lp, budget);
3771
3772 if (work_done < budget) {
3773 napi_complete_done(napi, work_done);
3774 niu_ldg_rearm(np, lp, 1);
3775 }
3776 return work_done;
3777 }
3778
3779 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3780 u64 stat)
3781 {
3782 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3783
3784 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3785 pr_cont("RBR_TMOUT ");
3786 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3787 pr_cont("RSP_CNT ");
3788 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3789 pr_cont("BYTE_EN_BUS ");
3790 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3791 pr_cont("RSP_DAT ");
3792 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3793 pr_cont("RCR_ACK ");
3794 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3795 pr_cont("RCR_SHA_PAR ");
3796 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3797 pr_cont("RBR_PRE_PAR ");
3798 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3799 pr_cont("CONFIG ");
3800 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3801 pr_cont("RCRINCON ");
3802 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3803 pr_cont("RCRFULL ");
3804 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3805 pr_cont("RBRFULL ");
3806 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3807 pr_cont("RBRLOGPAGE ");
3808 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3809 pr_cont("CFIGLOGPAGE ");
3810 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3811 pr_cont("DC_FIDO ");
3812
3813 pr_cont(")\n");
3814 }
3815
3816 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3817 {
3818 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3819 int err = 0;
3820
3821
3822 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3823 RX_DMA_CTL_STAT_PORT_FATAL))
3824 err = -EINVAL;
3825
3826 if (err) {
3827 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3828 rp->rx_channel,
3829 (unsigned long long) stat);
3830
3831 niu_log_rxchan_errors(np, rp, stat);
3832 }
3833
3834 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3835 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3836
3837 return err;
3838 }
3839
3840 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3841 u64 cs)
3842 {
3843 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3844
3845 if (cs & TX_CS_MBOX_ERR)
3846 pr_cont("MBOX ");
3847 if (cs & TX_CS_PKT_SIZE_ERR)
3848 pr_cont("PKT_SIZE ");
3849 if (cs & TX_CS_TX_RING_OFLOW)
3850 pr_cont("TX_RING_OFLOW ");
3851 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3852 pr_cont("PREF_BUF_PAR ");
3853 if (cs & TX_CS_NACK_PREF)
3854 pr_cont("NACK_PREF ");
3855 if (cs & TX_CS_NACK_PKT_RD)
3856 pr_cont("NACK_PKT_RD ");
3857 if (cs & TX_CS_CONF_PART_ERR)
3858 pr_cont("CONF_PART ");
3859 if (cs & TX_CS_PKT_PRT_ERR)
3860 pr_cont("PKT_PTR ");
3861
3862 pr_cont(")\n");
3863 }
3864
3865 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3866 {
3867 u64 cs, logh, logl;
3868
3869 cs = nr64(TX_CS(rp->tx_channel));
3870 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3871 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3872
3873 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3874 rp->tx_channel,
3875 (unsigned long long)cs,
3876 (unsigned long long)logh,
3877 (unsigned long long)logl);
3878
3879 niu_log_txchan_errors(np, rp, cs);
3880
3881 return -ENODEV;
3882 }
3883
3884 static int niu_mif_interrupt(struct niu *np)
3885 {
3886 u64 mif_status = nr64(MIF_STATUS);
3887 int phy_mdint = 0;
3888
3889 if (np->flags & NIU_FLAGS_XMAC) {
3890 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3891
3892 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3893 phy_mdint = 1;
3894 }
3895
3896 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3897 (unsigned long long)mif_status, phy_mdint);
3898
3899 return -ENODEV;
3900 }
3901
3902 static void niu_xmac_interrupt(struct niu *np)
3903 {
3904 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3905 u64 val;
3906
3907 val = nr64_mac(XTXMAC_STATUS);
3908 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3909 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3910 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3911 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3912 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3913 mp->tx_fifo_errors++;
3914 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3915 mp->tx_overflow_errors++;
3916 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3917 mp->tx_max_pkt_size_errors++;
3918 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3919 mp->tx_underflow_errors++;
3920
3921 val = nr64_mac(XRXMAC_STATUS);
3922 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3923 mp->rx_local_faults++;
3924 if (val & XRXMAC_STATUS_RFLT_DET)
3925 mp->rx_remote_faults++;
3926 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3927 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3928 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3929 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3930 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3931 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3932 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3933 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3934 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3935 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3936 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3937 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3938 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3939 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3940 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3941 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3942 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3943 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3944 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3945 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3946 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3947 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3948 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3949 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3950 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3951 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3952 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3953 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3954 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3955 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3956 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3957 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3958 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3959 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3960 if (val & XRXMAC_STATUS_RXUFLOW)
3961 mp->rx_underflows++;
3962 if (val & XRXMAC_STATUS_RXOFLOW)
3963 mp->rx_overflows++;
3964
3965 val = nr64_mac(XMAC_FC_STAT);
3966 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3967 mp->pause_off_state++;
3968 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3969 mp->pause_on_state++;
3970 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3971 mp->pause_received++;
3972 }
3973
3974 static void niu_bmac_interrupt(struct niu *np)
3975 {
3976 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3977 u64 val;
3978
3979 val = nr64_mac(BTXMAC_STATUS);
3980 if (val & BTXMAC_STATUS_UNDERRUN)
3981 mp->tx_underflow_errors++;
3982 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3983 mp->tx_max_pkt_size_errors++;
3984 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3985 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3986 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3987 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3988
3989 val = nr64_mac(BRXMAC_STATUS);
3990 if (val & BRXMAC_STATUS_OVERFLOW)
3991 mp->rx_overflows++;
3992 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3993 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3994 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3995 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3996 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3997 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3998 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3999 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4000
4001 val = nr64_mac(BMAC_CTRL_STATUS);
4002 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4003 mp->pause_off_state++;
4004 if (val & BMAC_CTRL_STATUS_PAUSE)
4005 mp->pause_on_state++;
4006 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4007 mp->pause_received++;
4008 }
4009
4010 static int niu_mac_interrupt(struct niu *np)
4011 {
4012 if (np->flags & NIU_FLAGS_XMAC)
4013 niu_xmac_interrupt(np);
4014 else
4015 niu_bmac_interrupt(np);
4016
4017 return 0;
4018 }
4019
4020 static void niu_log_device_error(struct niu *np, u64 stat)
4021 {
4022 netdev_err(np->dev, "Core device errors ( ");
4023
4024 if (stat & SYS_ERR_MASK_META2)
4025 pr_cont("META2 ");
4026 if (stat & SYS_ERR_MASK_META1)
4027 pr_cont("META1 ");
4028 if (stat & SYS_ERR_MASK_PEU)
4029 pr_cont("PEU ");
4030 if (stat & SYS_ERR_MASK_TXC)
4031 pr_cont("TXC ");
4032 if (stat & SYS_ERR_MASK_RDMC)
4033 pr_cont("RDMC ");
4034 if (stat & SYS_ERR_MASK_TDMC)
4035 pr_cont("TDMC ");
4036 if (stat & SYS_ERR_MASK_ZCP)
4037 pr_cont("ZCP ");
4038 if (stat & SYS_ERR_MASK_FFLP)
4039 pr_cont("FFLP ");
4040 if (stat & SYS_ERR_MASK_IPP)
4041 pr_cont("IPP ");
4042 if (stat & SYS_ERR_MASK_MAC)
4043 pr_cont("MAC ");
4044 if (stat & SYS_ERR_MASK_SMX)
4045 pr_cont("SMX ");
4046
4047 pr_cont(")\n");
4048 }
4049
4050 static int niu_device_error(struct niu *np)
4051 {
4052 u64 stat = nr64(SYS_ERR_STAT);
4053
4054 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4055 (unsigned long long)stat);
4056
4057 niu_log_device_error(np, stat);
4058
4059 return -ENODEV;
4060 }
4061
4062 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4063 u64 v0, u64 v1, u64 v2)
4064 {
4065
4066 int i, err = 0;
4067
4068 lp->v0 = v0;
4069 lp->v1 = v1;
4070 lp->v2 = v2;
4071
4072 if (v1 & 0x00000000ffffffffULL) {
4073 u32 rx_vec = (v1 & 0xffffffff);
4074
4075 for (i = 0; i < np->num_rx_rings; i++) {
4076 struct rx_ring_info *rp = &np->rx_rings[i];
4077
4078 if (rx_vec & (1 << rp->rx_channel)) {
4079 int r = niu_rx_error(np, rp);
4080 if (r) {
4081 err = r;
4082 } else {
4083 if (!v0)
4084 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4085 RX_DMA_CTL_STAT_MEX);
4086 }
4087 }
4088 }
4089 }
4090 if (v1 & 0x7fffffff00000000ULL) {
4091 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4092
4093 for (i = 0; i < np->num_tx_rings; i++) {
4094 struct tx_ring_info *rp = &np->tx_rings[i];
4095
4096 if (tx_vec & (1 << rp->tx_channel)) {
4097 int r = niu_tx_error(np, rp);
4098 if (r)
4099 err = r;
4100 }
4101 }
4102 }
4103 if ((v0 | v1) & 0x8000000000000000ULL) {
4104 int r = niu_mif_interrupt(np);
4105 if (r)
4106 err = r;
4107 }
4108 if (v2) {
4109 if (v2 & 0x01ef) {
4110 int r = niu_mac_interrupt(np);
4111 if (r)
4112 err = r;
4113 }
4114 if (v2 & 0x0210) {
4115 int r = niu_device_error(np);
4116 if (r)
4117 err = r;
4118 }
4119 }
4120
4121 if (err)
4122 niu_enable_interrupts(np, 0);
4123
4124 return err;
4125 }
4126
4127 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4128 int ldn)
4129 {
4130 struct rxdma_mailbox *mbox = rp->mbox;
4131 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4132
4133 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4134 RX_DMA_CTL_STAT_RCRTO);
4135 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4136
4137 netif_printk(np, intr, KERN_DEBUG, np->dev,
4138 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4139 }
4140
4141 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4142 int ldn)
4143 {
4144 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4145
4146 netif_printk(np, intr, KERN_DEBUG, np->dev,
4147 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4148 }
4149
4150 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4151 {
4152 struct niu_parent *parent = np->parent;
4153 u32 rx_vec, tx_vec;
4154 int i;
4155
4156 tx_vec = (v0 >> 32);
4157 rx_vec = (v0 & 0xffffffff);
4158
4159 for (i = 0; i < np->num_rx_rings; i++) {
4160 struct rx_ring_info *rp = &np->rx_rings[i];
4161 int ldn = LDN_RXDMA(rp->rx_channel);
4162
4163 if (parent->ldg_map[ldn] != ldg)
4164 continue;
4165
4166 nw64(LD_IM0(ldn), LD_IM0_MASK);
4167 if (rx_vec & (1 << rp->rx_channel))
4168 niu_rxchan_intr(np, rp, ldn);
4169 }
4170
4171 for (i = 0; i < np->num_tx_rings; i++) {
4172 struct tx_ring_info *rp = &np->tx_rings[i];
4173 int ldn = LDN_TXDMA(rp->tx_channel);
4174
4175 if (parent->ldg_map[ldn] != ldg)
4176 continue;
4177
4178 nw64(LD_IM0(ldn), LD_IM0_MASK);
4179 if (tx_vec & (1 << rp->tx_channel))
4180 niu_txchan_intr(np, rp, ldn);
4181 }
4182 }
4183
4184 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4185 u64 v0, u64 v1, u64 v2)
4186 {
4187 if (likely(napi_schedule_prep(&lp->napi))) {
4188 lp->v0 = v0;
4189 lp->v1 = v1;
4190 lp->v2 = v2;
4191 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4192 __napi_schedule(&lp->napi);
4193 }
4194 }
4195
4196 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4197 {
4198 struct niu_ldg *lp = dev_id;
4199 struct niu *np = lp->np;
4200 int ldg = lp->ldg_num;
4201 unsigned long flags;
4202 u64 v0, v1, v2;
4203
4204 if (netif_msg_intr(np))
4205 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4206 __func__, lp, ldg);
4207
4208 spin_lock_irqsave(&np->lock, flags);
4209
4210 v0 = nr64(LDSV0(ldg));
4211 v1 = nr64(LDSV1(ldg));
4212 v2 = nr64(LDSV2(ldg));
4213
4214 if (netif_msg_intr(np))
4215 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4216 (unsigned long long) v0,
4217 (unsigned long long) v1,
4218 (unsigned long long) v2);
4219
4220 if (unlikely(!v0 && !v1 && !v2)) {
4221 spin_unlock_irqrestore(&np->lock, flags);
4222 return IRQ_NONE;
4223 }
4224
4225 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4226 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4227 if (err)
4228 goto out;
4229 }
4230 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4231 niu_schedule_napi(np, lp, v0, v1, v2);
4232 else
4233 niu_ldg_rearm(np, lp, 1);
4234 out:
4235 spin_unlock_irqrestore(&np->lock, flags);
4236
4237 return IRQ_HANDLED;
4238 }
4239
4240 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4241 {
4242 if (rp->mbox) {
4243 np->ops->free_coherent(np->device,
4244 sizeof(struct rxdma_mailbox),
4245 rp->mbox, rp->mbox_dma);
4246 rp->mbox = NULL;
4247 }
4248 if (rp->rcr) {
4249 np->ops->free_coherent(np->device,
4250 MAX_RCR_RING_SIZE * sizeof(__le64),
4251 rp->rcr, rp->rcr_dma);
4252 rp->rcr = NULL;
4253 rp->rcr_table_size = 0;
4254 rp->rcr_index = 0;
4255 }
4256 if (rp->rbr) {
4257 niu_rbr_free(np, rp);
4258
4259 np->ops->free_coherent(np->device,
4260 MAX_RBR_RING_SIZE * sizeof(__le32),
4261 rp->rbr, rp->rbr_dma);
4262 rp->rbr = NULL;
4263 rp->rbr_table_size = 0;
4264 rp->rbr_index = 0;
4265 }
4266 kfree(rp->rxhash);
4267 rp->rxhash = NULL;
4268 }
4269
4270 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4271 {
4272 if (rp->mbox) {
4273 np->ops->free_coherent(np->device,
4274 sizeof(struct txdma_mailbox),
4275 rp->mbox, rp->mbox_dma);
4276 rp->mbox = NULL;
4277 }
4278 if (rp->descr) {
4279 int i;
4280
4281 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4282 if (rp->tx_buffs[i].skb)
4283 (void) release_tx_packet(np, rp, i);
4284 }
4285
4286 np->ops->free_coherent(np->device,
4287 MAX_TX_RING_SIZE * sizeof(__le64),
4288 rp->descr, rp->descr_dma);
4289 rp->descr = NULL;
4290 rp->pending = 0;
4291 rp->prod = 0;
4292 rp->cons = 0;
4293 rp->wrap_bit = 0;
4294 }
4295 }
4296
4297 static void niu_free_channels(struct niu *np)
4298 {
4299 int i;
4300
4301 if (np->rx_rings) {
4302 for (i = 0; i < np->num_rx_rings; i++) {
4303 struct rx_ring_info *rp = &np->rx_rings[i];
4304
4305 niu_free_rx_ring_info(np, rp);
4306 }
4307 kfree(np->rx_rings);
4308 np->rx_rings = NULL;
4309 np->num_rx_rings = 0;
4310 }
4311
4312 if (np->tx_rings) {
4313 for (i = 0; i < np->num_tx_rings; i++) {
4314 struct tx_ring_info *rp = &np->tx_rings[i];
4315
4316 niu_free_tx_ring_info(np, rp);
4317 }
4318 kfree(np->tx_rings);
4319 np->tx_rings = NULL;
4320 np->num_tx_rings = 0;
4321 }
4322 }
4323
4324 static int niu_alloc_rx_ring_info(struct niu *np,
4325 struct rx_ring_info *rp)
4326 {
4327 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4328
4329 rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *),
4330 GFP_KERNEL);
4331 if (!rp->rxhash)
4332 return -ENOMEM;
4333
4334 rp->mbox = np->ops->alloc_coherent(np->device,
4335 sizeof(struct rxdma_mailbox),
4336 &rp->mbox_dma, GFP_KERNEL);
4337 if (!rp->mbox)
4338 return -ENOMEM;
4339 if ((unsigned long)rp->mbox & (64UL - 1)) {
4340 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4341 rp->mbox);
4342 return -EINVAL;
4343 }
4344
4345 rp->rcr = np->ops->alloc_coherent(np->device,
4346 MAX_RCR_RING_SIZE * sizeof(__le64),
4347 &rp->rcr_dma, GFP_KERNEL);
4348 if (!rp->rcr)
4349 return -ENOMEM;
4350 if ((unsigned long)rp->rcr & (64UL - 1)) {
4351 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4352 rp->rcr);
4353 return -EINVAL;
4354 }
4355 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4356 rp->rcr_index = 0;
4357
4358 rp->rbr = np->ops->alloc_coherent(np->device,
4359 MAX_RBR_RING_SIZE * sizeof(__le32),
4360 &rp->rbr_dma, GFP_KERNEL);
4361 if (!rp->rbr)
4362 return -ENOMEM;
4363 if ((unsigned long)rp->rbr & (64UL - 1)) {
4364 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4365 rp->rbr);
4366 return -EINVAL;
4367 }
4368 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4369 rp->rbr_index = 0;
4370 rp->rbr_pending = 0;
4371
4372 return 0;
4373 }
4374
4375 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4376 {
4377 int mtu = np->dev->mtu;
4378
4379 /* These values are recommended by the HW designers for fair
4380 * utilization of DRR amongst the rings.
4381 */
4382 rp->max_burst = mtu + 32;
4383 if (rp->max_burst > 4096)
4384 rp->max_burst = 4096;
4385 }
4386
4387 static int niu_alloc_tx_ring_info(struct niu *np,
4388 struct tx_ring_info *rp)
4389 {
4390 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4391
4392 rp->mbox = np->ops->alloc_coherent(np->device,
4393 sizeof(struct txdma_mailbox),
4394 &rp->mbox_dma, GFP_KERNEL);
4395 if (!rp->mbox)
4396 return -ENOMEM;
4397 if ((unsigned long)rp->mbox & (64UL - 1)) {
4398 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4399 rp->mbox);
4400 return -EINVAL;
4401 }
4402
4403 rp->descr = np->ops->alloc_coherent(np->device,
4404 MAX_TX_RING_SIZE * sizeof(__le64),
4405 &rp->descr_dma, GFP_KERNEL);
4406 if (!rp->descr)
4407 return -ENOMEM;
4408 if ((unsigned long)rp->descr & (64UL - 1)) {
4409 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4410 rp->descr);
4411 return -EINVAL;
4412 }
4413
4414 rp->pending = MAX_TX_RING_SIZE;
4415 rp->prod = 0;
4416 rp->cons = 0;
4417 rp->wrap_bit = 0;
4418
4419 /* XXX make these configurable... XXX */
4420 rp->mark_freq = rp->pending / 4;
4421
4422 niu_set_max_burst(np, rp);
4423
4424 return 0;
4425 }
4426
4427 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4428 {
4429 u16 bss;
4430
4431 bss = min(PAGE_SHIFT, 15);
4432
4433 rp->rbr_block_size = 1 << bss;
4434 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4435
4436 rp->rbr_sizes[0] = 256;
4437 rp->rbr_sizes[1] = 1024;
4438 if (np->dev->mtu > ETH_DATA_LEN) {
4439 switch (PAGE_SIZE) {
4440 case 4 * 1024:
4441 rp->rbr_sizes[2] = 4096;
4442 break;
4443
4444 default:
4445 rp->rbr_sizes[2] = 8192;
4446 break;
4447 }
4448 } else {
4449 rp->rbr_sizes[2] = 2048;
4450 }
4451 rp->rbr_sizes[3] = rp->rbr_block_size;
4452 }
4453
4454 static int niu_alloc_channels(struct niu *np)
4455 {
4456 struct niu_parent *parent = np->parent;
4457 int first_rx_channel, first_tx_channel;
4458 int num_rx_rings, num_tx_rings;
4459 struct rx_ring_info *rx_rings;
4460 struct tx_ring_info *tx_rings;
4461 int i, port, err;
4462
4463 port = np->port;
4464 first_rx_channel = first_tx_channel = 0;
4465 for (i = 0; i < port; i++) {
4466 first_rx_channel += parent->rxchan_per_port[i];
4467 first_tx_channel += parent->txchan_per_port[i];
4468 }
4469
4470 num_rx_rings = parent->rxchan_per_port[port];
4471 num_tx_rings = parent->txchan_per_port[port];
4472
4473 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4474 GFP_KERNEL);
4475 err = -ENOMEM;
4476 if (!rx_rings)
4477 goto out_err;
4478
4479 np->num_rx_rings = num_rx_rings;
4480 smp_wmb();
4481 np->rx_rings = rx_rings;
4482
4483 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4484
4485 for (i = 0; i < np->num_rx_rings; i++) {
4486 struct rx_ring_info *rp = &np->rx_rings[i];
4487
4488 rp->np = np;
4489 rp->rx_channel = first_rx_channel + i;
4490
4491 err = niu_alloc_rx_ring_info(np, rp);
4492 if (err)
4493 goto out_err;
4494
4495 niu_size_rbr(np, rp);
4496
4497 /* XXX better defaults, configurable, etc... XXX */
4498 rp->nonsyn_window = 64;
4499 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4500 rp->syn_window = 64;
4501 rp->syn_threshold = rp->rcr_table_size - 64;
4502 rp->rcr_pkt_threshold = 16;
4503 rp->rcr_timeout = 8;
4504 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4505 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4506 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4507
4508 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4509 if (err)
4510 return err;
4511 }
4512
4513 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4514 GFP_KERNEL);
4515 err = -ENOMEM;
4516 if (!tx_rings)
4517 goto out_err;
4518
4519 np->num_tx_rings = num_tx_rings;
4520 smp_wmb();
4521 np->tx_rings = tx_rings;
4522
4523 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4524
4525 for (i = 0; i < np->num_tx_rings; i++) {
4526 struct tx_ring_info *rp = &np->tx_rings[i];
4527
4528 rp->np = np;
4529 rp->tx_channel = first_tx_channel + i;
4530
4531 err = niu_alloc_tx_ring_info(np, rp);
4532 if (err)
4533 goto out_err;
4534 }
4535
4536 return 0;
4537
4538 out_err:
4539 niu_free_channels(np);
4540 return err;
4541 }
4542
4543 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4544 {
4545 int limit = 1000;
4546
4547 while (--limit > 0) {
4548 u64 val = nr64(TX_CS(channel));
4549 if (val & TX_CS_SNG_STATE)
4550 return 0;
4551 }
4552 return -ENODEV;
4553 }
4554
4555 static int niu_tx_channel_stop(struct niu *np, int channel)
4556 {
4557 u64 val = nr64(TX_CS(channel));
4558
4559 val |= TX_CS_STOP_N_GO;
4560 nw64(TX_CS(channel), val);
4561
4562 return niu_tx_cs_sng_poll(np, channel);
4563 }
4564
4565 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4566 {
4567 int limit = 1000;
4568
4569 while (--limit > 0) {
4570 u64 val = nr64(TX_CS(channel));
4571 if (!(val & TX_CS_RST))
4572 return 0;
4573 }
4574 return -ENODEV;
4575 }
4576
4577 static int niu_tx_channel_reset(struct niu *np, int channel)
4578 {
4579 u64 val = nr64(TX_CS(channel));
4580 int err;
4581
4582 val |= TX_CS_RST;
4583 nw64(TX_CS(channel), val);
4584
4585 err = niu_tx_cs_reset_poll(np, channel);
4586 if (!err)
4587 nw64(TX_RING_KICK(channel), 0);
4588
4589 return err;
4590 }
4591
4592 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4593 {
4594 u64 val;
4595
4596 nw64(TX_LOG_MASK1(channel), 0);
4597 nw64(TX_LOG_VAL1(channel), 0);
4598 nw64(TX_LOG_MASK2(channel), 0);
4599 nw64(TX_LOG_VAL2(channel), 0);
4600 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4601 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4602 nw64(TX_LOG_PAGE_HDL(channel), 0);
4603
4604 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4605 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4606 nw64(TX_LOG_PAGE_VLD(channel), val);
4607
4608 /* XXX TXDMA 32bit mode? XXX */
4609
4610 return 0;
4611 }
4612
4613 static void niu_txc_enable_port(struct niu *np, int on)
4614 {
4615 unsigned long flags;
4616 u64 val, mask;
4617
4618 niu_lock_parent(np, flags);
4619 val = nr64(TXC_CONTROL);
4620 mask = (u64)1 << np->port;
4621 if (on) {
4622 val |= TXC_CONTROL_ENABLE | mask;
4623 } else {
4624 val &= ~mask;
4625 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4626 val &= ~TXC_CONTROL_ENABLE;
4627 }
4628 nw64(TXC_CONTROL, val);
4629 niu_unlock_parent(np, flags);
4630 }
4631
4632 static void niu_txc_set_imask(struct niu *np, u64 imask)
4633 {
4634 unsigned long flags;
4635 u64 val;
4636
4637 niu_lock_parent(np, flags);
4638 val = nr64(TXC_INT_MASK);
4639 val &= ~TXC_INT_MASK_VAL(np->port);
4640 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4641 niu_unlock_parent(np, flags);
4642 }
4643
4644 static void niu_txc_port_dma_enable(struct niu *np, int on)
4645 {
4646 u64 val = 0;
4647
4648 if (on) {
4649 int i;
4650
4651 for (i = 0; i < np->num_tx_rings; i++)
4652 val |= (1 << np->tx_rings[i].tx_channel);
4653 }
4654 nw64(TXC_PORT_DMA(np->port), val);
4655 }
4656
4657 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4658 {
4659 int err, channel = rp->tx_channel;
4660 u64 val, ring_len;
4661
4662 err = niu_tx_channel_stop(np, channel);
4663 if (err)
4664 return err;
4665
4666 err = niu_tx_channel_reset(np, channel);
4667 if (err)
4668 return err;
4669
4670 err = niu_tx_channel_lpage_init(np, channel);
4671 if (err)
4672 return err;
4673
4674 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4675 nw64(TX_ENT_MSK(channel), 0);
4676
4677 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4678 TX_RNG_CFIG_STADDR)) {
4679 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4680 channel, (unsigned long long)rp->descr_dma);
4681 return -EINVAL;
4682 }
4683
4684 /* The length field in TX_RNG_CFIG is measured in 64-byte
4685 * blocks. rp->pending is the number of TX descriptors in
4686 * our ring, 8 bytes each, thus we divide by 8 bytes more
4687 * to get the proper value the chip wants.
4688 */
4689 ring_len = (rp->pending / 8);
4690
4691 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4692 rp->descr_dma);
4693 nw64(TX_RNG_CFIG(channel), val);
4694
4695 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4696 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4697 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4698 channel, (unsigned long long)rp->mbox_dma);
4699 return -EINVAL;
4700 }
4701 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4702 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4703
4704 nw64(TX_CS(channel), 0);
4705
4706 rp->last_pkt_cnt = 0;
4707
4708 return 0;
4709 }
4710
4711 static void niu_init_rdc_groups(struct niu *np)
4712 {
4713 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4714 int i, first_table_num = tp->first_table_num;
4715
4716 for (i = 0; i < tp->num_tables; i++) {
4717 struct rdc_table *tbl = &tp->tables[i];
4718 int this_table = first_table_num + i;
4719 int slot;
4720
4721 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4722 nw64(RDC_TBL(this_table, slot),
4723 tbl->rxdma_channel[slot]);
4724 }
4725
4726 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4727 }
4728
4729 static void niu_init_drr_weight(struct niu *np)
4730 {
4731 int type = phy_decode(np->parent->port_phy, np->port);
4732 u64 val;
4733
4734 switch (type) {
4735 case PORT_TYPE_10G:
4736 val = PT_DRR_WEIGHT_DEFAULT_10G;
4737 break;
4738
4739 case PORT_TYPE_1G:
4740 default:
4741 val = PT_DRR_WEIGHT_DEFAULT_1G;
4742 break;
4743 }
4744 nw64(PT_DRR_WT(np->port), val);
4745 }
4746
4747 static int niu_init_hostinfo(struct niu *np)
4748 {
4749 struct niu_parent *parent = np->parent;
4750 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4751 int i, err, num_alt = niu_num_alt_addr(np);
4752 int first_rdc_table = tp->first_table_num;
4753
4754 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4755 if (err)
4756 return err;
4757
4758 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4759 if (err)
4760 return err;
4761
4762 for (i = 0; i < num_alt; i++) {
4763 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4764 if (err)
4765 return err;
4766 }
4767
4768 return 0;
4769 }
4770
4771 static int niu_rx_channel_reset(struct niu *np, int channel)
4772 {
4773 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4774 RXDMA_CFIG1_RST, 1000, 10,
4775 "RXDMA_CFIG1");
4776 }
4777
4778 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4779 {
4780 u64 val;
4781
4782 nw64(RX_LOG_MASK1(channel), 0);
4783 nw64(RX_LOG_VAL1(channel), 0);
4784 nw64(RX_LOG_MASK2(channel), 0);
4785 nw64(RX_LOG_VAL2(channel), 0);
4786 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4787 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4788 nw64(RX_LOG_PAGE_HDL(channel), 0);
4789
4790 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4791 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4792 nw64(RX_LOG_PAGE_VLD(channel), val);
4793
4794 return 0;
4795 }
4796
4797 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4798 {
4799 u64 val;
4800
4801 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4802 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4803 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4804 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4805 nw64(RDC_RED_PARA(rp->rx_channel), val);
4806 }
4807
4808 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4809 {
4810 u64 val = 0;
4811
4812 *ret = 0;
4813 switch (rp->rbr_block_size) {
4814 case 4 * 1024:
4815 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4816 break;
4817 case 8 * 1024:
4818 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4819 break;
4820 case 16 * 1024:
4821 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4822 break;
4823 case 32 * 1024:
4824 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4825 break;
4826 default:
4827 return -EINVAL;
4828 }
4829 val |= RBR_CFIG_B_VLD2;
4830 switch (rp->rbr_sizes[2]) {
4831 case 2 * 1024:
4832 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4833 break;
4834 case 4 * 1024:
4835 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4836 break;
4837 case 8 * 1024:
4838 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4839 break;
4840 case 16 * 1024:
4841 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4842 break;
4843
4844 default:
4845 return -EINVAL;
4846 }
4847 val |= RBR_CFIG_B_VLD1;
4848 switch (rp->rbr_sizes[1]) {
4849 case 1 * 1024:
4850 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4851 break;
4852 case 2 * 1024:
4853 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4854 break;
4855 case 4 * 1024:
4856 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4857 break;
4858 case 8 * 1024:
4859 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4860 break;
4861
4862 default:
4863 return -EINVAL;
4864 }
4865 val |= RBR_CFIG_B_VLD0;
4866 switch (rp->rbr_sizes[0]) {
4867 case 256:
4868 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4869 break;
4870 case 512:
4871 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4872 break;
4873 case 1 * 1024:
4874 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4875 break;
4876 case 2 * 1024:
4877 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4878 break;
4879
4880 default:
4881 return -EINVAL;
4882 }
4883
4884 *ret = val;
4885 return 0;
4886 }
4887
4888 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4889 {
4890 u64 val = nr64(RXDMA_CFIG1(channel));
4891 int limit;
4892
4893 if (on)
4894 val |= RXDMA_CFIG1_EN;
4895 else
4896 val &= ~RXDMA_CFIG1_EN;
4897 nw64(RXDMA_CFIG1(channel), val);
4898
4899 limit = 1000;
4900 while (--limit > 0) {
4901 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4902 break;
4903 udelay(10);
4904 }
4905 if (limit <= 0)
4906 return -ENODEV;
4907 return 0;
4908 }
4909
4910 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4911 {
4912 int err, channel = rp->rx_channel;
4913 u64 val;
4914
4915 err = niu_rx_channel_reset(np, channel);
4916 if (err)
4917 return err;
4918
4919 err = niu_rx_channel_lpage_init(np, channel);
4920 if (err)
4921 return err;
4922
4923 niu_rx_channel_wred_init(np, rp);
4924
4925 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4926 nw64(RX_DMA_CTL_STAT(channel),
4927 (RX_DMA_CTL_STAT_MEX |
4928 RX_DMA_CTL_STAT_RCRTHRES |
4929 RX_DMA_CTL_STAT_RCRTO |
4930 RX_DMA_CTL_STAT_RBR_EMPTY));
4931 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4932 nw64(RXDMA_CFIG2(channel),
4933 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4934 RXDMA_CFIG2_FULL_HDR));
4935 nw64(RBR_CFIG_A(channel),
4936 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4937 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4938 err = niu_compute_rbr_cfig_b(rp, &val);
4939 if (err)
4940 return err;
4941 nw64(RBR_CFIG_B(channel), val);
4942 nw64(RCRCFIG_A(channel),
4943 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4944 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4945 nw64(RCRCFIG_B(channel),
4946 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4947 RCRCFIG_B_ENTOUT |
4948 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4949
4950 err = niu_enable_rx_channel(np, channel, 1);
4951 if (err)
4952 return err;
4953
4954 nw64(RBR_KICK(channel), rp->rbr_index);
4955
4956 val = nr64(RX_DMA_CTL_STAT(channel));
4957 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4958 nw64(RX_DMA_CTL_STAT(channel), val);
4959
4960 return 0;
4961 }
4962
4963 static int niu_init_rx_channels(struct niu *np)
4964 {
4965 unsigned long flags;
4966 u64 seed = jiffies_64;
4967 int err, i;
4968
4969 niu_lock_parent(np, flags);
4970 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4971 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4972 niu_unlock_parent(np, flags);
4973
4974 /* XXX RXDMA 32bit mode? XXX */
4975
4976 niu_init_rdc_groups(np);
4977 niu_init_drr_weight(np);
4978
4979 err = niu_init_hostinfo(np);
4980 if (err)
4981 return err;
4982
4983 for (i = 0; i < np->num_rx_rings; i++) {
4984 struct rx_ring_info *rp = &np->rx_rings[i];
4985
4986 err = niu_init_one_rx_channel(np, rp);
4987 if (err)
4988 return err;
4989 }
4990
4991 return 0;
4992 }
4993
4994 static int niu_set_ip_frag_rule(struct niu *np)
4995 {
4996 struct niu_parent *parent = np->parent;
4997 struct niu_classifier *cp = &np->clas;
4998 struct niu_tcam_entry *tp;
4999 int index, err;
5000
5001 index = cp->tcam_top;
5002 tp = &parent->tcam[index];
5003
5004 /* Note that the noport bit is the same in both ipv4 and
5005 * ipv6 format TCAM entries.
5006 */
5007 memset(tp, 0, sizeof(*tp));
5008 tp->key[1] = TCAM_V4KEY1_NOPORT;
5009 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5010 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5011 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5012 err = tcam_write(np, index, tp->key, tp->key_mask);
5013 if (err)
5014 return err;
5015 err = tcam_assoc_write(np, index, tp->assoc_data);
5016 if (err)
5017 return err;
5018 tp->valid = 1;
5019 cp->tcam_valid_entries++;
5020
5021 return 0;
5022 }
5023
5024 static int niu_init_classifier_hw(struct niu *np)
5025 {
5026 struct niu_parent *parent = np->parent;
5027 struct niu_classifier *cp = &np->clas;
5028 int i, err;
5029
5030 nw64(H1POLY, cp->h1_init);
5031 nw64(H2POLY, cp->h2_init);
5032
5033 err = niu_init_hostinfo(np);
5034 if (err)
5035 return err;
5036
5037 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5038 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5039
5040 vlan_tbl_write(np, i, np->port,
5041 vp->vlan_pref, vp->rdc_num);
5042 }
5043
5044 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5045 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5046
5047 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5048 ap->rdc_num, ap->mac_pref);
5049 if (err)
5050 return err;
5051 }
5052
5053 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5054 int index = i - CLASS_CODE_USER_PROG1;
5055
5056 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5057 if (err)
5058 return err;
5059 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5060 if (err)
5061 return err;
5062 }
5063
5064 err = niu_set_ip_frag_rule(np);
5065 if (err)
5066 return err;
5067
5068 tcam_enable(np, 1);
5069
5070 return 0;
5071 }
5072
5073 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5074 {
5075 nw64(ZCP_RAM_DATA0, data[0]);
5076 nw64(ZCP_RAM_DATA1, data[1]);
5077 nw64(ZCP_RAM_DATA2, data[2]);
5078 nw64(ZCP_RAM_DATA3, data[3]);
5079 nw64(ZCP_RAM_DATA4, data[4]);
5080 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5081 nw64(ZCP_RAM_ACC,
5082 (ZCP_RAM_ACC_WRITE |
5083 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5084 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5085
5086 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5087 1000, 100);
5088 }
5089
5090 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5091 {
5092 int err;
5093
5094 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5095 1000, 100);
5096 if (err) {
5097 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5098 (unsigned long long)nr64(ZCP_RAM_ACC));
5099 return err;
5100 }
5101
5102 nw64(ZCP_RAM_ACC,
5103 (ZCP_RAM_ACC_READ |
5104 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5105 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5106
5107 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5108 1000, 100);
5109 if (err) {
5110 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5111 (unsigned long long)nr64(ZCP_RAM_ACC));
5112 return err;
5113 }
5114
5115 data[0] = nr64(ZCP_RAM_DATA0);
5116 data[1] = nr64(ZCP_RAM_DATA1);
5117 data[2] = nr64(ZCP_RAM_DATA2);
5118 data[3] = nr64(ZCP_RAM_DATA3);
5119 data[4] = nr64(ZCP_RAM_DATA4);
5120
5121 return 0;
5122 }
5123
5124 static void niu_zcp_cfifo_reset(struct niu *np)
5125 {
5126 u64 val = nr64(RESET_CFIFO);
5127
5128 val |= RESET_CFIFO_RST(np->port);
5129 nw64(RESET_CFIFO, val);
5130 udelay(10);
5131
5132 val &= ~RESET_CFIFO_RST(np->port);
5133 nw64(RESET_CFIFO, val);
5134 }
5135
5136 static int niu_init_zcp(struct niu *np)
5137 {
5138 u64 data[5], rbuf[5];
5139 int i, max, err;
5140
5141 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5142 if (np->port == 0 || np->port == 1)
5143 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5144 else
5145 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5146 } else
5147 max = NIU_CFIFO_ENTRIES;
5148
5149 data[0] = 0;
5150 data[1] = 0;
5151 data[2] = 0;
5152 data[3] = 0;
5153 data[4] = 0;
5154
5155 for (i = 0; i < max; i++) {
5156 err = niu_zcp_write(np, i, data);
5157 if (err)
5158 return err;
5159 err = niu_zcp_read(np, i, rbuf);
5160 if (err)
5161 return err;
5162 }
5163
5164 niu_zcp_cfifo_reset(np);
5165 nw64(CFIFO_ECC(np->port), 0);
5166 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5167 (void) nr64(ZCP_INT_STAT);
5168 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5169
5170 return 0;
5171 }
5172
5173 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5174 {
5175 u64 val = nr64_ipp(IPP_CFIG);
5176
5177 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5178 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5179 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5180 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5181 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5182 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5183 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5184 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5185 }
5186
5187 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5188 {
5189 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5190 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5191 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5192 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5193 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5194 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5195 }
5196
5197 static int niu_ipp_reset(struct niu *np)
5198 {
5199 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5200 1000, 100, "IPP_CFIG");
5201 }
5202
5203 static int niu_init_ipp(struct niu *np)
5204 {
5205 u64 data[5], rbuf[5], val;
5206 int i, max, err;
5207
5208 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5209 if (np->port == 0 || np->port == 1)
5210 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5211 else
5212 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5213 } else
5214 max = NIU_DFIFO_ENTRIES;
5215
5216 data[0] = 0;
5217 data[1] = 0;
5218 data[2] = 0;
5219 data[3] = 0;
5220 data[4] = 0;
5221
5222 for (i = 0; i < max; i++) {
5223 niu_ipp_write(np, i, data);
5224 niu_ipp_read(np, i, rbuf);
5225 }
5226
5227 (void) nr64_ipp(IPP_INT_STAT);
5228 (void) nr64_ipp(IPP_INT_STAT);
5229
5230 err = niu_ipp_reset(np);
5231 if (err)
5232 return err;
5233
5234 (void) nr64_ipp(IPP_PKT_DIS);
5235 (void) nr64_ipp(IPP_BAD_CS_CNT);
5236 (void) nr64_ipp(IPP_ECC);
5237
5238 (void) nr64_ipp(IPP_INT_STAT);
5239
5240 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5241
5242 val = nr64_ipp(IPP_CFIG);
5243 val &= ~IPP_CFIG_IP_MAX_PKT;
5244 val |= (IPP_CFIG_IPP_ENABLE |
5245 IPP_CFIG_DFIFO_ECC_EN |
5246 IPP_CFIG_DROP_BAD_CRC |
5247 IPP_CFIG_CKSUM_EN |
5248 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5249 nw64_ipp(IPP_CFIG, val);
5250
5251 return 0;
5252 }
5253
5254 static void niu_handle_led(struct niu *np, int status)
5255 {
5256 u64 val;
5257 val = nr64_mac(XMAC_CONFIG);
5258
5259 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5260 (np->flags & NIU_FLAGS_FIBER) != 0) {
5261 if (status) {
5262 val |= XMAC_CONFIG_LED_POLARITY;
5263 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5264 } else {
5265 val |= XMAC_CONFIG_FORCE_LED_ON;
5266 val &= ~XMAC_CONFIG_LED_POLARITY;
5267 }
5268 }
5269
5270 nw64_mac(XMAC_CONFIG, val);
5271 }
5272
5273 static void niu_init_xif_xmac(struct niu *np)
5274 {
5275 struct niu_link_config *lp = &np->link_config;
5276 u64 val;
5277
5278 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5279 val = nr64(MIF_CONFIG);
5280 val |= MIF_CONFIG_ATCA_GE;
5281 nw64(MIF_CONFIG, val);
5282 }
5283
5284 val = nr64_mac(XMAC_CONFIG);
5285 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5286
5287 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5288
5289 if (lp->loopback_mode == LOOPBACK_MAC) {
5290 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5291 val |= XMAC_CONFIG_LOOPBACK;
5292 } else {
5293 val &= ~XMAC_CONFIG_LOOPBACK;
5294 }
5295
5296 if (np->flags & NIU_FLAGS_10G) {
5297 val &= ~XMAC_CONFIG_LFS_DISABLE;
5298 } else {
5299 val |= XMAC_CONFIG_LFS_DISABLE;
5300 if (!(np->flags & NIU_FLAGS_FIBER) &&
5301 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5302 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5303 else
5304 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5305 }
5306
5307 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5308
5309 if (lp->active_speed == SPEED_100)
5310 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5311 else
5312 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5313
5314 nw64_mac(XMAC_CONFIG, val);
5315
5316 val = nr64_mac(XMAC_CONFIG);
5317 val &= ~XMAC_CONFIG_MODE_MASK;
5318 if (np->flags & NIU_FLAGS_10G) {
5319 val |= XMAC_CONFIG_MODE_XGMII;
5320 } else {
5321 if (lp->active_speed == SPEED_1000)
5322 val |= XMAC_CONFIG_MODE_GMII;
5323 else
5324 val |= XMAC_CONFIG_MODE_MII;
5325 }
5326
5327 nw64_mac(XMAC_CONFIG, val);
5328 }
5329
5330 static void niu_init_xif_bmac(struct niu *np)
5331 {
5332 struct niu_link_config *lp = &np->link_config;
5333 u64 val;
5334
5335 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5336
5337 if (lp->loopback_mode == LOOPBACK_MAC)
5338 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5339 else
5340 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5341
5342 if (lp->active_speed == SPEED_1000)
5343 val |= BMAC_XIF_CONFIG_GMII_MODE;
5344 else
5345 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5346
5347 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5348 BMAC_XIF_CONFIG_LED_POLARITY);
5349
5350 if (!(np->flags & NIU_FLAGS_10G) &&
5351 !(np->flags & NIU_FLAGS_FIBER) &&
5352 lp->active_speed == SPEED_100)
5353 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5354 else
5355 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5356
5357 nw64_mac(BMAC_XIF_CONFIG, val);
5358 }
5359
5360 static void niu_init_xif(struct niu *np)
5361 {
5362 if (np->flags & NIU_FLAGS_XMAC)
5363 niu_init_xif_xmac(np);
5364 else
5365 niu_init_xif_bmac(np);
5366 }
5367
5368 static void niu_pcs_mii_reset(struct niu *np)
5369 {
5370 int limit = 1000;
5371 u64 val = nr64_pcs(PCS_MII_CTL);
5372 val |= PCS_MII_CTL_RST;
5373 nw64_pcs(PCS_MII_CTL, val);
5374 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5375 udelay(100);
5376 val = nr64_pcs(PCS_MII_CTL);
5377 }
5378 }
5379
5380 static void niu_xpcs_reset(struct niu *np)
5381 {
5382 int limit = 1000;
5383 u64 val = nr64_xpcs(XPCS_CONTROL1);
5384 val |= XPCS_CONTROL1_RESET;
5385 nw64_xpcs(XPCS_CONTROL1, val);
5386 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5387 udelay(100);
5388 val = nr64_xpcs(XPCS_CONTROL1);
5389 }
5390 }
5391
5392 static int niu_init_pcs(struct niu *np)
5393 {
5394 struct niu_link_config *lp = &np->link_config;
5395 u64 val;
5396
5397 switch (np->flags & (NIU_FLAGS_10G |
5398 NIU_FLAGS_FIBER |
5399 NIU_FLAGS_XCVR_SERDES)) {
5400 case NIU_FLAGS_FIBER:
5401 /* 1G fiber */
5402 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5403 nw64_pcs(PCS_DPATH_MODE, 0);
5404 niu_pcs_mii_reset(np);
5405 break;
5406
5407 case NIU_FLAGS_10G:
5408 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5409 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5410 /* 10G SERDES */
5411 if (!(np->flags & NIU_FLAGS_XMAC))
5412 return -EINVAL;
5413
5414 /* 10G copper or fiber */
5415 val = nr64_mac(XMAC_CONFIG);
5416 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5417 nw64_mac(XMAC_CONFIG, val);
5418
5419 niu_xpcs_reset(np);
5420
5421 val = nr64_xpcs(XPCS_CONTROL1);
5422 if (lp->loopback_mode == LOOPBACK_PHY)
5423 val |= XPCS_CONTROL1_LOOPBACK;
5424 else
5425 val &= ~XPCS_CONTROL1_LOOPBACK;
5426 nw64_xpcs(XPCS_CONTROL1, val);
5427
5428 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5429 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5430 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5431 break;
5432
5433
5434 case NIU_FLAGS_XCVR_SERDES:
5435 /* 1G SERDES */
5436 niu_pcs_mii_reset(np);
5437 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5438 nw64_pcs(PCS_DPATH_MODE, 0);
5439 break;
5440
5441 case 0:
5442 /* 1G copper */
5443 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5444 /* 1G RGMII FIBER */
5445 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5446 niu_pcs_mii_reset(np);
5447 break;
5448
5449 default:
5450 return -EINVAL;
5451 }
5452
5453 return 0;
5454 }
5455
5456 static int niu_reset_tx_xmac(struct niu *np)
5457 {
5458 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5459 (XTXMAC_SW_RST_REG_RS |
5460 XTXMAC_SW_RST_SOFT_RST),
5461 1000, 100, "XTXMAC_SW_RST");
5462 }
5463
5464 static int niu_reset_tx_bmac(struct niu *np)
5465 {
5466 int limit;
5467
5468 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5469 limit = 1000;
5470 while (--limit >= 0) {
5471 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5472 break;
5473 udelay(100);
5474 }
5475 if (limit < 0) {
5476 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5477 np->port,
5478 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5479 return -ENODEV;
5480 }
5481
5482 return 0;
5483 }
5484
5485 static int niu_reset_tx_mac(struct niu *np)
5486 {
5487 if (np->flags & NIU_FLAGS_XMAC)
5488 return niu_reset_tx_xmac(np);
5489 else
5490 return niu_reset_tx_bmac(np);
5491 }
5492
5493 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5494 {
5495 u64 val;
5496
5497 val = nr64_mac(XMAC_MIN);
5498 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5499 XMAC_MIN_RX_MIN_PKT_SIZE);
5500 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5501 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5502 nw64_mac(XMAC_MIN, val);
5503
5504 nw64_mac(XMAC_MAX, max);
5505
5506 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5507
5508 val = nr64_mac(XMAC_IPG);
5509 if (np->flags & NIU_FLAGS_10G) {
5510 val &= ~XMAC_IPG_IPG_XGMII;
5511 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5512 } else {
5513 val &= ~XMAC_IPG_IPG_MII_GMII;
5514 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5515 }
5516 nw64_mac(XMAC_IPG, val);
5517
5518 val = nr64_mac(XMAC_CONFIG);
5519 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5520 XMAC_CONFIG_STRETCH_MODE |
5521 XMAC_CONFIG_VAR_MIN_IPG_EN |
5522 XMAC_CONFIG_TX_ENABLE);
5523 nw64_mac(XMAC_CONFIG, val);
5524
5525 nw64_mac(TXMAC_FRM_CNT, 0);
5526 nw64_mac(TXMAC_BYTE_CNT, 0);
5527 }
5528
5529 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5530 {
5531 u64 val;
5532
5533 nw64_mac(BMAC_MIN_FRAME, min);
5534 nw64_mac(BMAC_MAX_FRAME, max);
5535
5536 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5537 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5538 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5539
5540 val = nr64_mac(BTXMAC_CONFIG);
5541 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5542 BTXMAC_CONFIG_ENABLE);
5543 nw64_mac(BTXMAC_CONFIG, val);
5544 }
5545
5546 static void niu_init_tx_mac(struct niu *np)
5547 {
5548 u64 min, max;
5549
5550 min = 64;
5551 if (np->dev->mtu > ETH_DATA_LEN)
5552 max = 9216;
5553 else
5554 max = 1522;
5555
5556 /* The XMAC_MIN register only accepts values for TX min which
5557 * have the low 3 bits cleared.
5558 */
5559 BUG_ON(min & 0x7);
5560
5561 if (np->flags & NIU_FLAGS_XMAC)
5562 niu_init_tx_xmac(np, min, max);
5563 else
5564 niu_init_tx_bmac(np, min, max);
5565 }
5566
5567 static int niu_reset_rx_xmac(struct niu *np)
5568 {
5569 int limit;
5570
5571 nw64_mac(XRXMAC_SW_RST,
5572 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5573 limit = 1000;
5574 while (--limit >= 0) {
5575 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5576 XRXMAC_SW_RST_SOFT_RST)))
5577 break;
5578 udelay(100);
5579 }
5580 if (limit < 0) {
5581 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5582 np->port,
5583 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5584 return -ENODEV;
5585 }
5586
5587 return 0;
5588 }
5589
5590 static int niu_reset_rx_bmac(struct niu *np)
5591 {
5592 int limit;
5593
5594 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5595 limit = 1000;
5596 while (--limit >= 0) {
5597 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5598 break;
5599 udelay(100);
5600 }
5601 if (limit < 0) {
5602 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5603 np->port,
5604 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5605 return -ENODEV;
5606 }
5607
5608 return 0;
5609 }
5610
5611 static int niu_reset_rx_mac(struct niu *np)
5612 {
5613 if (np->flags & NIU_FLAGS_XMAC)
5614 return niu_reset_rx_xmac(np);
5615 else
5616 return niu_reset_rx_bmac(np);
5617 }
5618
5619 static void niu_init_rx_xmac(struct niu *np)
5620 {
5621 struct niu_parent *parent = np->parent;
5622 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5623 int first_rdc_table = tp->first_table_num;
5624 unsigned long i;
5625 u64 val;
5626
5627 nw64_mac(XMAC_ADD_FILT0, 0);
5628 nw64_mac(XMAC_ADD_FILT1, 0);
5629 nw64_mac(XMAC_ADD_FILT2, 0);
5630 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5631 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5632 for (i = 0; i < MAC_NUM_HASH; i++)
5633 nw64_mac(XMAC_HASH_TBL(i), 0);
5634 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5635 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5636 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5637
5638 val = nr64_mac(XMAC_CONFIG);
5639 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5640 XMAC_CONFIG_PROMISCUOUS |
5641 XMAC_CONFIG_PROMISC_GROUP |
5642 XMAC_CONFIG_ERR_CHK_DIS |
5643 XMAC_CONFIG_RX_CRC_CHK_DIS |
5644 XMAC_CONFIG_RESERVED_MULTICAST |
5645 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5646 XMAC_CONFIG_ADDR_FILTER_EN |
5647 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5648 XMAC_CONFIG_STRIP_CRC |
5649 XMAC_CONFIG_PASS_FLOW_CTRL |
5650 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5651 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5652 nw64_mac(XMAC_CONFIG, val);
5653
5654 nw64_mac(RXMAC_BT_CNT, 0);
5655 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5656 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5657 nw64_mac(RXMAC_FRAG_CNT, 0);
5658 nw64_mac(RXMAC_HIST_CNT1, 0);
5659 nw64_mac(RXMAC_HIST_CNT2, 0);
5660 nw64_mac(RXMAC_HIST_CNT3, 0);
5661 nw64_mac(RXMAC_HIST_CNT4, 0);
5662 nw64_mac(RXMAC_HIST_CNT5, 0);
5663 nw64_mac(RXMAC_HIST_CNT6, 0);
5664 nw64_mac(RXMAC_HIST_CNT7, 0);
5665 nw64_mac(RXMAC_MPSZER_CNT, 0);
5666 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5667 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5668 nw64_mac(LINK_FAULT_CNT, 0);
5669 }
5670
5671 static void niu_init_rx_bmac(struct niu *np)
5672 {
5673 struct niu_parent *parent = np->parent;
5674 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5675 int first_rdc_table = tp->first_table_num;
5676 unsigned long i;
5677 u64 val;
5678
5679 nw64_mac(BMAC_ADD_FILT0, 0);
5680 nw64_mac(BMAC_ADD_FILT1, 0);
5681 nw64_mac(BMAC_ADD_FILT2, 0);
5682 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5683 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5684 for (i = 0; i < MAC_NUM_HASH; i++)
5685 nw64_mac(BMAC_HASH_TBL(i), 0);
5686 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5687 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5688 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5689
5690 val = nr64_mac(BRXMAC_CONFIG);
5691 val &= ~(BRXMAC_CONFIG_ENABLE |
5692 BRXMAC_CONFIG_STRIP_PAD |
5693 BRXMAC_CONFIG_STRIP_FCS |
5694 BRXMAC_CONFIG_PROMISC |
5695 BRXMAC_CONFIG_PROMISC_GRP |
5696 BRXMAC_CONFIG_ADDR_FILT_EN |
5697 BRXMAC_CONFIG_DISCARD_DIS);
5698 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5699 nw64_mac(BRXMAC_CONFIG, val);
5700
5701 val = nr64_mac(BMAC_ADDR_CMPEN);
5702 val |= BMAC_ADDR_CMPEN_EN0;
5703 nw64_mac(BMAC_ADDR_CMPEN, val);
5704 }
5705
5706 static void niu_init_rx_mac(struct niu *np)
5707 {
5708 niu_set_primary_mac(np, np->dev->dev_addr);
5709
5710 if (np->flags & NIU_FLAGS_XMAC)
5711 niu_init_rx_xmac(np);
5712 else
5713 niu_init_rx_bmac(np);
5714 }
5715
5716 static void niu_enable_tx_xmac(struct niu *np, int on)
5717 {
5718 u64 val = nr64_mac(XMAC_CONFIG);
5719
5720 if (on)
5721 val |= XMAC_CONFIG_TX_ENABLE;
5722 else
5723 val &= ~XMAC_CONFIG_TX_ENABLE;
5724 nw64_mac(XMAC_CONFIG, val);
5725 }
5726
5727 static void niu_enable_tx_bmac(struct niu *np, int on)
5728 {
5729 u64 val = nr64_mac(BTXMAC_CONFIG);
5730
5731 if (on)
5732 val |= BTXMAC_CONFIG_ENABLE;
5733 else
5734 val &= ~BTXMAC_CONFIG_ENABLE;
5735 nw64_mac(BTXMAC_CONFIG, val);
5736 }
5737
5738 static void niu_enable_tx_mac(struct niu *np, int on)
5739 {
5740 if (np->flags & NIU_FLAGS_XMAC)
5741 niu_enable_tx_xmac(np, on);
5742 else
5743 niu_enable_tx_bmac(np, on);
5744 }
5745
5746 static void niu_enable_rx_xmac(struct niu *np, int on)
5747 {
5748 u64 val = nr64_mac(XMAC_CONFIG);
5749
5750 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5751 XMAC_CONFIG_PROMISCUOUS);
5752
5753 if (np->flags & NIU_FLAGS_MCAST)
5754 val |= XMAC_CONFIG_HASH_FILTER_EN;
5755 if (np->flags & NIU_FLAGS_PROMISC)
5756 val |= XMAC_CONFIG_PROMISCUOUS;
5757
5758 if (on)
5759 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5760 else
5761 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5762 nw64_mac(XMAC_CONFIG, val);
5763 }
5764
5765 static void niu_enable_rx_bmac(struct niu *np, int on)
5766 {
5767 u64 val = nr64_mac(BRXMAC_CONFIG);
5768
5769 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5770 BRXMAC_CONFIG_PROMISC);
5771
5772 if (np->flags & NIU_FLAGS_MCAST)
5773 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5774 if (np->flags & NIU_FLAGS_PROMISC)
5775 val |= BRXMAC_CONFIG_PROMISC;
5776
5777 if (on)
5778 val |= BRXMAC_CONFIG_ENABLE;
5779 else
5780 val &= ~BRXMAC_CONFIG_ENABLE;
5781 nw64_mac(BRXMAC_CONFIG, val);
5782 }
5783
5784 static void niu_enable_rx_mac(struct niu *np, int on)
5785 {
5786 if (np->flags & NIU_FLAGS_XMAC)
5787 niu_enable_rx_xmac(np, on);
5788 else
5789 niu_enable_rx_bmac(np, on);
5790 }
5791
5792 static int niu_init_mac(struct niu *np)
5793 {
5794 int err;
5795
5796 niu_init_xif(np);
5797 err = niu_init_pcs(np);
5798 if (err)
5799 return err;
5800
5801 err = niu_reset_tx_mac(np);
5802 if (err)
5803 return err;
5804 niu_init_tx_mac(np);
5805 err = niu_reset_rx_mac(np);
5806 if (err)
5807 return err;
5808 niu_init_rx_mac(np);
5809
5810 /* This looks hookey but the RX MAC reset we just did will
5811 * undo some of the state we setup in niu_init_tx_mac() so we
5812 * have to call it again. In particular, the RX MAC reset will
5813 * set the XMAC_MAX register back to it's default value.
5814 */
5815 niu_init_tx_mac(np);
5816 niu_enable_tx_mac(np, 1);
5817
5818 niu_enable_rx_mac(np, 1);
5819
5820 return 0;
5821 }
5822
5823 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5824 {
5825 (void) niu_tx_channel_stop(np, rp->tx_channel);
5826 }
5827
5828 static void niu_stop_tx_channels(struct niu *np)
5829 {
5830 int i;
5831
5832 for (i = 0; i < np->num_tx_rings; i++) {
5833 struct tx_ring_info *rp = &np->tx_rings[i];
5834
5835 niu_stop_one_tx_channel(np, rp);
5836 }
5837 }
5838
5839 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5840 {
5841 (void) niu_tx_channel_reset(np, rp->tx_channel);
5842 }
5843
5844 static void niu_reset_tx_channels(struct niu *np)
5845 {
5846 int i;
5847
5848 for (i = 0; i < np->num_tx_rings; i++) {
5849 struct tx_ring_info *rp = &np->tx_rings[i];
5850
5851 niu_reset_one_tx_channel(np, rp);
5852 }
5853 }
5854
5855 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5856 {
5857 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5858 }
5859
5860 static void niu_stop_rx_channels(struct niu *np)
5861 {
5862 int i;
5863
5864 for (i = 0; i < np->num_rx_rings; i++) {
5865 struct rx_ring_info *rp = &np->rx_rings[i];
5866
5867 niu_stop_one_rx_channel(np, rp);
5868 }
5869 }
5870
5871 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5872 {
5873 int channel = rp->rx_channel;
5874
5875 (void) niu_rx_channel_reset(np, channel);
5876 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5877 nw64(RX_DMA_CTL_STAT(channel), 0);
5878 (void) niu_enable_rx_channel(np, channel, 0);
5879 }
5880
5881 static void niu_reset_rx_channels(struct niu *np)
5882 {
5883 int i;
5884
5885 for (i = 0; i < np->num_rx_rings; i++) {
5886 struct rx_ring_info *rp = &np->rx_rings[i];
5887
5888 niu_reset_one_rx_channel(np, rp);
5889 }
5890 }
5891
5892 static void niu_disable_ipp(struct niu *np)
5893 {
5894 u64 rd, wr, val;
5895 int limit;
5896
5897 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5898 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5899 limit = 100;
5900 while (--limit >= 0 && (rd != wr)) {
5901 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5902 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5903 }
5904 if (limit < 0 &&
5905 (rd != 0 && wr != 1)) {
5906 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5907 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5908 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5909 }
5910
5911 val = nr64_ipp(IPP_CFIG);
5912 val &= ~(IPP_CFIG_IPP_ENABLE |
5913 IPP_CFIG_DFIFO_ECC_EN |
5914 IPP_CFIG_DROP_BAD_CRC |
5915 IPP_CFIG_CKSUM_EN);
5916 nw64_ipp(IPP_CFIG, val);
5917
5918 (void) niu_ipp_reset(np);
5919 }
5920
5921 static int niu_init_hw(struct niu *np)
5922 {
5923 int i, err;
5924
5925 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5926 niu_txc_enable_port(np, 1);
5927 niu_txc_port_dma_enable(np, 1);
5928 niu_txc_set_imask(np, 0);
5929
5930 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5931 for (i = 0; i < np->num_tx_rings; i++) {
5932 struct tx_ring_info *rp = &np->tx_rings[i];
5933
5934 err = niu_init_one_tx_channel(np, rp);
5935 if (err)
5936 return err;
5937 }
5938
5939 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5940 err = niu_init_rx_channels(np);
5941 if (err)
5942 goto out_uninit_tx_channels;
5943
5944 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5945 err = niu_init_classifier_hw(np);
5946 if (err)
5947 goto out_uninit_rx_channels;
5948
5949 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5950 err = niu_init_zcp(np);
5951 if (err)
5952 goto out_uninit_rx_channels;
5953
5954 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5955 err = niu_init_ipp(np);
5956 if (err)
5957 goto out_uninit_rx_channels;
5958
5959 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5960 err = niu_init_mac(np);
5961 if (err)
5962 goto out_uninit_ipp;
5963
5964 return 0;
5965
5966 out_uninit_ipp:
5967 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5968 niu_disable_ipp(np);
5969
5970 out_uninit_rx_channels:
5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5972 niu_stop_rx_channels(np);
5973 niu_reset_rx_channels(np);
5974
5975 out_uninit_tx_channels:
5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5977 niu_stop_tx_channels(np);
5978 niu_reset_tx_channels(np);
5979
5980 return err;
5981 }
5982
5983 static void niu_stop_hw(struct niu *np)
5984 {
5985 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
5986 niu_enable_interrupts(np, 0);
5987
5988 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
5989 niu_enable_rx_mac(np, 0);
5990
5991 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
5992 niu_disable_ipp(np);
5993
5994 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
5995 niu_stop_tx_channels(np);
5996
5997 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
5998 niu_stop_rx_channels(np);
5999
6000 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6001 niu_reset_tx_channels(np);
6002
6003 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6004 niu_reset_rx_channels(np);
6005 }
6006
6007 static void niu_set_irq_name(struct niu *np)
6008 {
6009 int port = np->port;
6010 int i, j = 1;
6011
6012 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6013
6014 if (port == 0) {
6015 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6016 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6017 j = 3;
6018 }
6019
6020 for (i = 0; i < np->num_ldg - j; i++) {
6021 if (i < np->num_rx_rings)
6022 sprintf(np->irq_name[i+j], "%s-rx-%d",
6023 np->dev->name, i);
6024 else if (i < np->num_tx_rings + np->num_rx_rings)
6025 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6026 i - np->num_rx_rings);
6027 }
6028 }
6029
6030 static int niu_request_irq(struct niu *np)
6031 {
6032 int i, j, err;
6033
6034 niu_set_irq_name(np);
6035
6036 err = 0;
6037 for (i = 0; i < np->num_ldg; i++) {
6038 struct niu_ldg *lp = &np->ldg[i];
6039
6040 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6041 np->irq_name[i], lp);
6042 if (err)
6043 goto out_free_irqs;
6044
6045 }
6046
6047 return 0;
6048
6049 out_free_irqs:
6050 for (j = 0; j < i; j++) {
6051 struct niu_ldg *lp = &np->ldg[j];
6052
6053 free_irq(lp->irq, lp);
6054 }
6055 return err;
6056 }
6057
6058 static void niu_free_irq(struct niu *np)
6059 {
6060 int i;
6061
6062 for (i = 0; i < np->num_ldg; i++) {
6063 struct niu_ldg *lp = &np->ldg[i];
6064
6065 free_irq(lp->irq, lp);
6066 }
6067 }
6068
6069 static void niu_enable_napi(struct niu *np)
6070 {
6071 int i;
6072
6073 for (i = 0; i < np->num_ldg; i++)
6074 napi_enable(&np->ldg[i].napi);
6075 }
6076
6077 static void niu_disable_napi(struct niu *np)
6078 {
6079 int i;
6080
6081 for (i = 0; i < np->num_ldg; i++)
6082 napi_disable(&np->ldg[i].napi);
6083 }
6084
6085 static int niu_open(struct net_device *dev)
6086 {
6087 struct niu *np = netdev_priv(dev);
6088 int err;
6089
6090 netif_carrier_off(dev);
6091
6092 err = niu_alloc_channels(np);
6093 if (err)
6094 goto out_err;
6095
6096 err = niu_enable_interrupts(np, 0);
6097 if (err)
6098 goto out_free_channels;
6099
6100 err = niu_request_irq(np);
6101 if (err)
6102 goto out_free_channels;
6103
6104 niu_enable_napi(np);
6105
6106 spin_lock_irq(&np->lock);
6107
6108 err = niu_init_hw(np);
6109 if (!err) {
6110 timer_setup(&np->timer, niu_timer, 0);
6111 np->timer.expires = jiffies + HZ;
6112
6113 err = niu_enable_interrupts(np, 1);
6114 if (err)
6115 niu_stop_hw(np);
6116 }
6117
6118 spin_unlock_irq(&np->lock);
6119
6120 if (err) {
6121 niu_disable_napi(np);
6122 goto out_free_irq;
6123 }
6124
6125 netif_tx_start_all_queues(dev);
6126
6127 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6128 netif_carrier_on(dev);
6129
6130 add_timer(&np->timer);
6131
6132 return 0;
6133
6134 out_free_irq:
6135 niu_free_irq(np);
6136
6137 out_free_channels:
6138 niu_free_channels(np);
6139
6140 out_err:
6141 return err;
6142 }
6143
6144 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6145 {
6146 cancel_work_sync(&np->reset_task);
6147
6148 niu_disable_napi(np);
6149 netif_tx_stop_all_queues(dev);
6150
6151 del_timer_sync(&np->timer);
6152
6153 spin_lock_irq(&np->lock);
6154
6155 niu_stop_hw(np);
6156
6157 spin_unlock_irq(&np->lock);
6158 }
6159
6160 static int niu_close(struct net_device *dev)
6161 {
6162 struct niu *np = netdev_priv(dev);
6163
6164 niu_full_shutdown(np, dev);
6165
6166 niu_free_irq(np);
6167
6168 niu_free_channels(np);
6169
6170 niu_handle_led(np, 0);
6171
6172 return 0;
6173 }
6174
6175 static void niu_sync_xmac_stats(struct niu *np)
6176 {
6177 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6178
6179 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6180 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6181
6182 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6183 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6184 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6185 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6186 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6187 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6188 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6189 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6190 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6191 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6192 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6193 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6194 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6195 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6196 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6197 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6198 }
6199
6200 static void niu_sync_bmac_stats(struct niu *np)
6201 {
6202 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6203
6204 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6205 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6206
6207 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6208 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6209 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6210 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6211 }
6212
6213 static void niu_sync_mac_stats(struct niu *np)
6214 {
6215 if (np->flags & NIU_FLAGS_XMAC)
6216 niu_sync_xmac_stats(np);
6217 else
6218 niu_sync_bmac_stats(np);
6219 }
6220
6221 static void niu_get_rx_stats(struct niu *np,
6222 struct rtnl_link_stats64 *stats)
6223 {
6224 u64 pkts, dropped, errors, bytes;
6225 struct rx_ring_info *rx_rings;
6226 int i;
6227
6228 pkts = dropped = errors = bytes = 0;
6229
6230 rx_rings = READ_ONCE(np->rx_rings);
6231 if (!rx_rings)
6232 goto no_rings;
6233
6234 for (i = 0; i < np->num_rx_rings; i++) {
6235 struct rx_ring_info *rp = &rx_rings[i];
6236
6237 niu_sync_rx_discard_stats(np, rp, 0);
6238
6239 pkts += rp->rx_packets;
6240 bytes += rp->rx_bytes;
6241 dropped += rp->rx_dropped;
6242 errors += rp->rx_errors;
6243 }
6244
6245 no_rings:
6246 stats->rx_packets = pkts;
6247 stats->rx_bytes = bytes;
6248 stats->rx_dropped = dropped;
6249 stats->rx_errors = errors;
6250 }
6251
6252 static void niu_get_tx_stats(struct niu *np,
6253 struct rtnl_link_stats64 *stats)
6254 {
6255 u64 pkts, errors, bytes;
6256 struct tx_ring_info *tx_rings;
6257 int i;
6258
6259 pkts = errors = bytes = 0;
6260
6261 tx_rings = READ_ONCE(np->tx_rings);
6262 if (!tx_rings)
6263 goto no_rings;
6264
6265 for (i = 0; i < np->num_tx_rings; i++) {
6266 struct tx_ring_info *rp = &tx_rings[i];
6267
6268 pkts += rp->tx_packets;
6269 bytes += rp->tx_bytes;
6270 errors += rp->tx_errors;
6271 }
6272
6273 no_rings:
6274 stats->tx_packets = pkts;
6275 stats->tx_bytes = bytes;
6276 stats->tx_errors = errors;
6277 }
6278
6279 static void niu_get_stats(struct net_device *dev,
6280 struct rtnl_link_stats64 *stats)
6281 {
6282 struct niu *np = netdev_priv(dev);
6283
6284 if (netif_running(dev)) {
6285 niu_get_rx_stats(np, stats);
6286 niu_get_tx_stats(np, stats);
6287 }
6288 }
6289
6290 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6291 {
6292 int i;
6293
6294 for (i = 0; i < 16; i++)
6295 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6296 }
6297
6298 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6299 {
6300 int i;
6301
6302 for (i = 0; i < 16; i++)
6303 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6304 }
6305
6306 static void niu_load_hash(struct niu *np, u16 *hash)
6307 {
6308 if (np->flags & NIU_FLAGS_XMAC)
6309 niu_load_hash_xmac(np, hash);
6310 else
6311 niu_load_hash_bmac(np, hash);
6312 }
6313
6314 static void niu_set_rx_mode(struct net_device *dev)
6315 {
6316 struct niu *np = netdev_priv(dev);
6317 int i, alt_cnt, err;
6318 struct netdev_hw_addr *ha;
6319 unsigned long flags;
6320 u16 hash[16] = { 0, };
6321
6322 spin_lock_irqsave(&np->lock, flags);
6323 niu_enable_rx_mac(np, 0);
6324
6325 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6326 if (dev->flags & IFF_PROMISC)
6327 np->flags |= NIU_FLAGS_PROMISC;
6328 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6329 np->flags |= NIU_FLAGS_MCAST;
6330
6331 alt_cnt = netdev_uc_count(dev);
6332 if (alt_cnt > niu_num_alt_addr(np)) {
6333 alt_cnt = 0;
6334 np->flags |= NIU_FLAGS_PROMISC;
6335 }
6336
6337 if (alt_cnt) {
6338 int index = 0;
6339
6340 netdev_for_each_uc_addr(ha, dev) {
6341 err = niu_set_alt_mac(np, index, ha->addr);
6342 if (err)
6343 netdev_warn(dev, "Error %d adding alt mac %d\n",
6344 err, index);
6345 err = niu_enable_alt_mac(np, index, 1);
6346 if (err)
6347 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6348 err, index);
6349
6350 index++;
6351 }
6352 } else {
6353 int alt_start;
6354 if (np->flags & NIU_FLAGS_XMAC)
6355 alt_start = 0;
6356 else
6357 alt_start = 1;
6358 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6359 err = niu_enable_alt_mac(np, i, 0);
6360 if (err)
6361 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6362 err, i);
6363 }
6364 }
6365 if (dev->flags & IFF_ALLMULTI) {
6366 for (i = 0; i < 16; i++)
6367 hash[i] = 0xffff;
6368 } else if (!netdev_mc_empty(dev)) {
6369 netdev_for_each_mc_addr(ha, dev) {
6370 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6371
6372 crc >>= 24;
6373 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6374 }
6375 }
6376
6377 if (np->flags & NIU_FLAGS_MCAST)
6378 niu_load_hash(np, hash);
6379
6380 niu_enable_rx_mac(np, 1);
6381 spin_unlock_irqrestore(&np->lock, flags);
6382 }
6383
6384 static int niu_set_mac_addr(struct net_device *dev, void *p)
6385 {
6386 struct niu *np = netdev_priv(dev);
6387 struct sockaddr *addr = p;
6388 unsigned long flags;
6389
6390 if (!is_valid_ether_addr(addr->sa_data))
6391 return -EADDRNOTAVAIL;
6392
6393 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6394
6395 if (!netif_running(dev))
6396 return 0;
6397
6398 spin_lock_irqsave(&np->lock, flags);
6399 niu_enable_rx_mac(np, 0);
6400 niu_set_primary_mac(np, dev->dev_addr);
6401 niu_enable_rx_mac(np, 1);
6402 spin_unlock_irqrestore(&np->lock, flags);
6403
6404 return 0;
6405 }
6406
6407 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6408 {
6409 return -EOPNOTSUPP;
6410 }
6411
6412 static void niu_netif_stop(struct niu *np)
6413 {
6414 netif_trans_update(np->dev); /* prevent tx timeout */
6415
6416 niu_disable_napi(np);
6417
6418 netif_tx_disable(np->dev);
6419 }
6420
6421 static void niu_netif_start(struct niu *np)
6422 {
6423 /* NOTE: unconditional netif_wake_queue is only appropriate
6424 * so long as all callers are assured to have free tx slots
6425 * (such as after niu_init_hw).
6426 */
6427 netif_tx_wake_all_queues(np->dev);
6428
6429 niu_enable_napi(np);
6430
6431 niu_enable_interrupts(np, 1);
6432 }
6433
6434 static void niu_reset_buffers(struct niu *np)
6435 {
6436 int i, j, k, err;
6437
6438 if (np->rx_rings) {
6439 for (i = 0; i < np->num_rx_rings; i++) {
6440 struct rx_ring_info *rp = &np->rx_rings[i];
6441
6442 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6443 struct page *page;
6444
6445 page = rp->rxhash[j];
6446 while (page) {
6447 struct page *next =
6448 (struct page *) page->mapping;
6449 u64 base = page->index;
6450 base = base >> RBR_DESCR_ADDR_SHIFT;
6451 rp->rbr[k++] = cpu_to_le32(base);
6452 page = next;
6453 }
6454 }
6455 for (; k < MAX_RBR_RING_SIZE; k++) {
6456 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6457 if (unlikely(err))
6458 break;
6459 }
6460
6461 rp->rbr_index = rp->rbr_table_size - 1;
6462 rp->rcr_index = 0;
6463 rp->rbr_pending = 0;
6464 rp->rbr_refill_pending = 0;
6465 }
6466 }
6467 if (np->tx_rings) {
6468 for (i = 0; i < np->num_tx_rings; i++) {
6469 struct tx_ring_info *rp = &np->tx_rings[i];
6470
6471 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6472 if (rp->tx_buffs[j].skb)
6473 (void) release_tx_packet(np, rp, j);
6474 }
6475
6476 rp->pending = MAX_TX_RING_SIZE;
6477 rp->prod = 0;
6478 rp->cons = 0;
6479 rp->wrap_bit = 0;
6480 }
6481 }
6482 }
6483
6484 static void niu_reset_task(struct work_struct *work)
6485 {
6486 struct niu *np = container_of(work, struct niu, reset_task);
6487 unsigned long flags;
6488 int err;
6489
6490 spin_lock_irqsave(&np->lock, flags);
6491 if (!netif_running(np->dev)) {
6492 spin_unlock_irqrestore(&np->lock, flags);
6493 return;
6494 }
6495
6496 spin_unlock_irqrestore(&np->lock, flags);
6497
6498 del_timer_sync(&np->timer);
6499
6500 niu_netif_stop(np);
6501
6502 spin_lock_irqsave(&np->lock, flags);
6503
6504 niu_stop_hw(np);
6505
6506 spin_unlock_irqrestore(&np->lock, flags);
6507
6508 niu_reset_buffers(np);
6509
6510 spin_lock_irqsave(&np->lock, flags);
6511
6512 err = niu_init_hw(np);
6513 if (!err) {
6514 np->timer.expires = jiffies + HZ;
6515 add_timer(&np->timer);
6516 niu_netif_start(np);
6517 }
6518
6519 spin_unlock_irqrestore(&np->lock, flags);
6520 }
6521
6522 static void niu_tx_timeout(struct net_device *dev)
6523 {
6524 struct niu *np = netdev_priv(dev);
6525
6526 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6527 dev->name);
6528
6529 schedule_work(&np->reset_task);
6530 }
6531
6532 static void niu_set_txd(struct tx_ring_info *rp, int index,
6533 u64 mapping, u64 len, u64 mark,
6534 u64 n_frags)
6535 {
6536 __le64 *desc = &rp->descr[index];
6537
6538 *desc = cpu_to_le64(mark |
6539 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6540 (len << TX_DESC_TR_LEN_SHIFT) |
6541 (mapping & TX_DESC_SAD));
6542 }
6543
6544 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6545 u64 pad_bytes, u64 len)
6546 {
6547 u16 eth_proto, eth_proto_inner;
6548 u64 csum_bits, l3off, ihl, ret;
6549 u8 ip_proto;
6550 int ipv6;
6551
6552 eth_proto = be16_to_cpu(ehdr->h_proto);
6553 eth_proto_inner = eth_proto;
6554 if (eth_proto == ETH_P_8021Q) {
6555 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6556 __be16 val = vp->h_vlan_encapsulated_proto;
6557
6558 eth_proto_inner = be16_to_cpu(val);
6559 }
6560
6561 ipv6 = ihl = 0;
6562 switch (skb->protocol) {
6563 case cpu_to_be16(ETH_P_IP):
6564 ip_proto = ip_hdr(skb)->protocol;
6565 ihl = ip_hdr(skb)->ihl;
6566 break;
6567 case cpu_to_be16(ETH_P_IPV6):
6568 ip_proto = ipv6_hdr(skb)->nexthdr;
6569 ihl = (40 >> 2);
6570 ipv6 = 1;
6571 break;
6572 default:
6573 ip_proto = ihl = 0;
6574 break;
6575 }
6576
6577 csum_bits = TXHDR_CSUM_NONE;
6578 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6579 u64 start, stuff;
6580
6581 csum_bits = (ip_proto == IPPROTO_TCP ?
6582 TXHDR_CSUM_TCP :
6583 (ip_proto == IPPROTO_UDP ?
6584 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6585
6586 start = skb_checksum_start_offset(skb) -
6587 (pad_bytes + sizeof(struct tx_pkt_hdr));
6588 stuff = start + skb->csum_offset;
6589
6590 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6591 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6592 }
6593
6594 l3off = skb_network_offset(skb) -
6595 (pad_bytes + sizeof(struct tx_pkt_hdr));
6596
6597 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6598 (len << TXHDR_LEN_SHIFT) |
6599 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6600 (ihl << TXHDR_IHL_SHIFT) |
6601 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) |
6602 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6603 (ipv6 ? TXHDR_IP_VER : 0) |
6604 csum_bits);
6605
6606 return ret;
6607 }
6608
6609 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6610 struct net_device *dev)
6611 {
6612 struct niu *np = netdev_priv(dev);
6613 unsigned long align, headroom;
6614 struct netdev_queue *txq;
6615 struct tx_ring_info *rp;
6616 struct tx_pkt_hdr *tp;
6617 unsigned int len, nfg;
6618 struct ethhdr *ehdr;
6619 int prod, i, tlen;
6620 u64 mapping, mrk;
6621
6622 i = skb_get_queue_mapping(skb);
6623 rp = &np->tx_rings[i];
6624 txq = netdev_get_tx_queue(dev, i);
6625
6626 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6627 netif_tx_stop_queue(txq);
6628 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6629 rp->tx_errors++;
6630 return NETDEV_TX_BUSY;
6631 }
6632
6633 if (eth_skb_pad(skb))
6634 goto out;
6635
6636 len = sizeof(struct tx_pkt_hdr) + 15;
6637 if (skb_headroom(skb) < len) {
6638 struct sk_buff *skb_new;
6639
6640 skb_new = skb_realloc_headroom(skb, len);
6641 if (!skb_new)
6642 goto out_drop;
6643 kfree_skb(skb);
6644 skb = skb_new;
6645 } else
6646 skb_orphan(skb);
6647
6648 align = ((unsigned long) skb->data & (16 - 1));
6649 headroom = align + sizeof(struct tx_pkt_hdr);
6650
6651 ehdr = (struct ethhdr *) skb->data;
6652 tp = skb_push(skb, headroom);
6653
6654 len = skb->len - sizeof(struct tx_pkt_hdr);
6655 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6656 tp->resv = 0;
6657
6658 len = skb_headlen(skb);
6659 mapping = np->ops->map_single(np->device, skb->data,
6660 len, DMA_TO_DEVICE);
6661
6662 prod = rp->prod;
6663
6664 rp->tx_buffs[prod].skb = skb;
6665 rp->tx_buffs[prod].mapping = mapping;
6666
6667 mrk = TX_DESC_SOP;
6668 if (++rp->mark_counter == rp->mark_freq) {
6669 rp->mark_counter = 0;
6670 mrk |= TX_DESC_MARK;
6671 rp->mark_pending++;
6672 }
6673
6674 tlen = len;
6675 nfg = skb_shinfo(skb)->nr_frags;
6676 while (tlen > 0) {
6677 tlen -= MAX_TX_DESC_LEN;
6678 nfg++;
6679 }
6680
6681 while (len > 0) {
6682 unsigned int this_len = len;
6683
6684 if (this_len > MAX_TX_DESC_LEN)
6685 this_len = MAX_TX_DESC_LEN;
6686
6687 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6688 mrk = nfg = 0;
6689
6690 prod = NEXT_TX(rp, prod);
6691 mapping += this_len;
6692 len -= this_len;
6693 }
6694
6695 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6696 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6697
6698 len = skb_frag_size(frag);
6699 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6700 frag->page_offset, len,
6701 DMA_TO_DEVICE);
6702
6703 rp->tx_buffs[prod].skb = NULL;
6704 rp->tx_buffs[prod].mapping = mapping;
6705
6706 niu_set_txd(rp, prod, mapping, len, 0, 0);
6707
6708 prod = NEXT_TX(rp, prod);
6709 }
6710
6711 if (prod < rp->prod)
6712 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6713 rp->prod = prod;
6714
6715 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6716
6717 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6718 netif_tx_stop_queue(txq);
6719 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6720 netif_tx_wake_queue(txq);
6721 }
6722
6723 out:
6724 return NETDEV_TX_OK;
6725
6726 out_drop:
6727 rp->tx_errors++;
6728 kfree_skb(skb);
6729 goto out;
6730 }
6731
6732 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6733 {
6734 struct niu *np = netdev_priv(dev);
6735 int err, orig_jumbo, new_jumbo;
6736
6737 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6738 new_jumbo = (new_mtu > ETH_DATA_LEN);
6739
6740 dev->mtu = new_mtu;
6741
6742 if (!netif_running(dev) ||
6743 (orig_jumbo == new_jumbo))
6744 return 0;
6745
6746 niu_full_shutdown(np, dev);
6747
6748 niu_free_channels(np);
6749
6750 niu_enable_napi(np);
6751
6752 err = niu_alloc_channels(np);
6753 if (err)
6754 return err;
6755
6756 spin_lock_irq(&np->lock);
6757
6758 err = niu_init_hw(np);
6759 if (!err) {
6760 timer_setup(&np->timer, niu_timer, 0);
6761 np->timer.expires = jiffies + HZ;
6762
6763 err = niu_enable_interrupts(np, 1);
6764 if (err)
6765 niu_stop_hw(np);
6766 }
6767
6768 spin_unlock_irq(&np->lock);
6769
6770 if (!err) {
6771 netif_tx_start_all_queues(dev);
6772 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6773 netif_carrier_on(dev);
6774
6775 add_timer(&np->timer);
6776 }
6777
6778 return err;
6779 }
6780
6781 static void niu_get_drvinfo(struct net_device *dev,
6782 struct ethtool_drvinfo *info)
6783 {
6784 struct niu *np = netdev_priv(dev);
6785 struct niu_vpd *vpd = &np->vpd;
6786
6787 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6788 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6789 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6790 vpd->fcode_major, vpd->fcode_minor);
6791 if (np->parent->plat_type != PLAT_TYPE_NIU)
6792 strlcpy(info->bus_info, pci_name(np->pdev),
6793 sizeof(info->bus_info));
6794 }
6795
6796 static int niu_get_link_ksettings(struct net_device *dev,
6797 struct ethtool_link_ksettings *cmd)
6798 {
6799 struct niu *np = netdev_priv(dev);
6800 struct niu_link_config *lp;
6801
6802 lp = &np->link_config;
6803
6804 memset(cmd, 0, sizeof(*cmd));
6805 cmd->base.phy_address = np->phy_addr;
6806 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6807 lp->supported);
6808 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6809 lp->active_advertising);
6810 cmd->base.autoneg = lp->active_autoneg;
6811 cmd->base.speed = lp->active_speed;
6812 cmd->base.duplex = lp->active_duplex;
6813 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6814
6815 return 0;
6816 }
6817
6818 static int niu_set_link_ksettings(struct net_device *dev,
6819 const struct ethtool_link_ksettings *cmd)
6820 {
6821 struct niu *np = netdev_priv(dev);
6822 struct niu_link_config *lp = &np->link_config;
6823
6824 ethtool_convert_link_mode_to_legacy_u32(&lp->advertising,
6825 cmd->link_modes.advertising);
6826 lp->speed = cmd->base.speed;
6827 lp->duplex = cmd->base.duplex;
6828 lp->autoneg = cmd->base.autoneg;
6829 return niu_init_link(np);
6830 }
6831
6832 static u32 niu_get_msglevel(struct net_device *dev)
6833 {
6834 struct niu *np = netdev_priv(dev);
6835 return np->msg_enable;
6836 }
6837
6838 static void niu_set_msglevel(struct net_device *dev, u32 value)
6839 {
6840 struct niu *np = netdev_priv(dev);
6841 np->msg_enable = value;
6842 }
6843
6844 static int niu_nway_reset(struct net_device *dev)
6845 {
6846 struct niu *np = netdev_priv(dev);
6847
6848 if (np->link_config.autoneg)
6849 return niu_init_link(np);
6850
6851 return 0;
6852 }
6853
6854 static int niu_get_eeprom_len(struct net_device *dev)
6855 {
6856 struct niu *np = netdev_priv(dev);
6857
6858 return np->eeprom_len;
6859 }
6860
6861 static int niu_get_eeprom(struct net_device *dev,
6862 struct ethtool_eeprom *eeprom, u8 *data)
6863 {
6864 struct niu *np = netdev_priv(dev);
6865 u32 offset, len, val;
6866
6867 offset = eeprom->offset;
6868 len = eeprom->len;
6869
6870 if (offset + len < offset)
6871 return -EINVAL;
6872 if (offset >= np->eeprom_len)
6873 return -EINVAL;
6874 if (offset + len > np->eeprom_len)
6875 len = eeprom->len = np->eeprom_len - offset;
6876
6877 if (offset & 3) {
6878 u32 b_offset, b_count;
6879
6880 b_offset = offset & 3;
6881 b_count = 4 - b_offset;
6882 if (b_count > len)
6883 b_count = len;
6884
6885 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6886 memcpy(data, ((char *)&val) + b_offset, b_count);
6887 data += b_count;
6888 len -= b_count;
6889 offset += b_count;
6890 }
6891 while (len >= 4) {
6892 val = nr64(ESPC_NCR(offset / 4));
6893 memcpy(data, &val, 4);
6894 data += 4;
6895 len -= 4;
6896 offset += 4;
6897 }
6898 if (len) {
6899 val = nr64(ESPC_NCR(offset / 4));
6900 memcpy(data, &val, len);
6901 }
6902 return 0;
6903 }
6904
6905 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6906 {
6907 switch (flow_type) {
6908 case TCP_V4_FLOW:
6909 case TCP_V6_FLOW:
6910 *pid = IPPROTO_TCP;
6911 break;
6912 case UDP_V4_FLOW:
6913 case UDP_V6_FLOW:
6914 *pid = IPPROTO_UDP;
6915 break;
6916 case SCTP_V4_FLOW:
6917 case SCTP_V6_FLOW:
6918 *pid = IPPROTO_SCTP;
6919 break;
6920 case AH_V4_FLOW:
6921 case AH_V6_FLOW:
6922 *pid = IPPROTO_AH;
6923 break;
6924 case ESP_V4_FLOW:
6925 case ESP_V6_FLOW:
6926 *pid = IPPROTO_ESP;
6927 break;
6928 default:
6929 *pid = 0;
6930 break;
6931 }
6932 }
6933
6934 static int niu_class_to_ethflow(u64 class, int *flow_type)
6935 {
6936 switch (class) {
6937 case CLASS_CODE_TCP_IPV4:
6938 *flow_type = TCP_V4_FLOW;
6939 break;
6940 case CLASS_CODE_UDP_IPV4:
6941 *flow_type = UDP_V4_FLOW;
6942 break;
6943 case CLASS_CODE_AH_ESP_IPV4:
6944 *flow_type = AH_V4_FLOW;
6945 break;
6946 case CLASS_CODE_SCTP_IPV4:
6947 *flow_type = SCTP_V4_FLOW;
6948 break;
6949 case CLASS_CODE_TCP_IPV6:
6950 *flow_type = TCP_V6_FLOW;
6951 break;
6952 case CLASS_CODE_UDP_IPV6:
6953 *flow_type = UDP_V6_FLOW;
6954 break;
6955 case CLASS_CODE_AH_ESP_IPV6:
6956 *flow_type = AH_V6_FLOW;
6957 break;
6958 case CLASS_CODE_SCTP_IPV6:
6959 *flow_type = SCTP_V6_FLOW;
6960 break;
6961 case CLASS_CODE_USER_PROG1:
6962 case CLASS_CODE_USER_PROG2:
6963 case CLASS_CODE_USER_PROG3:
6964 case CLASS_CODE_USER_PROG4:
6965 *flow_type = IP_USER_FLOW;
6966 break;
6967 default:
6968 return -EINVAL;
6969 }
6970
6971 return 0;
6972 }
6973
6974 static int niu_ethflow_to_class(int flow_type, u64 *class)
6975 {
6976 switch (flow_type) {
6977 case TCP_V4_FLOW:
6978 *class = CLASS_CODE_TCP_IPV4;
6979 break;
6980 case UDP_V4_FLOW:
6981 *class = CLASS_CODE_UDP_IPV4;
6982 break;
6983 case AH_ESP_V4_FLOW:
6984 case AH_V4_FLOW:
6985 case ESP_V4_FLOW:
6986 *class = CLASS_CODE_AH_ESP_IPV4;
6987 break;
6988 case SCTP_V4_FLOW:
6989 *class = CLASS_CODE_SCTP_IPV4;
6990 break;
6991 case TCP_V6_FLOW:
6992 *class = CLASS_CODE_TCP_IPV6;
6993 break;
6994 case UDP_V6_FLOW:
6995 *class = CLASS_CODE_UDP_IPV6;
6996 break;
6997 case AH_ESP_V6_FLOW:
6998 case AH_V6_FLOW:
6999 case ESP_V6_FLOW:
7000 *class = CLASS_CODE_AH_ESP_IPV6;
7001 break;
7002 case SCTP_V6_FLOW:
7003 *class = CLASS_CODE_SCTP_IPV6;
7004 break;
7005 default:
7006 return 0;
7007 }
7008
7009 return 1;
7010 }
7011
7012 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7013 {
7014 u64 ethflow = 0;
7015
7016 if (flow_key & FLOW_KEY_L2DA)
7017 ethflow |= RXH_L2DA;
7018 if (flow_key & FLOW_KEY_VLAN)
7019 ethflow |= RXH_VLAN;
7020 if (flow_key & FLOW_KEY_IPSA)
7021 ethflow |= RXH_IP_SRC;
7022 if (flow_key & FLOW_KEY_IPDA)
7023 ethflow |= RXH_IP_DST;
7024 if (flow_key & FLOW_KEY_PROTO)
7025 ethflow |= RXH_L3_PROTO;
7026 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7027 ethflow |= RXH_L4_B_0_1;
7028 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7029 ethflow |= RXH_L4_B_2_3;
7030
7031 return ethflow;
7032
7033 }
7034
7035 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7036 {
7037 u64 key = 0;
7038
7039 if (ethflow & RXH_L2DA)
7040 key |= FLOW_KEY_L2DA;
7041 if (ethflow & RXH_VLAN)
7042 key |= FLOW_KEY_VLAN;
7043 if (ethflow & RXH_IP_SRC)
7044 key |= FLOW_KEY_IPSA;
7045 if (ethflow & RXH_IP_DST)
7046 key |= FLOW_KEY_IPDA;
7047 if (ethflow & RXH_L3_PROTO)
7048 key |= FLOW_KEY_PROTO;
7049 if (ethflow & RXH_L4_B_0_1)
7050 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7051 if (ethflow & RXH_L4_B_2_3)
7052 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7053
7054 *flow_key = key;
7055
7056 return 1;
7057
7058 }
7059
7060 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7061 {
7062 u64 class;
7063
7064 nfc->data = 0;
7065
7066 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7067 return -EINVAL;
7068
7069 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7070 TCAM_KEY_DISC)
7071 nfc->data = RXH_DISCARD;
7072 else
7073 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7074 CLASS_CODE_USER_PROG1]);
7075 return 0;
7076 }
7077
7078 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7079 struct ethtool_rx_flow_spec *fsp)
7080 {
7081 u32 tmp;
7082 u16 prt;
7083
7084 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7085 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7086
7087 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7088 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7089
7090 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7091 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7092
7093 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7094 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7095
7096 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7097 TCAM_V4KEY2_TOS_SHIFT;
7098 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7099 TCAM_V4KEY2_TOS_SHIFT;
7100
7101 switch (fsp->flow_type) {
7102 case TCP_V4_FLOW:
7103 case UDP_V4_FLOW:
7104 case SCTP_V4_FLOW:
7105 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7106 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7107 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7108
7109 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7110 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7111 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7112
7113 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7114 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7115 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7116
7117 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7118 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7119 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7120 break;
7121 case AH_V4_FLOW:
7122 case ESP_V4_FLOW:
7123 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7124 TCAM_V4KEY2_PORT_SPI_SHIFT;
7125 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7126
7127 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7128 TCAM_V4KEY2_PORT_SPI_SHIFT;
7129 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7130 break;
7131 case IP_USER_FLOW:
7132 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7133 TCAM_V4KEY2_PORT_SPI_SHIFT;
7134 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7135
7136 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7137 TCAM_V4KEY2_PORT_SPI_SHIFT;
7138 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7139
7140 fsp->h_u.usr_ip4_spec.proto =
7141 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7142 TCAM_V4KEY2_PROTO_SHIFT;
7143 fsp->m_u.usr_ip4_spec.proto =
7144 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7145 TCAM_V4KEY2_PROTO_SHIFT;
7146
7147 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7148 break;
7149 default:
7150 break;
7151 }
7152 }
7153
7154 static int niu_get_ethtool_tcam_entry(struct niu *np,
7155 struct ethtool_rxnfc *nfc)
7156 {
7157 struct niu_parent *parent = np->parent;
7158 struct niu_tcam_entry *tp;
7159 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7160 u16 idx;
7161 u64 class;
7162 int ret = 0;
7163
7164 idx = tcam_get_index(np, (u16)nfc->fs.location);
7165
7166 tp = &parent->tcam[idx];
7167 if (!tp->valid) {
7168 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7169 parent->index, (u16)nfc->fs.location, idx);
7170 return -EINVAL;
7171 }
7172
7173 /* fill the flow spec entry */
7174 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7175 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7176 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7177 if (ret < 0) {
7178 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7179 parent->index);
7180 goto out;
7181 }
7182
7183 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7184 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7185 TCAM_V4KEY2_PROTO_SHIFT;
7186 if (proto == IPPROTO_ESP) {
7187 if (fsp->flow_type == AH_V4_FLOW)
7188 fsp->flow_type = ESP_V4_FLOW;
7189 else
7190 fsp->flow_type = ESP_V6_FLOW;
7191 }
7192 }
7193
7194 switch (fsp->flow_type) {
7195 case TCP_V4_FLOW:
7196 case UDP_V4_FLOW:
7197 case SCTP_V4_FLOW:
7198 case AH_V4_FLOW:
7199 case ESP_V4_FLOW:
7200 niu_get_ip4fs_from_tcam_key(tp, fsp);
7201 break;
7202 case TCP_V6_FLOW:
7203 case UDP_V6_FLOW:
7204 case SCTP_V6_FLOW:
7205 case AH_V6_FLOW:
7206 case ESP_V6_FLOW:
7207 /* Not yet implemented */
7208 ret = -EINVAL;
7209 break;
7210 case IP_USER_FLOW:
7211 niu_get_ip4fs_from_tcam_key(tp, fsp);
7212 break;
7213 default:
7214 ret = -EINVAL;
7215 break;
7216 }
7217
7218 if (ret < 0)
7219 goto out;
7220
7221 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7222 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7223 else
7224 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7225 TCAM_ASSOCDATA_OFFSET_SHIFT;
7226
7227 /* put the tcam size here */
7228 nfc->data = tcam_get_size(np);
7229 out:
7230 return ret;
7231 }
7232
7233 static int niu_get_ethtool_tcam_all(struct niu *np,
7234 struct ethtool_rxnfc *nfc,
7235 u32 *rule_locs)
7236 {
7237 struct niu_parent *parent = np->parent;
7238 struct niu_tcam_entry *tp;
7239 int i, idx, cnt;
7240 unsigned long flags;
7241 int ret = 0;
7242
7243 /* put the tcam size here */
7244 nfc->data = tcam_get_size(np);
7245
7246 niu_lock_parent(np, flags);
7247 for (cnt = 0, i = 0; i < nfc->data; i++) {
7248 idx = tcam_get_index(np, i);
7249 tp = &parent->tcam[idx];
7250 if (!tp->valid)
7251 continue;
7252 if (cnt == nfc->rule_cnt) {
7253 ret = -EMSGSIZE;
7254 break;
7255 }
7256 rule_locs[cnt] = i;
7257 cnt++;
7258 }
7259 niu_unlock_parent(np, flags);
7260
7261 nfc->rule_cnt = cnt;
7262
7263 return ret;
7264 }
7265
7266 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7267 u32 *rule_locs)
7268 {
7269 struct niu *np = netdev_priv(dev);
7270 int ret = 0;
7271
7272 switch (cmd->cmd) {
7273 case ETHTOOL_GRXFH:
7274 ret = niu_get_hash_opts(np, cmd);
7275 break;
7276 case ETHTOOL_GRXRINGS:
7277 cmd->data = np->num_rx_rings;
7278 break;
7279 case ETHTOOL_GRXCLSRLCNT:
7280 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7281 break;
7282 case ETHTOOL_GRXCLSRULE:
7283 ret = niu_get_ethtool_tcam_entry(np, cmd);
7284 break;
7285 case ETHTOOL_GRXCLSRLALL:
7286 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7287 break;
7288 default:
7289 ret = -EINVAL;
7290 break;
7291 }
7292
7293 return ret;
7294 }
7295
7296 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7297 {
7298 u64 class;
7299 u64 flow_key = 0;
7300 unsigned long flags;
7301
7302 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7303 return -EINVAL;
7304
7305 if (class < CLASS_CODE_USER_PROG1 ||
7306 class > CLASS_CODE_SCTP_IPV6)
7307 return -EINVAL;
7308
7309 if (nfc->data & RXH_DISCARD) {
7310 niu_lock_parent(np, flags);
7311 flow_key = np->parent->tcam_key[class -
7312 CLASS_CODE_USER_PROG1];
7313 flow_key |= TCAM_KEY_DISC;
7314 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7315 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7316 niu_unlock_parent(np, flags);
7317 return 0;
7318 } else {
7319 /* Discard was set before, but is not set now */
7320 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7321 TCAM_KEY_DISC) {
7322 niu_lock_parent(np, flags);
7323 flow_key = np->parent->tcam_key[class -
7324 CLASS_CODE_USER_PROG1];
7325 flow_key &= ~TCAM_KEY_DISC;
7326 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7327 flow_key);
7328 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7329 flow_key;
7330 niu_unlock_parent(np, flags);
7331 }
7332 }
7333
7334 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7335 return -EINVAL;
7336
7337 niu_lock_parent(np, flags);
7338 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7339 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7340 niu_unlock_parent(np, flags);
7341
7342 return 0;
7343 }
7344
7345 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7346 struct niu_tcam_entry *tp,
7347 int l2_rdc_tab, u64 class)
7348 {
7349 u8 pid = 0;
7350 u32 sip, dip, sipm, dipm, spi, spim;
7351 u16 sport, dport, spm, dpm;
7352
7353 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7354 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7355 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7356 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7357
7358 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7359 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7360 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7361 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7362
7363 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7364 tp->key[3] |= dip;
7365
7366 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7367 tp->key_mask[3] |= dipm;
7368
7369 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7370 TCAM_V4KEY2_TOS_SHIFT);
7371 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7372 TCAM_V4KEY2_TOS_SHIFT);
7373 switch (fsp->flow_type) {
7374 case TCP_V4_FLOW:
7375 case UDP_V4_FLOW:
7376 case SCTP_V4_FLOW:
7377 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7378 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7379 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7380 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7381
7382 tp->key[2] |= (((u64)sport << 16) | dport);
7383 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7384 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7385 break;
7386 case AH_V4_FLOW:
7387 case ESP_V4_FLOW:
7388 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7389 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7390
7391 tp->key[2] |= spi;
7392 tp->key_mask[2] |= spim;
7393 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7394 break;
7395 case IP_USER_FLOW:
7396 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7397 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7398
7399 tp->key[2] |= spi;
7400 tp->key_mask[2] |= spim;
7401 pid = fsp->h_u.usr_ip4_spec.proto;
7402 break;
7403 default:
7404 break;
7405 }
7406
7407 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7408 if (pid) {
7409 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7410 }
7411 }
7412
7413 static int niu_add_ethtool_tcam_entry(struct niu *np,
7414 struct ethtool_rxnfc *nfc)
7415 {
7416 struct niu_parent *parent = np->parent;
7417 struct niu_tcam_entry *tp;
7418 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7419 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7420 int l2_rdc_table = rdc_table->first_table_num;
7421 u16 idx;
7422 u64 class;
7423 unsigned long flags;
7424 int err, ret;
7425
7426 ret = 0;
7427
7428 idx = nfc->fs.location;
7429 if (idx >= tcam_get_size(np))
7430 return -EINVAL;
7431
7432 if (fsp->flow_type == IP_USER_FLOW) {
7433 int i;
7434 int add_usr_cls = 0;
7435 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7436 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7437
7438 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7439 return -EINVAL;
7440
7441 niu_lock_parent(np, flags);
7442
7443 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7444 if (parent->l3_cls[i]) {
7445 if (uspec->proto == parent->l3_cls_pid[i]) {
7446 class = parent->l3_cls[i];
7447 parent->l3_cls_refcnt[i]++;
7448 add_usr_cls = 1;
7449 break;
7450 }
7451 } else {
7452 /* Program new user IP class */
7453 switch (i) {
7454 case 0:
7455 class = CLASS_CODE_USER_PROG1;
7456 break;
7457 case 1:
7458 class = CLASS_CODE_USER_PROG2;
7459 break;
7460 case 2:
7461 class = CLASS_CODE_USER_PROG3;
7462 break;
7463 case 3:
7464 class = CLASS_CODE_USER_PROG4;
7465 break;
7466 default:
7467 class = CLASS_CODE_UNRECOG;
7468 break;
7469 }
7470 ret = tcam_user_ip_class_set(np, class, 0,
7471 uspec->proto,
7472 uspec->tos,
7473 umask->tos);
7474 if (ret)
7475 goto out;
7476
7477 ret = tcam_user_ip_class_enable(np, class, 1);
7478 if (ret)
7479 goto out;
7480 parent->l3_cls[i] = class;
7481 parent->l3_cls_pid[i] = uspec->proto;
7482 parent->l3_cls_refcnt[i]++;
7483 add_usr_cls = 1;
7484 break;
7485 }
7486 }
7487 if (!add_usr_cls) {
7488 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7489 parent->index, __func__, uspec->proto);
7490 ret = -EINVAL;
7491 goto out;
7492 }
7493 niu_unlock_parent(np, flags);
7494 } else {
7495 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7496 return -EINVAL;
7497 }
7498 }
7499
7500 niu_lock_parent(np, flags);
7501
7502 idx = tcam_get_index(np, idx);
7503 tp = &parent->tcam[idx];
7504
7505 memset(tp, 0, sizeof(*tp));
7506
7507 /* fill in the tcam key and mask */
7508 switch (fsp->flow_type) {
7509 case TCP_V4_FLOW:
7510 case UDP_V4_FLOW:
7511 case SCTP_V4_FLOW:
7512 case AH_V4_FLOW:
7513 case ESP_V4_FLOW:
7514 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7515 break;
7516 case TCP_V6_FLOW:
7517 case UDP_V6_FLOW:
7518 case SCTP_V6_FLOW:
7519 case AH_V6_FLOW:
7520 case ESP_V6_FLOW:
7521 /* Not yet implemented */
7522 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7523 parent->index, __func__, fsp->flow_type);
7524 ret = -EINVAL;
7525 goto out;
7526 case IP_USER_FLOW:
7527 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7528 break;
7529 default:
7530 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7531 parent->index, __func__, fsp->flow_type);
7532 ret = -EINVAL;
7533 goto out;
7534 }
7535
7536 /* fill in the assoc data */
7537 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7538 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7539 } else {
7540 if (fsp->ring_cookie >= np->num_rx_rings) {
7541 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7542 parent->index, __func__,
7543 (long long)fsp->ring_cookie);
7544 ret = -EINVAL;
7545 goto out;
7546 }
7547 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7548 (fsp->ring_cookie <<
7549 TCAM_ASSOCDATA_OFFSET_SHIFT));
7550 }
7551
7552 err = tcam_write(np, idx, tp->key, tp->key_mask);
7553 if (err) {
7554 ret = -EINVAL;
7555 goto out;
7556 }
7557 err = tcam_assoc_write(np, idx, tp->assoc_data);
7558 if (err) {
7559 ret = -EINVAL;
7560 goto out;
7561 }
7562
7563 /* validate the entry */
7564 tp->valid = 1;
7565 np->clas.tcam_valid_entries++;
7566 out:
7567 niu_unlock_parent(np, flags);
7568
7569 return ret;
7570 }
7571
7572 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7573 {
7574 struct niu_parent *parent = np->parent;
7575 struct niu_tcam_entry *tp;
7576 u16 idx;
7577 unsigned long flags;
7578 u64 class;
7579 int ret = 0;
7580
7581 if (loc >= tcam_get_size(np))
7582 return -EINVAL;
7583
7584 niu_lock_parent(np, flags);
7585
7586 idx = tcam_get_index(np, loc);
7587 tp = &parent->tcam[idx];
7588
7589 /* if the entry is of a user defined class, then update*/
7590 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7591 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7592
7593 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7594 int i;
7595 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7596 if (parent->l3_cls[i] == class) {
7597 parent->l3_cls_refcnt[i]--;
7598 if (!parent->l3_cls_refcnt[i]) {
7599 /* disable class */
7600 ret = tcam_user_ip_class_enable(np,
7601 class,
7602 0);
7603 if (ret)
7604 goto out;
7605 parent->l3_cls[i] = 0;
7606 parent->l3_cls_pid[i] = 0;
7607 }
7608 break;
7609 }
7610 }
7611 if (i == NIU_L3_PROG_CLS) {
7612 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7613 parent->index, __func__,
7614 (unsigned long long)class);
7615 ret = -EINVAL;
7616 goto out;
7617 }
7618 }
7619
7620 ret = tcam_flush(np, idx);
7621 if (ret)
7622 goto out;
7623
7624 /* invalidate the entry */
7625 tp->valid = 0;
7626 np->clas.tcam_valid_entries--;
7627 out:
7628 niu_unlock_parent(np, flags);
7629
7630 return ret;
7631 }
7632
7633 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7634 {
7635 struct niu *np = netdev_priv(dev);
7636 int ret = 0;
7637
7638 switch (cmd->cmd) {
7639 case ETHTOOL_SRXFH:
7640 ret = niu_set_hash_opts(np, cmd);
7641 break;
7642 case ETHTOOL_SRXCLSRLINS:
7643 ret = niu_add_ethtool_tcam_entry(np, cmd);
7644 break;
7645 case ETHTOOL_SRXCLSRLDEL:
7646 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7647 break;
7648 default:
7649 ret = -EINVAL;
7650 break;
7651 }
7652
7653 return ret;
7654 }
7655
7656 static const struct {
7657 const char string[ETH_GSTRING_LEN];
7658 } niu_xmac_stat_keys[] = {
7659 { "tx_frames" },
7660 { "tx_bytes" },
7661 { "tx_fifo_errors" },
7662 { "tx_overflow_errors" },
7663 { "tx_max_pkt_size_errors" },
7664 { "tx_underflow_errors" },
7665 { "rx_local_faults" },
7666 { "rx_remote_faults" },
7667 { "rx_link_faults" },
7668 { "rx_align_errors" },
7669 { "rx_frags" },
7670 { "rx_mcasts" },
7671 { "rx_bcasts" },
7672 { "rx_hist_cnt1" },
7673 { "rx_hist_cnt2" },
7674 { "rx_hist_cnt3" },
7675 { "rx_hist_cnt4" },
7676 { "rx_hist_cnt5" },
7677 { "rx_hist_cnt6" },
7678 { "rx_hist_cnt7" },
7679 { "rx_octets" },
7680 { "rx_code_violations" },
7681 { "rx_len_errors" },
7682 { "rx_crc_errors" },
7683 { "rx_underflows" },
7684 { "rx_overflows" },
7685 { "pause_off_state" },
7686 { "pause_on_state" },
7687 { "pause_received" },
7688 };
7689
7690 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7691
7692 static const struct {
7693 const char string[ETH_GSTRING_LEN];
7694 } niu_bmac_stat_keys[] = {
7695 { "tx_underflow_errors" },
7696 { "tx_max_pkt_size_errors" },
7697 { "tx_bytes" },
7698 { "tx_frames" },
7699 { "rx_overflows" },
7700 { "rx_frames" },
7701 { "rx_align_errors" },
7702 { "rx_crc_errors" },
7703 { "rx_len_errors" },
7704 { "pause_off_state" },
7705 { "pause_on_state" },
7706 { "pause_received" },
7707 };
7708
7709 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7710
7711 static const struct {
7712 const char string[ETH_GSTRING_LEN];
7713 } niu_rxchan_stat_keys[] = {
7714 { "rx_channel" },
7715 { "rx_packets" },
7716 { "rx_bytes" },
7717 { "rx_dropped" },
7718 { "rx_errors" },
7719 };
7720
7721 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7722
7723 static const struct {
7724 const char string[ETH_GSTRING_LEN];
7725 } niu_txchan_stat_keys[] = {
7726 { "tx_channel" },
7727 { "tx_packets" },
7728 { "tx_bytes" },
7729 { "tx_errors" },
7730 };
7731
7732 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7733
7734 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7735 {
7736 struct niu *np = netdev_priv(dev);
7737 int i;
7738
7739 if (stringset != ETH_SS_STATS)
7740 return;
7741
7742 if (np->flags & NIU_FLAGS_XMAC) {
7743 memcpy(data, niu_xmac_stat_keys,
7744 sizeof(niu_xmac_stat_keys));
7745 data += sizeof(niu_xmac_stat_keys);
7746 } else {
7747 memcpy(data, niu_bmac_stat_keys,
7748 sizeof(niu_bmac_stat_keys));
7749 data += sizeof(niu_bmac_stat_keys);
7750 }
7751 for (i = 0; i < np->num_rx_rings; i++) {
7752 memcpy(data, niu_rxchan_stat_keys,
7753 sizeof(niu_rxchan_stat_keys));
7754 data += sizeof(niu_rxchan_stat_keys);
7755 }
7756 for (i = 0; i < np->num_tx_rings; i++) {
7757 memcpy(data, niu_txchan_stat_keys,
7758 sizeof(niu_txchan_stat_keys));
7759 data += sizeof(niu_txchan_stat_keys);
7760 }
7761 }
7762
7763 static int niu_get_sset_count(struct net_device *dev, int stringset)
7764 {
7765 struct niu *np = netdev_priv(dev);
7766
7767 if (stringset != ETH_SS_STATS)
7768 return -EINVAL;
7769
7770 return (np->flags & NIU_FLAGS_XMAC ?
7771 NUM_XMAC_STAT_KEYS :
7772 NUM_BMAC_STAT_KEYS) +
7773 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7774 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7775 }
7776
7777 static void niu_get_ethtool_stats(struct net_device *dev,
7778 struct ethtool_stats *stats, u64 *data)
7779 {
7780 struct niu *np = netdev_priv(dev);
7781 int i;
7782
7783 niu_sync_mac_stats(np);
7784 if (np->flags & NIU_FLAGS_XMAC) {
7785 memcpy(data, &np->mac_stats.xmac,
7786 sizeof(struct niu_xmac_stats));
7787 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7788 } else {
7789 memcpy(data, &np->mac_stats.bmac,
7790 sizeof(struct niu_bmac_stats));
7791 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7792 }
7793 for (i = 0; i < np->num_rx_rings; i++) {
7794 struct rx_ring_info *rp = &np->rx_rings[i];
7795
7796 niu_sync_rx_discard_stats(np, rp, 0);
7797
7798 data[0] = rp->rx_channel;
7799 data[1] = rp->rx_packets;
7800 data[2] = rp->rx_bytes;
7801 data[3] = rp->rx_dropped;
7802 data[4] = rp->rx_errors;
7803 data += 5;
7804 }
7805 for (i = 0; i < np->num_tx_rings; i++) {
7806 struct tx_ring_info *rp = &np->tx_rings[i];
7807
7808 data[0] = rp->tx_channel;
7809 data[1] = rp->tx_packets;
7810 data[2] = rp->tx_bytes;
7811 data[3] = rp->tx_errors;
7812 data += 4;
7813 }
7814 }
7815
7816 static u64 niu_led_state_save(struct niu *np)
7817 {
7818 if (np->flags & NIU_FLAGS_XMAC)
7819 return nr64_mac(XMAC_CONFIG);
7820 else
7821 return nr64_mac(BMAC_XIF_CONFIG);
7822 }
7823
7824 static void niu_led_state_restore(struct niu *np, u64 val)
7825 {
7826 if (np->flags & NIU_FLAGS_XMAC)
7827 nw64_mac(XMAC_CONFIG, val);
7828 else
7829 nw64_mac(BMAC_XIF_CONFIG, val);
7830 }
7831
7832 static void niu_force_led(struct niu *np, int on)
7833 {
7834 u64 val, reg, bit;
7835
7836 if (np->flags & NIU_FLAGS_XMAC) {
7837 reg = XMAC_CONFIG;
7838 bit = XMAC_CONFIG_FORCE_LED_ON;
7839 } else {
7840 reg = BMAC_XIF_CONFIG;
7841 bit = BMAC_XIF_CONFIG_LINK_LED;
7842 }
7843
7844 val = nr64_mac(reg);
7845 if (on)
7846 val |= bit;
7847 else
7848 val &= ~bit;
7849 nw64_mac(reg, val);
7850 }
7851
7852 static int niu_set_phys_id(struct net_device *dev,
7853 enum ethtool_phys_id_state state)
7854
7855 {
7856 struct niu *np = netdev_priv(dev);
7857
7858 if (!netif_running(dev))
7859 return -EAGAIN;
7860
7861 switch (state) {
7862 case ETHTOOL_ID_ACTIVE:
7863 np->orig_led_state = niu_led_state_save(np);
7864 return 1; /* cycle on/off once per second */
7865
7866 case ETHTOOL_ID_ON:
7867 niu_force_led(np, 1);
7868 break;
7869
7870 case ETHTOOL_ID_OFF:
7871 niu_force_led(np, 0);
7872 break;
7873
7874 case ETHTOOL_ID_INACTIVE:
7875 niu_led_state_restore(np, np->orig_led_state);
7876 }
7877
7878 return 0;
7879 }
7880
7881 static const struct ethtool_ops niu_ethtool_ops = {
7882 .get_drvinfo = niu_get_drvinfo,
7883 .get_link = ethtool_op_get_link,
7884 .get_msglevel = niu_get_msglevel,
7885 .set_msglevel = niu_set_msglevel,
7886 .nway_reset = niu_nway_reset,
7887 .get_eeprom_len = niu_get_eeprom_len,
7888 .get_eeprom = niu_get_eeprom,
7889 .get_strings = niu_get_strings,
7890 .get_sset_count = niu_get_sset_count,
7891 .get_ethtool_stats = niu_get_ethtool_stats,
7892 .set_phys_id = niu_set_phys_id,
7893 .get_rxnfc = niu_get_nfc,
7894 .set_rxnfc = niu_set_nfc,
7895 .get_link_ksettings = niu_get_link_ksettings,
7896 .set_link_ksettings = niu_set_link_ksettings,
7897 };
7898
7899 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7900 int ldg, int ldn)
7901 {
7902 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7903 return -EINVAL;
7904 if (ldn < 0 || ldn > LDN_MAX)
7905 return -EINVAL;
7906
7907 parent->ldg_map[ldn] = ldg;
7908
7909 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7910 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7911 * the firmware, and we're not supposed to change them.
7912 * Validate the mapping, because if it's wrong we probably
7913 * won't get any interrupts and that's painful to debug.
7914 */
7915 if (nr64(LDG_NUM(ldn)) != ldg) {
7916 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7917 np->port, ldn, ldg,
7918 (unsigned long long) nr64(LDG_NUM(ldn)));
7919 return -EINVAL;
7920 }
7921 } else
7922 nw64(LDG_NUM(ldn), ldg);
7923
7924 return 0;
7925 }
7926
7927 static int niu_set_ldg_timer_res(struct niu *np, int res)
7928 {
7929 if (res < 0 || res > LDG_TIMER_RES_VAL)
7930 return -EINVAL;
7931
7932
7933 nw64(LDG_TIMER_RES, res);
7934
7935 return 0;
7936 }
7937
7938 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7939 {
7940 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7941 (func < 0 || func > 3) ||
7942 (vector < 0 || vector > 0x1f))
7943 return -EINVAL;
7944
7945 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7946
7947 return 0;
7948 }
7949
7950 static int niu_pci_eeprom_read(struct niu *np, u32 addr)
7951 {
7952 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7953 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7954 int limit;
7955
7956 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7957 return -EINVAL;
7958
7959 frame = frame_base;
7960 nw64(ESPC_PIO_STAT, frame);
7961 limit = 64;
7962 do {
7963 udelay(5);
7964 frame = nr64(ESPC_PIO_STAT);
7965 if (frame & ESPC_PIO_STAT_READ_END)
7966 break;
7967 } while (limit--);
7968 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7969 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7970 (unsigned long long) frame);
7971 return -ENODEV;
7972 }
7973
7974 frame = frame_base;
7975 nw64(ESPC_PIO_STAT, frame);
7976 limit = 64;
7977 do {
7978 udelay(5);
7979 frame = nr64(ESPC_PIO_STAT);
7980 if (frame & ESPC_PIO_STAT_READ_END)
7981 break;
7982 } while (limit--);
7983 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7984 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7985 (unsigned long long) frame);
7986 return -ENODEV;
7987 }
7988
7989 frame = nr64(ESPC_PIO_STAT);
7990 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7991 }
7992
7993 static int niu_pci_eeprom_read16(struct niu *np, u32 off)
7994 {
7995 int err = niu_pci_eeprom_read(np, off);
7996 u16 val;
7997
7998 if (err < 0)
7999 return err;
8000 val = (err << 8);
8001 err = niu_pci_eeprom_read(np, off + 1);
8002 if (err < 0)
8003 return err;
8004 val |= (err & 0xff);
8005
8006 return val;
8007 }
8008
8009 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8010 {
8011 int err = niu_pci_eeprom_read(np, off);
8012 u16 val;
8013
8014 if (err < 0)
8015 return err;
8016
8017 val = (err & 0xff);
8018 err = niu_pci_eeprom_read(np, off + 1);
8019 if (err < 0)
8020 return err;
8021
8022 val |= (err & 0xff) << 8;
8023
8024 return val;
8025 }
8026
8027 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf,
8028 int namebuf_len)
8029 {
8030 int i;
8031
8032 for (i = 0; i < namebuf_len; i++) {
8033 int err = niu_pci_eeprom_read(np, off + i);
8034 if (err < 0)
8035 return err;
8036 *namebuf++ = err;
8037 if (!err)
8038 break;
8039 }
8040 if (i >= namebuf_len)
8041 return -EINVAL;
8042
8043 return i + 1;
8044 }
8045
8046 static void niu_vpd_parse_version(struct niu *np)
8047 {
8048 struct niu_vpd *vpd = &np->vpd;
8049 int len = strlen(vpd->version) + 1;
8050 const char *s = vpd->version;
8051 int i;
8052
8053 for (i = 0; i < len - 5; i++) {
8054 if (!strncmp(s + i, "FCode ", 6))
8055 break;
8056 }
8057 if (i >= len - 5)
8058 return;
8059
8060 s += i + 5;
8061 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8062
8063 netif_printk(np, probe, KERN_DEBUG, np->dev,
8064 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8065 vpd->fcode_major, vpd->fcode_minor);
8066 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8067 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8068 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8069 np->flags |= NIU_FLAGS_VPD_VALID;
8070 }
8071
8072 /* ESPC_PIO_EN_ENABLE must be set */
8073 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)
8074 {
8075 unsigned int found_mask = 0;
8076 #define FOUND_MASK_MODEL 0x00000001
8077 #define FOUND_MASK_BMODEL 0x00000002
8078 #define FOUND_MASK_VERS 0x00000004
8079 #define FOUND_MASK_MAC 0x00000008
8080 #define FOUND_MASK_NMAC 0x00000010
8081 #define FOUND_MASK_PHY 0x00000020
8082 #define FOUND_MASK_ALL 0x0000003f
8083
8084 netif_printk(np, probe, KERN_DEBUG, np->dev,
8085 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8086 while (start < end) {
8087 int len, err, prop_len;
8088 char namebuf[64];
8089 u8 *prop_buf;
8090 int max_len;
8091
8092 if (found_mask == FOUND_MASK_ALL) {
8093 niu_vpd_parse_version(np);
8094 return 1;
8095 }
8096
8097 err = niu_pci_eeprom_read(np, start + 2);
8098 if (err < 0)
8099 return err;
8100 len = err;
8101 start += 3;
8102
8103 prop_len = niu_pci_eeprom_read(np, start + 4);
8104 if (prop_len < 0)
8105 return prop_len;
8106 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8107 if (err < 0)
8108 return err;
8109
8110 prop_buf = NULL;
8111 max_len = 0;
8112 if (!strcmp(namebuf, "model")) {
8113 prop_buf = np->vpd.model;
8114 max_len = NIU_VPD_MODEL_MAX;
8115 found_mask |= FOUND_MASK_MODEL;
8116 } else if (!strcmp(namebuf, "board-model")) {
8117 prop_buf = np->vpd.board_model;
8118 max_len = NIU_VPD_BD_MODEL_MAX;
8119 found_mask |= FOUND_MASK_BMODEL;
8120 } else if (!strcmp(namebuf, "version")) {
8121 prop_buf = np->vpd.version;
8122 max_len = NIU_VPD_VERSION_MAX;
8123 found_mask |= FOUND_MASK_VERS;
8124 } else if (!strcmp(namebuf, "local-mac-address")) {
8125 prop_buf = np->vpd.local_mac;
8126 max_len = ETH_ALEN;
8127 found_mask |= FOUND_MASK_MAC;
8128 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8129 prop_buf = &np->vpd.mac_num;
8130 max_len = 1;
8131 found_mask |= FOUND_MASK_NMAC;
8132 } else if (!strcmp(namebuf, "phy-type")) {
8133 prop_buf = np->vpd.phy_type;
8134 max_len = NIU_VPD_PHY_TYPE_MAX;
8135 found_mask |= FOUND_MASK_PHY;
8136 }
8137
8138 if (max_len && prop_len > max_len) {
8139 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8140 return -EINVAL;
8141 }
8142
8143 if (prop_buf) {
8144 u32 off = start + 5 + err;
8145 int i;
8146
8147 netif_printk(np, probe, KERN_DEBUG, np->dev,
8148 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8149 namebuf, prop_len);
8150 for (i = 0; i < prop_len; i++) {
8151 err = niu_pci_eeprom_read(np, off + i);
8152 if (err >= 0)
8153 *prop_buf = err;
8154 ++prop_buf;
8155 }
8156 }
8157
8158 start += len;
8159 }
8160
8161 return 0;
8162 }
8163
8164 /* ESPC_PIO_EN_ENABLE must be set */
8165 static void niu_pci_vpd_fetch(struct niu *np, u32 start)
8166 {
8167 u32 offset;
8168 int err;
8169
8170 err = niu_pci_eeprom_read16_swp(np, start + 1);
8171 if (err < 0)
8172 return;
8173
8174 offset = err + 3;
8175
8176 while (start + offset < ESPC_EEPROM_SIZE) {
8177 u32 here = start + offset;
8178 u32 end;
8179
8180 err = niu_pci_eeprom_read(np, here);
8181 if (err != 0x90)
8182 return;
8183
8184 err = niu_pci_eeprom_read16_swp(np, here + 1);
8185 if (err < 0)
8186 return;
8187
8188 here = start + offset + 3;
8189 end = start + offset + err;
8190
8191 offset += err;
8192
8193 err = niu_pci_vpd_scan_props(np, here, end);
8194 if (err < 0 || err == 1)
8195 return;
8196 }
8197 }
8198
8199 /* ESPC_PIO_EN_ENABLE must be set */
8200 static u32 niu_pci_vpd_offset(struct niu *np)
8201 {
8202 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8203 int err;
8204
8205 while (start < end) {
8206 ret = start;
8207
8208 /* ROM header signature? */
8209 err = niu_pci_eeprom_read16(np, start + 0);
8210 if (err != 0x55aa)
8211 return 0;
8212
8213 /* Apply offset to PCI data structure. */
8214 err = niu_pci_eeprom_read16(np, start + 23);
8215 if (err < 0)
8216 return 0;
8217 start += err;
8218
8219 /* Check for "PCIR" signature. */
8220 err = niu_pci_eeprom_read16(np, start + 0);
8221 if (err != 0x5043)
8222 return 0;
8223 err = niu_pci_eeprom_read16(np, start + 2);
8224 if (err != 0x4952)
8225 return 0;
8226
8227 /* Check for OBP image type. */
8228 err = niu_pci_eeprom_read(np, start + 20);
8229 if (err < 0)
8230 return 0;
8231 if (err != 0x01) {
8232 err = niu_pci_eeprom_read(np, ret + 2);
8233 if (err < 0)
8234 return 0;
8235
8236 start = ret + (err * 512);
8237 continue;
8238 }
8239
8240 err = niu_pci_eeprom_read16_swp(np, start + 8);
8241 if (err < 0)
8242 return err;
8243 ret += err;
8244
8245 err = niu_pci_eeprom_read(np, ret + 0);
8246 if (err != 0x82)
8247 return 0;
8248
8249 return ret;
8250 }
8251
8252 return 0;
8253 }
8254
8255 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop)
8256 {
8257 if (!strcmp(phy_prop, "mif")) {
8258 /* 1G copper, MII */
8259 np->flags &= ~(NIU_FLAGS_FIBER |
8260 NIU_FLAGS_10G);
8261 np->mac_xcvr = MAC_XCVR_MII;
8262 } else if (!strcmp(phy_prop, "xgf")) {
8263 /* 10G fiber, XPCS */
8264 np->flags |= (NIU_FLAGS_10G |
8265 NIU_FLAGS_FIBER);
8266 np->mac_xcvr = MAC_XCVR_XPCS;
8267 } else if (!strcmp(phy_prop, "pcs")) {
8268 /* 1G fiber, PCS */
8269 np->flags &= ~NIU_FLAGS_10G;
8270 np->flags |= NIU_FLAGS_FIBER;
8271 np->mac_xcvr = MAC_XCVR_PCS;
8272 } else if (!strcmp(phy_prop, "xgc")) {
8273 /* 10G copper, XPCS */
8274 np->flags |= NIU_FLAGS_10G;
8275 np->flags &= ~NIU_FLAGS_FIBER;
8276 np->mac_xcvr = MAC_XCVR_XPCS;
8277 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8278 /* 10G Serdes or 1G Serdes, default to 10G */
8279 np->flags |= NIU_FLAGS_10G;
8280 np->flags &= ~NIU_FLAGS_FIBER;
8281 np->flags |= NIU_FLAGS_XCVR_SERDES;
8282 np->mac_xcvr = MAC_XCVR_XPCS;
8283 } else {
8284 return -EINVAL;
8285 }
8286 return 0;
8287 }
8288
8289 static int niu_pci_vpd_get_nports(struct niu *np)
8290 {
8291 int ports = 0;
8292
8293 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8294 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8295 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8296 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8297 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8298 ports = 4;
8299 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8300 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8301 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8302 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8303 ports = 2;
8304 }
8305
8306 return ports;
8307 }
8308
8309 static void niu_pci_vpd_validate(struct niu *np)
8310 {
8311 struct net_device *dev = np->dev;
8312 struct niu_vpd *vpd = &np->vpd;
8313 u8 val8;
8314
8315 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8316 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8317
8318 np->flags &= ~NIU_FLAGS_VPD_VALID;
8319 return;
8320 }
8321
8322 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8323 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8324 np->flags |= NIU_FLAGS_10G;
8325 np->flags &= ~NIU_FLAGS_FIBER;
8326 np->flags |= NIU_FLAGS_XCVR_SERDES;
8327 np->mac_xcvr = MAC_XCVR_PCS;
8328 if (np->port > 1) {
8329 np->flags |= NIU_FLAGS_FIBER;
8330 np->flags &= ~NIU_FLAGS_10G;
8331 }
8332 if (np->flags & NIU_FLAGS_10G)
8333 np->mac_xcvr = MAC_XCVR_XPCS;
8334 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8335 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8336 NIU_FLAGS_HOTPLUG_PHY);
8337 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8338 dev_err(np->device, "Illegal phy string [%s]\n",
8339 np->vpd.phy_type);
8340 dev_err(np->device, "Falling back to SPROM\n");
8341 np->flags &= ~NIU_FLAGS_VPD_VALID;
8342 return;
8343 }
8344
8345 memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN);
8346
8347 val8 = dev->dev_addr[5];
8348 dev->dev_addr[5] += np->port;
8349 if (dev->dev_addr[5] < val8)
8350 dev->dev_addr[4]++;
8351 }
8352
8353 static int niu_pci_probe_sprom(struct niu *np)
8354 {
8355 struct net_device *dev = np->dev;
8356 int len, i;
8357 u64 val, sum;
8358 u8 val8;
8359
8360 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8361 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8362 len = val / 4;
8363
8364 np->eeprom_len = len;
8365
8366 netif_printk(np, probe, KERN_DEBUG, np->dev,
8367 "SPROM: Image size %llu\n", (unsigned long long)val);
8368
8369 sum = 0;
8370 for (i = 0; i < len; i++) {
8371 val = nr64(ESPC_NCR(i));
8372 sum += (val >> 0) & 0xff;
8373 sum += (val >> 8) & 0xff;
8374 sum += (val >> 16) & 0xff;
8375 sum += (val >> 24) & 0xff;
8376 }
8377 netif_printk(np, probe, KERN_DEBUG, np->dev,
8378 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8379 if ((sum & 0xff) != 0xab) {
8380 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8381 return -EINVAL;
8382 }
8383
8384 val = nr64(ESPC_PHY_TYPE);
8385 switch (np->port) {
8386 case 0:
8387 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8388 ESPC_PHY_TYPE_PORT0_SHIFT;
8389 break;
8390 case 1:
8391 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8392 ESPC_PHY_TYPE_PORT1_SHIFT;
8393 break;
8394 case 2:
8395 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8396 ESPC_PHY_TYPE_PORT2_SHIFT;
8397 break;
8398 case 3:
8399 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8400 ESPC_PHY_TYPE_PORT3_SHIFT;
8401 break;
8402 default:
8403 dev_err(np->device, "Bogus port number %u\n",
8404 np->port);
8405 return -EINVAL;
8406 }
8407 netif_printk(np, probe, KERN_DEBUG, np->dev,
8408 "SPROM: PHY type %x\n", val8);
8409
8410 switch (val8) {
8411 case ESPC_PHY_TYPE_1G_COPPER:
8412 /* 1G copper, MII */
8413 np->flags &= ~(NIU_FLAGS_FIBER |
8414 NIU_FLAGS_10G);
8415 np->mac_xcvr = MAC_XCVR_MII;
8416 break;
8417
8418 case ESPC_PHY_TYPE_1G_FIBER:
8419 /* 1G fiber, PCS */
8420 np->flags &= ~NIU_FLAGS_10G;
8421 np->flags |= NIU_FLAGS_FIBER;
8422 np->mac_xcvr = MAC_XCVR_PCS;
8423 break;
8424
8425 case ESPC_PHY_TYPE_10G_COPPER:
8426 /* 10G copper, XPCS */
8427 np->flags |= NIU_FLAGS_10G;
8428 np->flags &= ~NIU_FLAGS_FIBER;
8429 np->mac_xcvr = MAC_XCVR_XPCS;
8430 break;
8431
8432 case ESPC_PHY_TYPE_10G_FIBER:
8433 /* 10G fiber, XPCS */
8434 np->flags |= (NIU_FLAGS_10G |
8435 NIU_FLAGS_FIBER);
8436 np->mac_xcvr = MAC_XCVR_XPCS;
8437 break;
8438
8439 default:
8440 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8441 return -EINVAL;
8442 }
8443
8444 val = nr64(ESPC_MAC_ADDR0);
8445 netif_printk(np, probe, KERN_DEBUG, np->dev,
8446 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8447 dev->dev_addr[0] = (val >> 0) & 0xff;
8448 dev->dev_addr[1] = (val >> 8) & 0xff;
8449 dev->dev_addr[2] = (val >> 16) & 0xff;
8450 dev->dev_addr[3] = (val >> 24) & 0xff;
8451
8452 val = nr64(ESPC_MAC_ADDR1);
8453 netif_printk(np, probe, KERN_DEBUG, np->dev,
8454 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8455 dev->dev_addr[4] = (val >> 0) & 0xff;
8456 dev->dev_addr[5] = (val >> 8) & 0xff;
8457
8458 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8459 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8460 dev->dev_addr);
8461 return -EINVAL;
8462 }
8463
8464 val8 = dev->dev_addr[5];
8465 dev->dev_addr[5] += np->port;
8466 if (dev->dev_addr[5] < val8)
8467 dev->dev_addr[4]++;
8468
8469 val = nr64(ESPC_MOD_STR_LEN);
8470 netif_printk(np, probe, KERN_DEBUG, np->dev,
8471 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8472 if (val >= 8 * 4)
8473 return -EINVAL;
8474
8475 for (i = 0; i < val; i += 4) {
8476 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8477
8478 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8479 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8480 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8481 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8482 }
8483 np->vpd.model[val] = '\0';
8484
8485 val = nr64(ESPC_BD_MOD_STR_LEN);
8486 netif_printk(np, probe, KERN_DEBUG, np->dev,
8487 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8488 if (val >= 4 * 4)
8489 return -EINVAL;
8490
8491 for (i = 0; i < val; i += 4) {
8492 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8493
8494 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8495 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8496 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8497 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8498 }
8499 np->vpd.board_model[val] = '\0';
8500
8501 np->vpd.mac_num =
8502 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8503 netif_printk(np, probe, KERN_DEBUG, np->dev,
8504 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8505
8506 return 0;
8507 }
8508
8509 static int niu_get_and_validate_port(struct niu *np)
8510 {
8511 struct niu_parent *parent = np->parent;
8512
8513 if (np->port <= 1)
8514 np->flags |= NIU_FLAGS_XMAC;
8515
8516 if (!parent->num_ports) {
8517 if (parent->plat_type == PLAT_TYPE_NIU) {
8518 parent->num_ports = 2;
8519 } else {
8520 parent->num_ports = niu_pci_vpd_get_nports(np);
8521 if (!parent->num_ports) {
8522 /* Fall back to SPROM as last resort.
8523 * This will fail on most cards.
8524 */
8525 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8526 ESPC_NUM_PORTS_MACS_VAL;
8527
8528 /* All of the current probing methods fail on
8529 * Maramba on-board parts.
8530 */
8531 if (!parent->num_ports)
8532 parent->num_ports = 4;
8533 }
8534 }
8535 }
8536
8537 if (np->port >= parent->num_ports)
8538 return -ENODEV;
8539
8540 return 0;
8541 }
8542
8543 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p,
8544 int dev_id_1, int dev_id_2, u8 phy_port, int type)
8545 {
8546 u32 id = (dev_id_1 << 16) | dev_id_2;
8547 u8 idx;
8548
8549 if (dev_id_1 < 0 || dev_id_2 < 0)
8550 return 0;
8551 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8552 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8553 * test covers the 8706 as well.
8554 */
8555 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8556 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8557 return 0;
8558 } else {
8559 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8560 return 0;
8561 }
8562
8563 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8564 parent->index, id,
8565 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8566 type == PHY_TYPE_PCS ? "PCS" : "MII",
8567 phy_port);
8568
8569 if (p->cur[type] >= NIU_MAX_PORTS) {
8570 pr_err("Too many PHY ports\n");
8571 return -EINVAL;
8572 }
8573 idx = p->cur[type];
8574 p->phy_id[type][idx] = id;
8575 p->phy_port[type][idx] = phy_port;
8576 p->cur[type] = idx + 1;
8577 return 0;
8578 }
8579
8580 static int port_has_10g(struct phy_probe_info *p, int port)
8581 {
8582 int i;
8583
8584 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8585 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8586 return 1;
8587 }
8588 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8589 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8590 return 1;
8591 }
8592
8593 return 0;
8594 }
8595
8596 static int count_10g_ports(struct phy_probe_info *p, int *lowest)
8597 {
8598 int port, cnt;
8599
8600 cnt = 0;
8601 *lowest = 32;
8602 for (port = 8; port < 32; port++) {
8603 if (port_has_10g(p, port)) {
8604 if (!cnt)
8605 *lowest = port;
8606 cnt++;
8607 }
8608 }
8609
8610 return cnt;
8611 }
8612
8613 static int count_1g_ports(struct phy_probe_info *p, int *lowest)
8614 {
8615 *lowest = 32;
8616 if (p->cur[PHY_TYPE_MII])
8617 *lowest = p->phy_port[PHY_TYPE_MII][0];
8618
8619 return p->cur[PHY_TYPE_MII];
8620 }
8621
8622 static void niu_n2_divide_channels(struct niu_parent *parent)
8623 {
8624 int num_ports = parent->num_ports;
8625 int i;
8626
8627 for (i = 0; i < num_ports; i++) {
8628 parent->rxchan_per_port[i] = (16 / num_ports);
8629 parent->txchan_per_port[i] = (16 / num_ports);
8630
8631 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8632 parent->index, i,
8633 parent->rxchan_per_port[i],
8634 parent->txchan_per_port[i]);
8635 }
8636 }
8637
8638 static void niu_divide_channels(struct niu_parent *parent,
8639 int num_10g, int num_1g)
8640 {
8641 int num_ports = parent->num_ports;
8642 int rx_chans_per_10g, rx_chans_per_1g;
8643 int tx_chans_per_10g, tx_chans_per_1g;
8644 int i, tot_rx, tot_tx;
8645
8646 if (!num_10g || !num_1g) {
8647 rx_chans_per_10g = rx_chans_per_1g =
8648 (NIU_NUM_RXCHAN / num_ports);
8649 tx_chans_per_10g = tx_chans_per_1g =
8650 (NIU_NUM_TXCHAN / num_ports);
8651 } else {
8652 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8653 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8654 (rx_chans_per_1g * num_1g)) /
8655 num_10g;
8656
8657 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8658 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8659 (tx_chans_per_1g * num_1g)) /
8660 num_10g;
8661 }
8662
8663 tot_rx = tot_tx = 0;
8664 for (i = 0; i < num_ports; i++) {
8665 int type = phy_decode(parent->port_phy, i);
8666
8667 if (type == PORT_TYPE_10G) {
8668 parent->rxchan_per_port[i] = rx_chans_per_10g;
8669 parent->txchan_per_port[i] = tx_chans_per_10g;
8670 } else {
8671 parent->rxchan_per_port[i] = rx_chans_per_1g;
8672 parent->txchan_per_port[i] = tx_chans_per_1g;
8673 }
8674 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8675 parent->index, i,
8676 parent->rxchan_per_port[i],
8677 parent->txchan_per_port[i]);
8678 tot_rx += parent->rxchan_per_port[i];
8679 tot_tx += parent->txchan_per_port[i];
8680 }
8681
8682 if (tot_rx > NIU_NUM_RXCHAN) {
8683 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8684 parent->index, tot_rx);
8685 for (i = 0; i < num_ports; i++)
8686 parent->rxchan_per_port[i] = 1;
8687 }
8688 if (tot_tx > NIU_NUM_TXCHAN) {
8689 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8690 parent->index, tot_tx);
8691 for (i = 0; i < num_ports; i++)
8692 parent->txchan_per_port[i] = 1;
8693 }
8694 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8695 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8696 parent->index, tot_rx, tot_tx);
8697 }
8698 }
8699
8700 static void niu_divide_rdc_groups(struct niu_parent *parent,
8701 int num_10g, int num_1g)
8702 {
8703 int i, num_ports = parent->num_ports;
8704 int rdc_group, rdc_groups_per_port;
8705 int rdc_channel_base;
8706
8707 rdc_group = 0;
8708 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8709
8710 rdc_channel_base = 0;
8711
8712 for (i = 0; i < num_ports; i++) {
8713 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8714 int grp, num_channels = parent->rxchan_per_port[i];
8715 int this_channel_offset;
8716
8717 tp->first_table_num = rdc_group;
8718 tp->num_tables = rdc_groups_per_port;
8719 this_channel_offset = 0;
8720 for (grp = 0; grp < tp->num_tables; grp++) {
8721 struct rdc_table *rt = &tp->tables[grp];
8722 int slot;
8723
8724 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8725 parent->index, i, tp->first_table_num + grp);
8726 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8727 rt->rxdma_channel[slot] =
8728 rdc_channel_base + this_channel_offset;
8729
8730 pr_cont("%d ", rt->rxdma_channel[slot]);
8731
8732 if (++this_channel_offset == num_channels)
8733 this_channel_offset = 0;
8734 }
8735 pr_cont("]\n");
8736 }
8737
8738 parent->rdc_default[i] = rdc_channel_base;
8739
8740 rdc_channel_base += num_channels;
8741 rdc_group += rdc_groups_per_port;
8742 }
8743 }
8744
8745 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent,
8746 struct phy_probe_info *info)
8747 {
8748 unsigned long flags;
8749 int port, err;
8750
8751 memset(info, 0, sizeof(*info));
8752
8753 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8754 niu_lock_parent(np, flags);
8755 err = 0;
8756 for (port = 8; port < 32; port++) {
8757 int dev_id_1, dev_id_2;
8758
8759 dev_id_1 = mdio_read(np, port,
8760 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8761 dev_id_2 = mdio_read(np, port,
8762 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8763 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8764 PHY_TYPE_PMA_PMD);
8765 if (err)
8766 break;
8767 dev_id_1 = mdio_read(np, port,
8768 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8769 dev_id_2 = mdio_read(np, port,
8770 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8771 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8772 PHY_TYPE_PCS);
8773 if (err)
8774 break;
8775 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8776 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8777 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8778 PHY_TYPE_MII);
8779 if (err)
8780 break;
8781 }
8782 niu_unlock_parent(np, flags);
8783
8784 return err;
8785 }
8786
8787 static int walk_phys(struct niu *np, struct niu_parent *parent)
8788 {
8789 struct phy_probe_info *info = &parent->phy_probe_info;
8790 int lowest_10g, lowest_1g;
8791 int num_10g, num_1g;
8792 u32 val;
8793 int err;
8794
8795 num_10g = num_1g = 0;
8796
8797 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8798 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8799 num_10g = 0;
8800 num_1g = 2;
8801 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8802 parent->num_ports = 4;
8803 val = (phy_encode(PORT_TYPE_1G, 0) |
8804 phy_encode(PORT_TYPE_1G, 1) |
8805 phy_encode(PORT_TYPE_1G, 2) |
8806 phy_encode(PORT_TYPE_1G, 3));
8807 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8808 num_10g = 2;
8809 num_1g = 0;
8810 parent->num_ports = 2;
8811 val = (phy_encode(PORT_TYPE_10G, 0) |
8812 phy_encode(PORT_TYPE_10G, 1));
8813 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8814 (parent->plat_type == PLAT_TYPE_NIU)) {
8815 /* this is the Monza case */
8816 if (np->flags & NIU_FLAGS_10G) {
8817 val = (phy_encode(PORT_TYPE_10G, 0) |
8818 phy_encode(PORT_TYPE_10G, 1));
8819 } else {
8820 val = (phy_encode(PORT_TYPE_1G, 0) |
8821 phy_encode(PORT_TYPE_1G, 1));
8822 }
8823 } else {
8824 err = fill_phy_probe_info(np, parent, info);
8825 if (err)
8826 return err;
8827
8828 num_10g = count_10g_ports(info, &lowest_10g);
8829 num_1g = count_1g_ports(info, &lowest_1g);
8830
8831 switch ((num_10g << 4) | num_1g) {
8832 case 0x24:
8833 if (lowest_1g == 10)
8834 parent->plat_type = PLAT_TYPE_VF_P0;
8835 else if (lowest_1g == 26)
8836 parent->plat_type = PLAT_TYPE_VF_P1;
8837 else
8838 goto unknown_vg_1g_port;
8839
8840 /* fallthru */
8841 case 0x22:
8842 val = (phy_encode(PORT_TYPE_10G, 0) |
8843 phy_encode(PORT_TYPE_10G, 1) |
8844 phy_encode(PORT_TYPE_1G, 2) |
8845 phy_encode(PORT_TYPE_1G, 3));
8846 break;
8847
8848 case 0x20:
8849 val = (phy_encode(PORT_TYPE_10G, 0) |
8850 phy_encode(PORT_TYPE_10G, 1));
8851 break;
8852
8853 case 0x10:
8854 val = phy_encode(PORT_TYPE_10G, np->port);
8855 break;
8856
8857 case 0x14:
8858 if (lowest_1g == 10)
8859 parent->plat_type = PLAT_TYPE_VF_P0;
8860 else if (lowest_1g == 26)
8861 parent->plat_type = PLAT_TYPE_VF_P1;
8862 else
8863 goto unknown_vg_1g_port;
8864
8865 /* fallthru */
8866 case 0x13:
8867 if ((lowest_10g & 0x7) == 0)
8868 val = (phy_encode(PORT_TYPE_10G, 0) |
8869 phy_encode(PORT_TYPE_1G, 1) |
8870 phy_encode(PORT_TYPE_1G, 2) |
8871 phy_encode(PORT_TYPE_1G, 3));
8872 else
8873 val = (phy_encode(PORT_TYPE_1G, 0) |
8874 phy_encode(PORT_TYPE_10G, 1) |
8875 phy_encode(PORT_TYPE_1G, 2) |
8876 phy_encode(PORT_TYPE_1G, 3));
8877 break;
8878
8879 case 0x04:
8880 if (lowest_1g == 10)
8881 parent->plat_type = PLAT_TYPE_VF_P0;
8882 else if (lowest_1g == 26)
8883 parent->plat_type = PLAT_TYPE_VF_P1;
8884 else
8885 goto unknown_vg_1g_port;
8886
8887 val = (phy_encode(PORT_TYPE_1G, 0) |
8888 phy_encode(PORT_TYPE_1G, 1) |
8889 phy_encode(PORT_TYPE_1G, 2) |
8890 phy_encode(PORT_TYPE_1G, 3));
8891 break;
8892
8893 default:
8894 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8895 num_10g, num_1g);
8896 return -EINVAL;
8897 }
8898 }
8899
8900 parent->port_phy = val;
8901
8902 if (parent->plat_type == PLAT_TYPE_NIU)
8903 niu_n2_divide_channels(parent);
8904 else
8905 niu_divide_channels(parent, num_10g, num_1g);
8906
8907 niu_divide_rdc_groups(parent, num_10g, num_1g);
8908
8909 return 0;
8910
8911 unknown_vg_1g_port:
8912 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8913 return -EINVAL;
8914 }
8915
8916 static int niu_probe_ports(struct niu *np)
8917 {
8918 struct niu_parent *parent = np->parent;
8919 int err, i;
8920
8921 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8922 err = walk_phys(np, parent);
8923 if (err)
8924 return err;
8925
8926 niu_set_ldg_timer_res(np, 2);
8927 for (i = 0; i <= LDN_MAX; i++)
8928 niu_ldn_irq_enable(np, i, 0);
8929 }
8930
8931 if (parent->port_phy == PORT_PHY_INVALID)
8932 return -EINVAL;
8933
8934 return 0;
8935 }
8936
8937 static int niu_classifier_swstate_init(struct niu *np)
8938 {
8939 struct niu_classifier *cp = &np->clas;
8940
8941 cp->tcam_top = (u16) np->port;
8942 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8943 cp->h1_init = 0xffffffff;
8944 cp->h2_init = 0xffff;
8945
8946 return fflp_early_init(np);
8947 }
8948
8949 static void niu_link_config_init(struct niu *np)
8950 {
8951 struct niu_link_config *lp = &np->link_config;
8952
8953 lp->advertising = (ADVERTISED_10baseT_Half |
8954 ADVERTISED_10baseT_Full |
8955 ADVERTISED_100baseT_Half |
8956 ADVERTISED_100baseT_Full |
8957 ADVERTISED_1000baseT_Half |
8958 ADVERTISED_1000baseT_Full |
8959 ADVERTISED_10000baseT_Full |
8960 ADVERTISED_Autoneg);
8961 lp->speed = lp->active_speed = SPEED_INVALID;
8962 lp->duplex = DUPLEX_FULL;
8963 lp->active_duplex = DUPLEX_INVALID;
8964 lp->autoneg = 1;
8965 #if 0
8966 lp->loopback_mode = LOOPBACK_MAC;
8967 lp->active_speed = SPEED_10000;
8968 lp->active_duplex = DUPLEX_FULL;
8969 #else
8970 lp->loopback_mode = LOOPBACK_DISABLED;
8971 #endif
8972 }
8973
8974 static int niu_init_mac_ipp_pcs_base(struct niu *np)
8975 {
8976 switch (np->port) {
8977 case 0:
8978 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8979 np->ipp_off = 0x00000;
8980 np->pcs_off = 0x04000;
8981 np->xpcs_off = 0x02000;
8982 break;
8983
8984 case 1:
8985 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8986 np->ipp_off = 0x08000;
8987 np->pcs_off = 0x0a000;
8988 np->xpcs_off = 0x08000;
8989 break;
8990
8991 case 2:
8992 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8993 np->ipp_off = 0x04000;
8994 np->pcs_off = 0x0e000;
8995 np->xpcs_off = ~0UL;
8996 break;
8997
8998 case 3:
8999 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9000 np->ipp_off = 0x0c000;
9001 np->pcs_off = 0x12000;
9002 np->xpcs_off = ~0UL;
9003 break;
9004
9005 default:
9006 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9007 return -EINVAL;
9008 }
9009
9010 return 0;
9011 }
9012
9013 static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
9014 {
9015 struct msix_entry msi_vec[NIU_NUM_LDG];
9016 struct niu_parent *parent = np->parent;
9017 struct pci_dev *pdev = np->pdev;
9018 int i, num_irqs;
9019 u8 first_ldg;
9020
9021 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9022 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9023 ldg_num_map[i] = first_ldg + i;
9024
9025 num_irqs = (parent->rxchan_per_port[np->port] +
9026 parent->txchan_per_port[np->port] +
9027 (np->port == 0 ? 3 : 1));
9028 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9029
9030 for (i = 0; i < num_irqs; i++) {
9031 msi_vec[i].vector = 0;
9032 msi_vec[i].entry = i;
9033 }
9034
9035 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
9036 if (num_irqs < 0) {
9037 np->flags &= ~NIU_FLAGS_MSIX;
9038 return;
9039 }
9040
9041 np->flags |= NIU_FLAGS_MSIX;
9042 for (i = 0; i < num_irqs; i++)
9043 np->ldg[i].irq = msi_vec[i].vector;
9044 np->num_ldg = num_irqs;
9045 }
9046
9047 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9048 {
9049 #ifdef CONFIG_SPARC64
9050 struct platform_device *op = np->op;
9051 const u32 *int_prop;
9052 int i;
9053
9054 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9055 if (!int_prop)
9056 return -ENODEV;
9057
9058 for (i = 0; i < op->archdata.num_irqs; i++) {
9059 ldg_num_map[i] = int_prop[i];
9060 np->ldg[i].irq = op->archdata.irqs[i];
9061 }
9062
9063 np->num_ldg = op->archdata.num_irqs;
9064
9065 return 0;
9066 #else
9067 return -EINVAL;
9068 #endif
9069 }
9070
9071 static int niu_ldg_init(struct niu *np)
9072 {
9073 struct niu_parent *parent = np->parent;
9074 u8 ldg_num_map[NIU_NUM_LDG];
9075 int first_chan, num_chan;
9076 int i, err, ldg_rotor;
9077 u8 port;
9078
9079 np->num_ldg = 1;
9080 np->ldg[0].irq = np->dev->irq;
9081 if (parent->plat_type == PLAT_TYPE_NIU) {
9082 err = niu_n2_irq_init(np, ldg_num_map);
9083 if (err)
9084 return err;
9085 } else
9086 niu_try_msix(np, ldg_num_map);
9087
9088 port = np->port;
9089 for (i = 0; i < np->num_ldg; i++) {
9090 struct niu_ldg *lp = &np->ldg[i];
9091
9092 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9093
9094 lp->np = np;
9095 lp->ldg_num = ldg_num_map[i];
9096 lp->timer = 2; /* XXX */
9097
9098 /* On N2 NIU the firmware has setup the SID mappings so they go
9099 * to the correct values that will route the LDG to the proper
9100 * interrupt in the NCU interrupt table.
9101 */
9102 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9103 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9104 if (err)
9105 return err;
9106 }
9107 }
9108
9109 /* We adopt the LDG assignment ordering used by the N2 NIU
9110 * 'interrupt' properties because that simplifies a lot of
9111 * things. This ordering is:
9112 *
9113 * MAC
9114 * MIF (if port zero)
9115 * SYSERR (if port zero)
9116 * RX channels
9117 * TX channels
9118 */
9119
9120 ldg_rotor = 0;
9121
9122 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9123 LDN_MAC(port));
9124 if (err)
9125 return err;
9126
9127 ldg_rotor++;
9128 if (ldg_rotor == np->num_ldg)
9129 ldg_rotor = 0;
9130
9131 if (port == 0) {
9132 err = niu_ldg_assign_ldn(np, parent,
9133 ldg_num_map[ldg_rotor],
9134 LDN_MIF);
9135 if (err)
9136 return err;
9137
9138 ldg_rotor++;
9139 if (ldg_rotor == np->num_ldg)
9140 ldg_rotor = 0;
9141
9142 err = niu_ldg_assign_ldn(np, parent,
9143 ldg_num_map[ldg_rotor],
9144 LDN_DEVICE_ERROR);
9145 if (err)
9146 return err;
9147
9148 ldg_rotor++;
9149 if (ldg_rotor == np->num_ldg)
9150 ldg_rotor = 0;
9151
9152 }
9153
9154 first_chan = 0;
9155 for (i = 0; i < port; i++)
9156 first_chan += parent->rxchan_per_port[i];
9157 num_chan = parent->rxchan_per_port[port];
9158
9159 for (i = first_chan; i < (first_chan + num_chan); i++) {
9160 err = niu_ldg_assign_ldn(np, parent,
9161 ldg_num_map[ldg_rotor],
9162 LDN_RXDMA(i));
9163 if (err)
9164 return err;
9165 ldg_rotor++;
9166 if (ldg_rotor == np->num_ldg)
9167 ldg_rotor = 0;
9168 }
9169
9170 first_chan = 0;
9171 for (i = 0; i < port; i++)
9172 first_chan += parent->txchan_per_port[i];
9173 num_chan = parent->txchan_per_port[port];
9174 for (i = first_chan; i < (first_chan + num_chan); i++) {
9175 err = niu_ldg_assign_ldn(np, parent,
9176 ldg_num_map[ldg_rotor],
9177 LDN_TXDMA(i));
9178 if (err)
9179 return err;
9180 ldg_rotor++;
9181 if (ldg_rotor == np->num_ldg)
9182 ldg_rotor = 0;
9183 }
9184
9185 return 0;
9186 }
9187
9188 static void niu_ldg_free(struct niu *np)
9189 {
9190 if (np->flags & NIU_FLAGS_MSIX)
9191 pci_disable_msix(np->pdev);
9192 }
9193
9194 static int niu_get_of_props(struct niu *np)
9195 {
9196 #ifdef CONFIG_SPARC64
9197 struct net_device *dev = np->dev;
9198 struct device_node *dp;
9199 const char *phy_type;
9200 const u8 *mac_addr;
9201 const char *model;
9202 int prop_len;
9203
9204 if (np->parent->plat_type == PLAT_TYPE_NIU)
9205 dp = np->op->dev.of_node;
9206 else
9207 dp = pci_device_to_OF_node(np->pdev);
9208
9209 phy_type = of_get_property(dp, "phy-type", &prop_len);
9210 if (!phy_type) {
9211 netdev_err(dev, "%pOF: OF node lacks phy-type property\n", dp);
9212 return -EINVAL;
9213 }
9214
9215 if (!strcmp(phy_type, "none"))
9216 return -ENODEV;
9217
9218 strcpy(np->vpd.phy_type, phy_type);
9219
9220 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9221 netdev_err(dev, "%pOF: Illegal phy string [%s]\n",
9222 dp, np->vpd.phy_type);
9223 return -EINVAL;
9224 }
9225
9226 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9227 if (!mac_addr) {
9228 netdev_err(dev, "%pOF: OF node lacks local-mac-address property\n",
9229 dp);
9230 return -EINVAL;
9231 }
9232 if (prop_len != dev->addr_len) {
9233 netdev_err(dev, "%pOF: OF MAC address prop len (%d) is wrong\n",
9234 dp, prop_len);
9235 }
9236 memcpy(dev->dev_addr, mac_addr, dev->addr_len);
9237 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9238 netdev_err(dev, "%pOF: OF MAC address is invalid\n", dp);
9239 netdev_err(dev, "%pOF: [ %pM ]\n", dp, dev->dev_addr);
9240 return -EINVAL;
9241 }
9242
9243 model = of_get_property(dp, "model", &prop_len);
9244
9245 if (model)
9246 strcpy(np->vpd.model, model);
9247
9248 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9249 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9250 NIU_FLAGS_HOTPLUG_PHY);
9251 }
9252
9253 return 0;
9254 #else
9255 return -EINVAL;
9256 #endif
9257 }
9258
9259 static int niu_get_invariants(struct niu *np)
9260 {
9261 int err, have_props;
9262 u32 offset;
9263
9264 err = niu_get_of_props(np);
9265 if (err == -ENODEV)
9266 return err;
9267
9268 have_props = !err;
9269
9270 err = niu_init_mac_ipp_pcs_base(np);
9271 if (err)
9272 return err;
9273
9274 if (have_props) {
9275 err = niu_get_and_validate_port(np);
9276 if (err)
9277 return err;
9278
9279 } else {
9280 if (np->parent->plat_type == PLAT_TYPE_NIU)
9281 return -EINVAL;
9282
9283 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9284 offset = niu_pci_vpd_offset(np);
9285 netif_printk(np, probe, KERN_DEBUG, np->dev,
9286 "%s() VPD offset [%08x]\n", __func__, offset);
9287 if (offset)
9288 niu_pci_vpd_fetch(np, offset);
9289 nw64(ESPC_PIO_EN, 0);
9290
9291 if (np->flags & NIU_FLAGS_VPD_VALID) {
9292 niu_pci_vpd_validate(np);
9293 err = niu_get_and_validate_port(np);
9294 if (err)
9295 return err;
9296 }
9297
9298 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9299 err = niu_get_and_validate_port(np);
9300 if (err)
9301 return err;
9302 err = niu_pci_probe_sprom(np);
9303 if (err)
9304 return err;
9305 }
9306 }
9307
9308 err = niu_probe_ports(np);
9309 if (err)
9310 return err;
9311
9312 niu_ldg_init(np);
9313
9314 niu_classifier_swstate_init(np);
9315 niu_link_config_init(np);
9316
9317 err = niu_determine_phy_disposition(np);
9318 if (!err)
9319 err = niu_init_link(np);
9320
9321 return err;
9322 }
9323
9324 static LIST_HEAD(niu_parent_list);
9325 static DEFINE_MUTEX(niu_parent_lock);
9326 static int niu_parent_index;
9327
9328 static ssize_t show_port_phy(struct device *dev,
9329 struct device_attribute *attr, char *buf)
9330 {
9331 struct platform_device *plat_dev = to_platform_device(dev);
9332 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9333 u32 port_phy = p->port_phy;
9334 char *orig_buf = buf;
9335 int i;
9336
9337 if (port_phy == PORT_PHY_UNKNOWN ||
9338 port_phy == PORT_PHY_INVALID)
9339 return 0;
9340
9341 for (i = 0; i < p->num_ports; i++) {
9342 const char *type_str;
9343 int type;
9344
9345 type = phy_decode(port_phy, i);
9346 if (type == PORT_TYPE_10G)
9347 type_str = "10G";
9348 else
9349 type_str = "1G";
9350 buf += sprintf(buf,
9351 (i == 0) ? "%s" : " %s",
9352 type_str);
9353 }
9354 buf += sprintf(buf, "\n");
9355 return buf - orig_buf;
9356 }
9357
9358 static ssize_t show_plat_type(struct device *dev,
9359 struct device_attribute *attr, char *buf)
9360 {
9361 struct platform_device *plat_dev = to_platform_device(dev);
9362 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9363 const char *type_str;
9364
9365 switch (p->plat_type) {
9366 case PLAT_TYPE_ATLAS:
9367 type_str = "atlas";
9368 break;
9369 case PLAT_TYPE_NIU:
9370 type_str = "niu";
9371 break;
9372 case PLAT_TYPE_VF_P0:
9373 type_str = "vf_p0";
9374 break;
9375 case PLAT_TYPE_VF_P1:
9376 type_str = "vf_p1";
9377 break;
9378 default:
9379 type_str = "unknown";
9380 break;
9381 }
9382
9383 return sprintf(buf, "%s\n", type_str);
9384 }
9385
9386 static ssize_t __show_chan_per_port(struct device *dev,
9387 struct device_attribute *attr, char *buf,
9388 int rx)
9389 {
9390 struct platform_device *plat_dev = to_platform_device(dev);
9391 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9392 char *orig_buf = buf;
9393 u8 *arr;
9394 int i;
9395
9396 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9397
9398 for (i = 0; i < p->num_ports; i++) {
9399 buf += sprintf(buf,
9400 (i == 0) ? "%d" : " %d",
9401 arr[i]);
9402 }
9403 buf += sprintf(buf, "\n");
9404
9405 return buf - orig_buf;
9406 }
9407
9408 static ssize_t show_rxchan_per_port(struct device *dev,
9409 struct device_attribute *attr, char *buf)
9410 {
9411 return __show_chan_per_port(dev, attr, buf, 1);
9412 }
9413
9414 static ssize_t show_txchan_per_port(struct device *dev,
9415 struct device_attribute *attr, char *buf)
9416 {
9417 return __show_chan_per_port(dev, attr, buf, 1);
9418 }
9419
9420 static ssize_t show_num_ports(struct device *dev,
9421 struct device_attribute *attr, char *buf)
9422 {
9423 struct platform_device *plat_dev = to_platform_device(dev);
9424 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9425
9426 return sprintf(buf, "%d\n", p->num_ports);
9427 }
9428
9429 static struct device_attribute niu_parent_attributes[] = {
9430 __ATTR(port_phy, 0444, show_port_phy, NULL),
9431 __ATTR(plat_type, 0444, show_plat_type, NULL),
9432 __ATTR(rxchan_per_port, 0444, show_rxchan_per_port, NULL),
9433 __ATTR(txchan_per_port, 0444, show_txchan_per_port, NULL),
9434 __ATTR(num_ports, 0444, show_num_ports, NULL),
9435 {}
9436 };
9437
9438 static struct niu_parent *niu_new_parent(struct niu *np,
9439 union niu_parent_id *id, u8 ptype)
9440 {
9441 struct platform_device *plat_dev;
9442 struct niu_parent *p;
9443 int i;
9444
9445 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9446 NULL, 0);
9447 if (IS_ERR(plat_dev))
9448 return NULL;
9449
9450 for (i = 0; niu_parent_attributes[i].attr.name; i++) {
9451 int err = device_create_file(&plat_dev->dev,
9452 &niu_parent_attributes[i]);
9453 if (err)
9454 goto fail_unregister;
9455 }
9456
9457 p = kzalloc(sizeof(*p), GFP_KERNEL);
9458 if (!p)
9459 goto fail_unregister;
9460
9461 p->index = niu_parent_index++;
9462
9463 plat_dev->dev.platform_data = p;
9464 p->plat_dev = plat_dev;
9465
9466 memcpy(&p->id, id, sizeof(*id));
9467 p->plat_type = ptype;
9468 INIT_LIST_HEAD(&p->list);
9469 atomic_set(&p->refcnt, 0);
9470 list_add(&p->list, &niu_parent_list);
9471 spin_lock_init(&p->lock);
9472
9473 p->rxdma_clock_divider = 7500;
9474
9475 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9476 if (p->plat_type == PLAT_TYPE_NIU)
9477 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9478
9479 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9480 int index = i - CLASS_CODE_USER_PROG1;
9481
9482 p->tcam_key[index] = TCAM_KEY_TSEL;
9483 p->flow_key[index] = (FLOW_KEY_IPSA |
9484 FLOW_KEY_IPDA |
9485 FLOW_KEY_PROTO |
9486 (FLOW_KEY_L4_BYTE12 <<
9487 FLOW_KEY_L4_0_SHIFT) |
9488 (FLOW_KEY_L4_BYTE12 <<
9489 FLOW_KEY_L4_1_SHIFT));
9490 }
9491
9492 for (i = 0; i < LDN_MAX + 1; i++)
9493 p->ldg_map[i] = LDG_INVALID;
9494
9495 return p;
9496
9497 fail_unregister:
9498 platform_device_unregister(plat_dev);
9499 return NULL;
9500 }
9501
9502 static struct niu_parent *niu_get_parent(struct niu *np,
9503 union niu_parent_id *id, u8 ptype)
9504 {
9505 struct niu_parent *p, *tmp;
9506 int port = np->port;
9507
9508 mutex_lock(&niu_parent_lock);
9509 p = NULL;
9510 list_for_each_entry(tmp, &niu_parent_list, list) {
9511 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9512 p = tmp;
9513 break;
9514 }
9515 }
9516 if (!p)
9517 p = niu_new_parent(np, id, ptype);
9518
9519 if (p) {
9520 char port_name[8];
9521 int err;
9522
9523 sprintf(port_name, "port%d", port);
9524 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9525 &np->device->kobj,
9526 port_name);
9527 if (!err) {
9528 p->ports[port] = np;
9529 atomic_inc(&p->refcnt);
9530 }
9531 }
9532 mutex_unlock(&niu_parent_lock);
9533
9534 return p;
9535 }
9536
9537 static void niu_put_parent(struct niu *np)
9538 {
9539 struct niu_parent *p = np->parent;
9540 u8 port = np->port;
9541 char port_name[8];
9542
9543 BUG_ON(!p || p->ports[port] != np);
9544
9545 netif_printk(np, probe, KERN_DEBUG, np->dev,
9546 "%s() port[%u]\n", __func__, port);
9547
9548 sprintf(port_name, "port%d", port);
9549
9550 mutex_lock(&niu_parent_lock);
9551
9552 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9553
9554 p->ports[port] = NULL;
9555 np->parent = NULL;
9556
9557 if (atomic_dec_and_test(&p->refcnt)) {
9558 list_del(&p->list);
9559 platform_device_unregister(p->plat_dev);
9560 }
9561
9562 mutex_unlock(&niu_parent_lock);
9563 }
9564
9565 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9566 u64 *handle, gfp_t flag)
9567 {
9568 dma_addr_t dh;
9569 void *ret;
9570
9571 ret = dma_alloc_coherent(dev, size, &dh, flag);
9572 if (ret)
9573 *handle = dh;
9574 return ret;
9575 }
9576
9577 static void niu_pci_free_coherent(struct device *dev, size_t size,
9578 void *cpu_addr, u64 handle)
9579 {
9580 dma_free_coherent(dev, size, cpu_addr, handle);
9581 }
9582
9583 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9584 unsigned long offset, size_t size,
9585 enum dma_data_direction direction)
9586 {
9587 return dma_map_page(dev, page, offset, size, direction);
9588 }
9589
9590 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9591 size_t size, enum dma_data_direction direction)
9592 {
9593 dma_unmap_page(dev, dma_address, size, direction);
9594 }
9595
9596 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9597 size_t size,
9598 enum dma_data_direction direction)
9599 {
9600 return dma_map_single(dev, cpu_addr, size, direction);
9601 }
9602
9603 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9604 size_t size,
9605 enum dma_data_direction direction)
9606 {
9607 dma_unmap_single(dev, dma_address, size, direction);
9608 }
9609
9610 static const struct niu_ops niu_pci_ops = {
9611 .alloc_coherent = niu_pci_alloc_coherent,
9612 .free_coherent = niu_pci_free_coherent,
9613 .map_page = niu_pci_map_page,
9614 .unmap_page = niu_pci_unmap_page,
9615 .map_single = niu_pci_map_single,
9616 .unmap_single = niu_pci_unmap_single,
9617 };
9618
9619 static void niu_driver_version(void)
9620 {
9621 static int niu_version_printed;
9622
9623 if (niu_version_printed++ == 0)
9624 pr_info("%s", version);
9625 }
9626
9627 static struct net_device *niu_alloc_and_init(struct device *gen_dev,
9628 struct pci_dev *pdev,
9629 struct platform_device *op,
9630 const struct niu_ops *ops, u8 port)
9631 {
9632 struct net_device *dev;
9633 struct niu *np;
9634
9635 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9636 if (!dev)
9637 return NULL;
9638
9639 SET_NETDEV_DEV(dev, gen_dev);
9640
9641 np = netdev_priv(dev);
9642 np->dev = dev;
9643 np->pdev = pdev;
9644 np->op = op;
9645 np->device = gen_dev;
9646 np->ops = ops;
9647
9648 np->msg_enable = niu_debug;
9649
9650 spin_lock_init(&np->lock);
9651 INIT_WORK(&np->reset_task, niu_reset_task);
9652
9653 np->port = port;
9654
9655 return dev;
9656 }
9657
9658 static const struct net_device_ops niu_netdev_ops = {
9659 .ndo_open = niu_open,
9660 .ndo_stop = niu_close,
9661 .ndo_start_xmit = niu_start_xmit,
9662 .ndo_get_stats64 = niu_get_stats,
9663 .ndo_set_rx_mode = niu_set_rx_mode,
9664 .ndo_validate_addr = eth_validate_addr,
9665 .ndo_set_mac_address = niu_set_mac_addr,
9666 .ndo_do_ioctl = niu_ioctl,
9667 .ndo_tx_timeout = niu_tx_timeout,
9668 .ndo_change_mtu = niu_change_mtu,
9669 };
9670
9671 static void niu_assign_netdev_ops(struct net_device *dev)
9672 {
9673 dev->netdev_ops = &niu_netdev_ops;
9674 dev->ethtool_ops = &niu_ethtool_ops;
9675 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9676 }
9677
9678 static void niu_device_announce(struct niu *np)
9679 {
9680 struct net_device *dev = np->dev;
9681
9682 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9683
9684 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9685 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9686 dev->name,
9687 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9688 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9689 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9690 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9691 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9692 np->vpd.phy_type);
9693 } else {
9694 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9695 dev->name,
9696 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9697 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9698 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9699 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9700 "COPPER")),
9701 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9702 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9703 np->vpd.phy_type);
9704 }
9705 }
9706
9707 static void niu_set_basic_features(struct net_device *dev)
9708 {
9709 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9710 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9711 }
9712
9713 static int niu_pci_init_one(struct pci_dev *pdev,
9714 const struct pci_device_id *ent)
9715 {
9716 union niu_parent_id parent_id;
9717 struct net_device *dev;
9718 struct niu *np;
9719 int err;
9720 u64 dma_mask;
9721
9722 niu_driver_version();
9723
9724 err = pci_enable_device(pdev);
9725 if (err) {
9726 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9727 return err;
9728 }
9729
9730 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9731 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9732 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9733 err = -ENODEV;
9734 goto err_out_disable_pdev;
9735 }
9736
9737 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9738 if (err) {
9739 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9740 goto err_out_disable_pdev;
9741 }
9742
9743 if (!pci_is_pcie(pdev)) {
9744 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9745 err = -ENODEV;
9746 goto err_out_free_res;
9747 }
9748
9749 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9750 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9751 if (!dev) {
9752 err = -ENOMEM;
9753 goto err_out_free_res;
9754 }
9755 np = netdev_priv(dev);
9756
9757 memset(&parent_id, 0, sizeof(parent_id));
9758 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9759 parent_id.pci.bus = pdev->bus->number;
9760 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9761
9762 np->parent = niu_get_parent(np, &parent_id,
9763 PLAT_TYPE_ATLAS);
9764 if (!np->parent) {
9765 err = -ENOMEM;
9766 goto err_out_free_dev;
9767 }
9768
9769 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
9770 PCI_EXP_DEVCTL_NOSNOOP_EN,
9771 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
9772 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
9773 PCI_EXP_DEVCTL_RELAX_EN);
9774
9775 dma_mask = DMA_BIT_MASK(44);
9776 err = pci_set_dma_mask(pdev, dma_mask);
9777 if (!err) {
9778 dev->features |= NETIF_F_HIGHDMA;
9779 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9780 if (err) {
9781 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9782 goto err_out_release_parent;
9783 }
9784 }
9785 if (err) {
9786 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9787 if (err) {
9788 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9789 goto err_out_release_parent;
9790 }
9791 }
9792
9793 niu_set_basic_features(dev);
9794
9795 dev->priv_flags |= IFF_UNICAST_FLT;
9796
9797 np->regs = pci_ioremap_bar(pdev, 0);
9798 if (!np->regs) {
9799 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9800 err = -ENOMEM;
9801 goto err_out_release_parent;
9802 }
9803
9804 pci_set_master(pdev);
9805 pci_save_state(pdev);
9806
9807 dev->irq = pdev->irq;
9808
9809 /* MTU range: 68 - 9216 */
9810 dev->min_mtu = ETH_MIN_MTU;
9811 dev->max_mtu = NIU_MAX_MTU;
9812
9813 niu_assign_netdev_ops(dev);
9814
9815 err = niu_get_invariants(np);
9816 if (err) {
9817 if (err != -ENODEV)
9818 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9819 goto err_out_iounmap;
9820 }
9821
9822 err = register_netdev(dev);
9823 if (err) {
9824 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9825 goto err_out_iounmap;
9826 }
9827
9828 pci_set_drvdata(pdev, dev);
9829
9830 niu_device_announce(np);
9831
9832 return 0;
9833
9834 err_out_iounmap:
9835 if (np->regs) {
9836 iounmap(np->regs);
9837 np->regs = NULL;
9838 }
9839
9840 err_out_release_parent:
9841 niu_put_parent(np);
9842
9843 err_out_free_dev:
9844 free_netdev(dev);
9845
9846 err_out_free_res:
9847 pci_release_regions(pdev);
9848
9849 err_out_disable_pdev:
9850 pci_disable_device(pdev);
9851
9852 return err;
9853 }
9854
9855 static void niu_pci_remove_one(struct pci_dev *pdev)
9856 {
9857 struct net_device *dev = pci_get_drvdata(pdev);
9858
9859 if (dev) {
9860 struct niu *np = netdev_priv(dev);
9861
9862 unregister_netdev(dev);
9863 if (np->regs) {
9864 iounmap(np->regs);
9865 np->regs = NULL;
9866 }
9867
9868 niu_ldg_free(np);
9869
9870 niu_put_parent(np);
9871
9872 free_netdev(dev);
9873 pci_release_regions(pdev);
9874 pci_disable_device(pdev);
9875 }
9876 }
9877
9878 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9879 {
9880 struct net_device *dev = pci_get_drvdata(pdev);
9881 struct niu *np = netdev_priv(dev);
9882 unsigned long flags;
9883
9884 if (!netif_running(dev))
9885 return 0;
9886
9887 flush_work(&np->reset_task);
9888 niu_netif_stop(np);
9889
9890 del_timer_sync(&np->timer);
9891
9892 spin_lock_irqsave(&np->lock, flags);
9893 niu_enable_interrupts(np, 0);
9894 spin_unlock_irqrestore(&np->lock, flags);
9895
9896 netif_device_detach(dev);
9897
9898 spin_lock_irqsave(&np->lock, flags);
9899 niu_stop_hw(np);
9900 spin_unlock_irqrestore(&np->lock, flags);
9901
9902 pci_save_state(pdev);
9903
9904 return 0;
9905 }
9906
9907 static int niu_resume(struct pci_dev *pdev)
9908 {
9909 struct net_device *dev = pci_get_drvdata(pdev);
9910 struct niu *np = netdev_priv(dev);
9911 unsigned long flags;
9912 int err;
9913
9914 if (!netif_running(dev))
9915 return 0;
9916
9917 pci_restore_state(pdev);
9918
9919 netif_device_attach(dev);
9920
9921 spin_lock_irqsave(&np->lock, flags);
9922
9923 err = niu_init_hw(np);
9924 if (!err) {
9925 np->timer.expires = jiffies + HZ;
9926 add_timer(&np->timer);
9927 niu_netif_start(np);
9928 }
9929
9930 spin_unlock_irqrestore(&np->lock, flags);
9931
9932 return err;
9933 }
9934
9935 static struct pci_driver niu_pci_driver = {
9936 .name = DRV_MODULE_NAME,
9937 .id_table = niu_pci_tbl,
9938 .probe = niu_pci_init_one,
9939 .remove = niu_pci_remove_one,
9940 .suspend = niu_suspend,
9941 .resume = niu_resume,
9942 };
9943
9944 #ifdef CONFIG_SPARC64
9945 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9946 u64 *dma_addr, gfp_t flag)
9947 {
9948 unsigned long order = get_order(size);
9949 unsigned long page = __get_free_pages(flag, order);
9950
9951 if (page == 0UL)
9952 return NULL;
9953 memset((char *)page, 0, PAGE_SIZE << order);
9954 *dma_addr = __pa(page);
9955
9956 return (void *) page;
9957 }
9958
9959 static void niu_phys_free_coherent(struct device *dev, size_t size,
9960 void *cpu_addr, u64 handle)
9961 {
9962 unsigned long order = get_order(size);
9963
9964 free_pages((unsigned long) cpu_addr, order);
9965 }
9966
9967 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9968 unsigned long offset, size_t size,
9969 enum dma_data_direction direction)
9970 {
9971 return page_to_phys(page) + offset;
9972 }
9973
9974 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9975 size_t size, enum dma_data_direction direction)
9976 {
9977 /* Nothing to do. */
9978 }
9979
9980 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9981 size_t size,
9982 enum dma_data_direction direction)
9983 {
9984 return __pa(cpu_addr);
9985 }
9986
9987 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9988 size_t size,
9989 enum dma_data_direction direction)
9990 {
9991 /* Nothing to do. */
9992 }
9993
9994 static const struct niu_ops niu_phys_ops = {
9995 .alloc_coherent = niu_phys_alloc_coherent,
9996 .free_coherent = niu_phys_free_coherent,
9997 .map_page = niu_phys_map_page,
9998 .unmap_page = niu_phys_unmap_page,
9999 .map_single = niu_phys_map_single,
10000 .unmap_single = niu_phys_unmap_single,
10001 };
10002
10003 static int niu_of_probe(struct platform_device *op)
10004 {
10005 union niu_parent_id parent_id;
10006 struct net_device *dev;
10007 struct niu *np;
10008 const u32 *reg;
10009 int err;
10010
10011 niu_driver_version();
10012
10013 reg = of_get_property(op->dev.of_node, "reg", NULL);
10014 if (!reg) {
10015 dev_err(&op->dev, "%pOF: No 'reg' property, aborting\n",
10016 op->dev.of_node);
10017 return -ENODEV;
10018 }
10019
10020 dev = niu_alloc_and_init(&op->dev, NULL, op,
10021 &niu_phys_ops, reg[0] & 0x1);
10022 if (!dev) {
10023 err = -ENOMEM;
10024 goto err_out;
10025 }
10026 np = netdev_priv(dev);
10027
10028 memset(&parent_id, 0, sizeof(parent_id));
10029 parent_id.of = of_get_parent(op->dev.of_node);
10030
10031 np->parent = niu_get_parent(np, &parent_id,
10032 PLAT_TYPE_NIU);
10033 if (!np->parent) {
10034 err = -ENOMEM;
10035 goto err_out_free_dev;
10036 }
10037
10038 niu_set_basic_features(dev);
10039
10040 np->regs = of_ioremap(&op->resource[1], 0,
10041 resource_size(&op->resource[1]),
10042 "niu regs");
10043 if (!np->regs) {
10044 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10045 err = -ENOMEM;
10046 goto err_out_release_parent;
10047 }
10048
10049 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10050 resource_size(&op->resource[2]),
10051 "niu vregs-1");
10052 if (!np->vir_regs_1) {
10053 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10054 err = -ENOMEM;
10055 goto err_out_iounmap;
10056 }
10057
10058 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10059 resource_size(&op->resource[3]),
10060 "niu vregs-2");
10061 if (!np->vir_regs_2) {
10062 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10063 err = -ENOMEM;
10064 goto err_out_iounmap;
10065 }
10066
10067 niu_assign_netdev_ops(dev);
10068
10069 err = niu_get_invariants(np);
10070 if (err) {
10071 if (err != -ENODEV)
10072 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10073 goto err_out_iounmap;
10074 }
10075
10076 err = register_netdev(dev);
10077 if (err) {
10078 dev_err(&op->dev, "Cannot register net device, aborting\n");
10079 goto err_out_iounmap;
10080 }
10081
10082 platform_set_drvdata(op, dev);
10083
10084 niu_device_announce(np);
10085
10086 return 0;
10087
10088 err_out_iounmap:
10089 if (np->vir_regs_1) {
10090 of_iounmap(&op->resource[2], np->vir_regs_1,
10091 resource_size(&op->resource[2]));
10092 np->vir_regs_1 = NULL;
10093 }
10094
10095 if (np->vir_regs_2) {
10096 of_iounmap(&op->resource[3], np->vir_regs_2,
10097 resource_size(&op->resource[3]));
10098 np->vir_regs_2 = NULL;
10099 }
10100
10101 if (np->regs) {
10102 of_iounmap(&op->resource[1], np->regs,
10103 resource_size(&op->resource[1]));
10104 np->regs = NULL;
10105 }
10106
10107 err_out_release_parent:
10108 niu_put_parent(np);
10109
10110 err_out_free_dev:
10111 free_netdev(dev);
10112
10113 err_out:
10114 return err;
10115 }
10116
10117 static int niu_of_remove(struct platform_device *op)
10118 {
10119 struct net_device *dev = platform_get_drvdata(op);
10120
10121 if (dev) {
10122 struct niu *np = netdev_priv(dev);
10123
10124 unregister_netdev(dev);
10125
10126 if (np->vir_regs_1) {
10127 of_iounmap(&op->resource[2], np->vir_regs_1,
10128 resource_size(&op->resource[2]));
10129 np->vir_regs_1 = NULL;
10130 }
10131
10132 if (np->vir_regs_2) {
10133 of_iounmap(&op->resource[3], np->vir_regs_2,
10134 resource_size(&op->resource[3]));
10135 np->vir_regs_2 = NULL;
10136 }
10137
10138 if (np->regs) {
10139 of_iounmap(&op->resource[1], np->regs,
10140 resource_size(&op->resource[1]));
10141 np->regs = NULL;
10142 }
10143
10144 niu_ldg_free(np);
10145
10146 niu_put_parent(np);
10147
10148 free_netdev(dev);
10149 }
10150 return 0;
10151 }
10152
10153 static const struct of_device_id niu_match[] = {
10154 {
10155 .name = "network",
10156 .compatible = "SUNW,niusl",
10157 },
10158 {},
10159 };
10160 MODULE_DEVICE_TABLE(of, niu_match);
10161
10162 static struct platform_driver niu_of_driver = {
10163 .driver = {
10164 .name = "niu",
10165 .of_match_table = niu_match,
10166 },
10167 .probe = niu_of_probe,
10168 .remove = niu_of_remove,
10169 };
10170
10171 #endif /* CONFIG_SPARC64 */
10172
10173 static int __init niu_init(void)
10174 {
10175 int err = 0;
10176
10177 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10178
10179 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10180
10181 #ifdef CONFIG_SPARC64
10182 err = platform_driver_register(&niu_of_driver);
10183 #endif
10184
10185 if (!err) {
10186 err = pci_register_driver(&niu_pci_driver);
10187 #ifdef CONFIG_SPARC64
10188 if (err)
10189 platform_driver_unregister(&niu_of_driver);
10190 #endif
10191 }
10192
10193 return err;
10194 }
10195
10196 static void __exit niu_exit(void)
10197 {
10198 pci_unregister_driver(&niu_pci_driver);
10199 #ifdef CONFIG_SPARC64
10200 platform_driver_unregister(&niu_of_driver);
10201 #endif
10202 }
10203
10204 module_init(niu_init);
10205 module_exit(niu_exit);
Linux with added FPC-III support