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fm10k: cleanup namespace pollution
[linux/fpc-iii.git] / drivers / net / ethernet / sfc / ef10.c
blobc4a0e8a967dd7eebebbdeb7376f9d010bab9d596
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include "ef10_sriov.h"
19 #include <linux/in.h>
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
23
24 /* Hardware control for EF10 architecture including 'Huntington'. */
25
26 #define EFX_EF10_DRVGEN_EV 7
27 enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30 };
31
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50 #define HUNT_FILTER_TBL_ROWS 8192
51
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53 struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56 };
57
58 struct efx_ef10_filter_table {
59 /* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
66 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
68 */
69 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
71 #define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75 /* Shadow of net_device address lists, guarded by mac_lock */
76 #define EFX_EF10_FILTER_DEV_UC_MAX 32
77 #define EFX_EF10_FILTER_DEV_MC_MAX 256
78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
80 int dev_uc_count;
81 int dev_mc_count;
82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
86 };
87
88 /* An arbitrary search limit for the software hash table */
89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95 {
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101 }
102
103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104 {
105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
109 }
110
111 static bool efx_ef10_is_vf(struct efx_nic *efx)
112 {
113 return efx->type->is_vf;
114 }
115
116 static int efx_ef10_get_pf_index(struct efx_nic *efx)
117 {
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132 }
133
134 #ifdef CONFIG_SFC_SRIOV
135 static int efx_ef10_get_vf_index(struct efx_nic *efx)
136 {
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151 }
152 #endif
153
154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
155 {
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
175
176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
185 netif_err(efx, probe, efx->net_dev,
186 "current firmware does not support an RX prefix\n");
187 return -ENODEV;
188 }
189
190 return 0;
191 }
192
193 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
194 {
195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
196 int rc;
197
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
199 outbuf, sizeof(outbuf), NULL);
200 if (rc)
201 return rc;
202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
203 return rc > 0 ? rc : -ERANGE;
204 }
205
206 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
207 {
208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
209 size_t outlen;
210 int rc;
211
212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
213
214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
215 outbuf, sizeof(outbuf), &outlen);
216 if (rc)
217 return rc;
218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
219 return -EIO;
220
221 ether_addr_copy(mac_address,
222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
223 return 0;
224 }
225
226 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
227 {
228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
230 size_t outlen;
231 int num_addrs, rc;
232
233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
234 EVB_PORT_ID_ASSIGNED);
235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
237
238 if (rc)
239 return rc;
240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
241 return -EIO;
242
243 num_addrs = MCDI_DWORD(outbuf,
244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
245
246 WARN_ON(num_addrs != 1);
247
248 ether_addr_copy(mac_address,
249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
250
251 return 0;
252 }
253
254 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
255 struct device_attribute *attr,
256 char *buf)
257 {
258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
259
260 return sprintf(buf, "%d\n",
261 ((efx->mcdi->fn_flags) &
262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
263 ? 1 : 0);
264 }
265
266 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
267 struct device_attribute *attr,
268 char *buf)
269 {
270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
271
272 return sprintf(buf, "%d\n",
273 ((efx->mcdi->fn_flags) &
274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
275 ? 1 : 0);
276 }
277
278 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
279 NULL);
280 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
281
282 static int efx_ef10_probe(struct efx_nic *efx)
283 {
284 struct efx_ef10_nic_data *nic_data;
285 struct net_device *net_dev = efx->net_dev;
286 int i, rc;
287
288 /* We can have one VI for each 8K region. However, until we
289 * use TX option descriptors we need two TX queues per channel.
290 */
291 efx->max_channels = min_t(unsigned int,
292 EFX_MAX_CHANNELS,
293 efx_ef10_mem_map_size(efx) /
294 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
295 efx->max_tx_channels = efx->max_channels;
296 if (WARN_ON(efx->max_channels == 0))
297 return -EIO;
298
299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
300 if (!nic_data)
301 return -ENOMEM;
302 efx->nic_data = nic_data;
303
304 /* we assume later that we can copy from this buffer in dwords */
305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
306
307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
309 if (rc)
310 goto fail1;
311
312 /* Get the MC's warm boot count. In case it's rebooting right
313 * now, be prepared to retry.
314 */
315 i = 0;
316 for (;;) {
317 rc = efx_ef10_get_warm_boot_count(efx);
318 if (rc >= 0)
319 break;
320 if (++i == 5)
321 goto fail2;
322 ssleep(1);
323 }
324 nic_data->warm_boot_count = rc;
325
326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
327
328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
329
330 /* In case we're recovering from a crash (kexec), we want to
331 * cancel any outstanding request by the previous user of this
332 * function. We send a special message using the least
333 * significant bits of the 'high' (doorbell) register.
334 */
335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
336
337 rc = efx_mcdi_init(efx);
338 if (rc)
339 goto fail2;
340
341 /* Reset (most) configuration for this function */
342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
343 if (rc)
344 goto fail3;
345
346 /* Enable event logging */
347 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
348 if (rc)
349 goto fail3;
350
351 rc = device_create_file(&efx->pci_dev->dev,
352 &dev_attr_link_control_flag);
353 if (rc)
354 goto fail3;
355
356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
357 if (rc)
358 goto fail4;
359
360 rc = efx_ef10_get_pf_index(efx);
361 if (rc)
362 goto fail5;
363
364 rc = efx_ef10_init_datapath_caps(efx);
365 if (rc < 0)
366 goto fail5;
367
368 efx->rx_packet_len_offset =
369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
370
371 rc = efx_mcdi_port_get_number(efx);
372 if (rc < 0)
373 goto fail5;
374 efx->port_num = rc;
375 net_dev->dev_port = rc;
376
377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
378 if (rc)
379 goto fail5;
380
381 rc = efx_ef10_get_sysclk_freq(efx);
382 if (rc < 0)
383 goto fail5;
384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
385
386 /* Check whether firmware supports bug 35388 workaround.
387 * First try to enable it, then if we get EPERM, just
388 * ask if it's already enabled
389 */
390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
391 if (rc == 0) {
392 nic_data->workaround_35388 = true;
393 } else if (rc == -EPERM) {
394 unsigned int enabled;
395
396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
397 if (rc)
398 goto fail3;
399 nic_data->workaround_35388 = enabled &
400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
401 } else if (rc != -ENOSYS && rc != -ENOENT) {
402 goto fail5;
403 }
404 netif_dbg(efx, probe, efx->net_dev,
405 "workaround for bug 35388 is %sabled\n",
406 nic_data->workaround_35388 ? "en" : "dis");
407
408 rc = efx_mcdi_mon_probe(efx);
409 if (rc && rc != -EPERM)
410 goto fail5;
411
412 efx_ptp_probe(efx, NULL);
413
414 #ifdef CONFIG_SFC_SRIOV
415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
418
419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
420 } else
421 #endif
422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
423
424 return 0;
425
426 fail5:
427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
428 fail4:
429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
430 fail3:
431 efx_mcdi_fini(efx);
432 fail2:
433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
434 fail1:
435 kfree(nic_data);
436 efx->nic_data = NULL;
437 return rc;
438 }
439
440 static int efx_ef10_free_vis(struct efx_nic *efx)
441 {
442 MCDI_DECLARE_BUF_ERR(outbuf);
443 size_t outlen;
444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
445 outbuf, sizeof(outbuf), &outlen);
446
447 /* -EALREADY means nothing to free, so ignore */
448 if (rc == -EALREADY)
449 rc = 0;
450 if (rc)
451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
452 rc);
453 return rc;
454 }
455
456 #ifdef EFX_USE_PIO
457
458 static void efx_ef10_free_piobufs(struct efx_nic *efx)
459 {
460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
462 unsigned int i;
463 int rc;
464
465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
466
467 for (i = 0; i < nic_data->n_piobufs; i++) {
468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
469 nic_data->piobuf_handle[i]);
470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
471 NULL, 0, NULL);
472 WARN_ON(rc);
473 }
474
475 nic_data->n_piobufs = 0;
476 }
477
478 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
479 {
480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
482 unsigned int i;
483 size_t outlen;
484 int rc = 0;
485
486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
487
488 for (i = 0; i < n; i++) {
489 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
490 outbuf, sizeof(outbuf), &outlen);
491 if (rc)
492 break;
493 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
494 rc = -EIO;
495 break;
496 }
497 nic_data->piobuf_handle[i] =
498 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
499 netif_dbg(efx, probe, efx->net_dev,
500 "allocated PIO buffer %u handle %x\n", i,
501 nic_data->piobuf_handle[i]);
502 }
503
504 nic_data->n_piobufs = i;
505 if (rc)
506 efx_ef10_free_piobufs(efx);
507 return rc;
508 }
509
510 static int efx_ef10_link_piobufs(struct efx_nic *efx)
511 {
512 struct efx_ef10_nic_data *nic_data = efx->nic_data;
513 _MCDI_DECLARE_BUF(inbuf,
514 max(MC_CMD_LINK_PIOBUF_IN_LEN,
515 MC_CMD_UNLINK_PIOBUF_IN_LEN));
516 struct efx_channel *channel;
517 struct efx_tx_queue *tx_queue;
518 unsigned int offset, index;
519 int rc;
520
521 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
522 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
523
524 memset(inbuf, 0, sizeof(inbuf));
525
526 /* Link a buffer to each VI in the write-combining mapping */
527 for (index = 0; index < nic_data->n_piobufs; ++index) {
528 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
529 nic_data->piobuf_handle[index]);
530 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
531 nic_data->pio_write_vi_base + index);
532 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
533 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
534 NULL, 0, NULL);
535 if (rc) {
536 netif_err(efx, drv, efx->net_dev,
537 "failed to link VI %u to PIO buffer %u (%d)\n",
538 nic_data->pio_write_vi_base + index, index,
539 rc);
540 goto fail;
541 }
542 netif_dbg(efx, probe, efx->net_dev,
543 "linked VI %u to PIO buffer %u\n",
544 nic_data->pio_write_vi_base + index, index);
545 }
546
547 /* Link a buffer to each TX queue */
548 efx_for_each_channel(channel, efx) {
549 efx_for_each_channel_tx_queue(tx_queue, channel) {
550 /* We assign the PIO buffers to queues in
551 * reverse order to allow for the following
552 * special case.
553 */
554 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
555 tx_queue->channel->channel - 1) *
556 efx_piobuf_size);
557 index = offset / ER_DZ_TX_PIOBUF_SIZE;
558 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
559
560 /* When the host page size is 4K, the first
561 * host page in the WC mapping may be within
562 * the same VI page as the last TX queue. We
563 * can only link one buffer to each VI.
564 */
565 if (tx_queue->queue == nic_data->pio_write_vi_base) {
566 BUG_ON(index != 0);
567 rc = 0;
568 } else {
569 MCDI_SET_DWORD(inbuf,
570 LINK_PIOBUF_IN_PIOBUF_HANDLE,
571 nic_data->piobuf_handle[index]);
572 MCDI_SET_DWORD(inbuf,
573 LINK_PIOBUF_IN_TXQ_INSTANCE,
574 tx_queue->queue);
575 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
576 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
577 NULL, 0, NULL);
578 }
579
580 if (rc) {
581 /* This is non-fatal; the TX path just
582 * won't use PIO for this queue
583 */
584 netif_err(efx, drv, efx->net_dev,
585 "failed to link VI %u to PIO buffer %u (%d)\n",
586 tx_queue->queue, index, rc);
587 tx_queue->piobuf = NULL;
588 } else {
589 tx_queue->piobuf =
590 nic_data->pio_write_base +
591 index * EFX_VI_PAGE_SIZE + offset;
592 tx_queue->piobuf_offset = offset;
593 netif_dbg(efx, probe, efx->net_dev,
594 "linked VI %u to PIO buffer %u offset %x addr %p\n",
595 tx_queue->queue, index,
596 tx_queue->piobuf_offset,
597 tx_queue->piobuf);
598 }
599 }
600 }
601
602 return 0;
603
604 fail:
605 while (index--) {
606 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
607 nic_data->pio_write_vi_base + index);
608 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
609 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
610 NULL, 0, NULL);
611 }
612 return rc;
613 }
614
615 #else /* !EFX_USE_PIO */
616
617 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
618 {
619 return n == 0 ? 0 : -ENOBUFS;
620 }
621
622 static int efx_ef10_link_piobufs(struct efx_nic *efx)
623 {
624 return 0;
625 }
626
627 static void efx_ef10_free_piobufs(struct efx_nic *efx)
628 {
629 }
630
631 #endif /* EFX_USE_PIO */
632
633 static void efx_ef10_remove(struct efx_nic *efx)
634 {
635 struct efx_ef10_nic_data *nic_data = efx->nic_data;
636 int rc;
637
638 #ifdef CONFIG_SFC_SRIOV
639 struct efx_ef10_nic_data *nic_data_pf;
640 struct pci_dev *pci_dev_pf;
641 struct efx_nic *efx_pf;
642 struct ef10_vf *vf;
643
644 if (efx->pci_dev->is_virtfn) {
645 pci_dev_pf = efx->pci_dev->physfn;
646 if (pci_dev_pf) {
647 efx_pf = pci_get_drvdata(pci_dev_pf);
648 nic_data_pf = efx_pf->nic_data;
649 vf = nic_data_pf->vf + nic_data->vf_index;
650 vf->efx = NULL;
651 } else
652 netif_info(efx, drv, efx->net_dev,
653 "Could not get the PF id from VF\n");
654 }
655 #endif
656
657 efx_ptp_remove(efx);
658
659 efx_mcdi_mon_remove(efx);
660
661 efx_ef10_rx_free_indir_table(efx);
662
663 if (nic_data->wc_membase)
664 iounmap(nic_data->wc_membase);
665
666 rc = efx_ef10_free_vis(efx);
667 WARN_ON(rc != 0);
668
669 if (!nic_data->must_restore_piobufs)
670 efx_ef10_free_piobufs(efx);
671
672 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
673 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
674
675 efx_mcdi_fini(efx);
676 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
677 kfree(nic_data);
678 }
679
680 static int efx_ef10_probe_pf(struct efx_nic *efx)
681 {
682 return efx_ef10_probe(efx);
683 }
684
685 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
686 {
687 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
688
689 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
690 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
691 NULL, 0, NULL);
692 }
693
694 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
695 {
696 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
697
698 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
699 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
700 NULL, 0, NULL);
701 }
702
703 int efx_ef10_vport_add_mac(struct efx_nic *efx,
704 unsigned int port_id, u8 *mac)
705 {
706 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
707
708 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
709 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
710
711 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
712 sizeof(inbuf), NULL, 0, NULL);
713 }
714
715 int efx_ef10_vport_del_mac(struct efx_nic *efx,
716 unsigned int port_id, u8 *mac)
717 {
718 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
719
720 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
721 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
722
723 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
724 sizeof(inbuf), NULL, 0, NULL);
725 }
726
727 #ifdef CONFIG_SFC_SRIOV
728 static int efx_ef10_probe_vf(struct efx_nic *efx)
729 {
730 int rc;
731 struct pci_dev *pci_dev_pf;
732
733 /* If the parent PF has no VF data structure, it doesn't know about this
734 * VF so fail probe. The VF needs to be re-created. This can happen
735 * if the PF driver is unloaded while the VF is assigned to a guest.
736 */
737 pci_dev_pf = efx->pci_dev->physfn;
738 if (pci_dev_pf) {
739 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
740 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
741
742 if (!nic_data_pf->vf) {
743 netif_info(efx, drv, efx->net_dev,
744 "The VF cannot link to its parent PF; "
745 "please destroy and re-create the VF\n");
746 return -EBUSY;
747 }
748 }
749
750 rc = efx_ef10_probe(efx);
751 if (rc)
752 return rc;
753
754 rc = efx_ef10_get_vf_index(efx);
755 if (rc)
756 goto fail;
757
758 if (efx->pci_dev->is_virtfn) {
759 if (efx->pci_dev->physfn) {
760 struct efx_nic *efx_pf =
761 pci_get_drvdata(efx->pci_dev->physfn);
762 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
763 struct efx_ef10_nic_data *nic_data = efx->nic_data;
764
765 nic_data_p->vf[nic_data->vf_index].efx = efx;
766 nic_data_p->vf[nic_data->vf_index].pci_dev =
767 efx->pci_dev;
768 } else
769 netif_info(efx, drv, efx->net_dev,
770 "Could not get the PF id from VF\n");
771 }
772
773 return 0;
774
775 fail:
776 efx_ef10_remove(efx);
777 return rc;
778 }
779 #else
780 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
781 {
782 return 0;
783 }
784 #endif
785
786 static int efx_ef10_alloc_vis(struct efx_nic *efx,
787 unsigned int min_vis, unsigned int max_vis)
788 {
789 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
790 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
791 struct efx_ef10_nic_data *nic_data = efx->nic_data;
792 size_t outlen;
793 int rc;
794
795 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
796 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
797 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
798 outbuf, sizeof(outbuf), &outlen);
799 if (rc != 0)
800 return rc;
801
802 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
803 return -EIO;
804
805 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
806 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
807
808 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
809 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
810 return 0;
811 }
812
813 /* Note that the failure path of this function does not free
814 * resources, as this will be done by efx_ef10_remove().
815 */
816 static int efx_ef10_dimension_resources(struct efx_nic *efx)
817 {
818 struct efx_ef10_nic_data *nic_data = efx->nic_data;
819 unsigned int uc_mem_map_size, wc_mem_map_size;
820 unsigned int min_vis = max(EFX_TXQ_TYPES,
821 efx_separate_tx_channels ? 2 : 1);
822 unsigned int channel_vis, pio_write_vi_base, max_vis;
823 void __iomem *membase;
824 int rc;
825
826 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
827
828 #ifdef EFX_USE_PIO
829 /* Try to allocate PIO buffers if wanted and if the full
830 * number of PIO buffers would be sufficient to allocate one
831 * copy-buffer per TX channel. Failure is non-fatal, as there
832 * are only a small number of PIO buffers shared between all
833 * functions of the controller.
834 */
835 if (efx_piobuf_size != 0 &&
836 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
837 efx->n_tx_channels) {
838 unsigned int n_piobufs =
839 DIV_ROUND_UP(efx->n_tx_channels,
840 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
841
842 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
843 if (rc)
844 netif_err(efx, probe, efx->net_dev,
845 "failed to allocate PIO buffers (%d)\n", rc);
846 else
847 netif_dbg(efx, probe, efx->net_dev,
848 "allocated %u PIO buffers\n", n_piobufs);
849 }
850 #else
851 nic_data->n_piobufs = 0;
852 #endif
853
854 /* PIO buffers should be mapped with write-combining enabled,
855 * and we want to make single UC and WC mappings rather than
856 * several of each (in fact that's the only option if host
857 * page size is >4K). So we may allocate some extra VIs just
858 * for writing PIO buffers through.
859 *
860 * The UC mapping contains (channel_vis - 1) complete VIs and the
861 * first half of the next VI. Then the WC mapping begins with
862 * the second half of this last VI.
863 */
864 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
865 ER_DZ_TX_PIOBUF);
866 if (nic_data->n_piobufs) {
867 /* pio_write_vi_base rounds down to give the number of complete
868 * VIs inside the UC mapping.
869 */
870 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
871 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
872 nic_data->n_piobufs) *
873 EFX_VI_PAGE_SIZE) -
874 uc_mem_map_size);
875 max_vis = pio_write_vi_base + nic_data->n_piobufs;
876 } else {
877 pio_write_vi_base = 0;
878 wc_mem_map_size = 0;
879 max_vis = channel_vis;
880 }
881
882 /* In case the last attached driver failed to free VIs, do it now */
883 rc = efx_ef10_free_vis(efx);
884 if (rc != 0)
885 return rc;
886
887 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
888 if (rc != 0)
889 return rc;
890
891 if (nic_data->n_allocated_vis < channel_vis) {
892 netif_info(efx, drv, efx->net_dev,
893 "Could not allocate enough VIs to satisfy RSS"
894 " requirements. Performance may not be optimal.\n");
895 /* We didn't get the VIs to populate our channels.
896 * We could keep what we got but then we'd have more
897 * interrupts than we need.
898 * Instead calculate new max_channels and restart
899 */
900 efx->max_channels = nic_data->n_allocated_vis;
901 efx->max_tx_channels =
902 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
903
904 efx_ef10_free_vis(efx);
905 return -EAGAIN;
906 }
907
908 /* If we didn't get enough VIs to map all the PIO buffers, free the
909 * PIO buffers
910 */
911 if (nic_data->n_piobufs &&
912 nic_data->n_allocated_vis <
913 pio_write_vi_base + nic_data->n_piobufs) {
914 netif_dbg(efx, probe, efx->net_dev,
915 "%u VIs are not sufficient to map %u PIO buffers\n",
916 nic_data->n_allocated_vis, nic_data->n_piobufs);
917 efx_ef10_free_piobufs(efx);
918 }
919
920 /* Shrink the original UC mapping of the memory BAR */
921 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
922 if (!membase) {
923 netif_err(efx, probe, efx->net_dev,
924 "could not shrink memory BAR to %x\n",
925 uc_mem_map_size);
926 return -ENOMEM;
927 }
928 iounmap(efx->membase);
929 efx->membase = membase;
930
931 /* Set up the WC mapping if needed */
932 if (wc_mem_map_size) {
933 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
934 uc_mem_map_size,
935 wc_mem_map_size);
936 if (!nic_data->wc_membase) {
937 netif_err(efx, probe, efx->net_dev,
938 "could not allocate WC mapping of size %x\n",
939 wc_mem_map_size);
940 return -ENOMEM;
941 }
942 nic_data->pio_write_vi_base = pio_write_vi_base;
943 nic_data->pio_write_base =
944 nic_data->wc_membase +
945 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
946 uc_mem_map_size);
947
948 rc = efx_ef10_link_piobufs(efx);
949 if (rc)
950 efx_ef10_free_piobufs(efx);
951 }
952
953 netif_dbg(efx, probe, efx->net_dev,
954 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
955 &efx->membase_phys, efx->membase, uc_mem_map_size,
956 nic_data->wc_membase, wc_mem_map_size);
957
958 return 0;
959 }
960
961 static int efx_ef10_init_nic(struct efx_nic *efx)
962 {
963 struct efx_ef10_nic_data *nic_data = efx->nic_data;
964 int rc;
965
966 if (nic_data->must_check_datapath_caps) {
967 rc = efx_ef10_init_datapath_caps(efx);
968 if (rc)
969 return rc;
970 nic_data->must_check_datapath_caps = false;
971 }
972
973 if (nic_data->must_realloc_vis) {
974 /* We cannot let the number of VIs change now */
975 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
976 nic_data->n_allocated_vis);
977 if (rc)
978 return rc;
979 nic_data->must_realloc_vis = false;
980 }
981
982 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
983 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
984 if (rc == 0) {
985 rc = efx_ef10_link_piobufs(efx);
986 if (rc)
987 efx_ef10_free_piobufs(efx);
988 }
989
990 /* Log an error on failure, but this is non-fatal */
991 if (rc)
992 netif_err(efx, drv, efx->net_dev,
993 "failed to restore PIO buffers (%d)\n", rc);
994 nic_data->must_restore_piobufs = false;
995 }
996
997 /* don't fail init if RSS setup doesn't work */
998 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
999
1000 return 0;
1001 }
1002
1003 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1004 {
1005 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1006 #ifdef CONFIG_SFC_SRIOV
1007 unsigned int i;
1008 #endif
1009
1010 /* All our allocations have been reset */
1011 nic_data->must_realloc_vis = true;
1012 nic_data->must_restore_filters = true;
1013 nic_data->must_restore_piobufs = true;
1014 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1015
1016 /* Driver-created vswitches and vports must be re-created */
1017 nic_data->must_probe_vswitching = true;
1018 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1019 #ifdef CONFIG_SFC_SRIOV
1020 if (nic_data->vf)
1021 for (i = 0; i < efx->vf_count; i++)
1022 nic_data->vf[i].vport_id = 0;
1023 #endif
1024 }
1025
1026 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1027 {
1028 if (reason == RESET_TYPE_MC_FAILURE)
1029 return RESET_TYPE_DATAPATH;
1030
1031 return efx_mcdi_map_reset_reason(reason);
1032 }
1033
1034 static int efx_ef10_map_reset_flags(u32 *flags)
1035 {
1036 enum {
1037 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1038 ETH_RESET_SHARED_SHIFT),
1039 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1040 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1041 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1042 ETH_RESET_SHARED_SHIFT)
1043 };
1044
1045 /* We assume for now that our PCI function is permitted to
1046 * reset everything.
1047 */
1048
1049 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1050 *flags &= ~EF10_RESET_MC;
1051 return RESET_TYPE_WORLD;
1052 }
1053
1054 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1055 *flags &= ~EF10_RESET_PORT;
1056 return RESET_TYPE_ALL;
1057 }
1058
1059 /* no invisible reset implemented */
1060
1061 return -EINVAL;
1062 }
1063
1064 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1065 {
1066 int rc = efx_mcdi_reset(efx, reset_type);
1067
1068 /* Unprivileged functions return -EPERM, but need to return success
1069 * here so that the datapath is brought back up.
1070 */
1071 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1072 rc = 0;
1073
1074 /* If it was a port reset, trigger reallocation of MC resources.
1075 * Note that on an MC reset nothing needs to be done now because we'll
1076 * detect the MC reset later and handle it then.
1077 * For an FLR, we never get an MC reset event, but the MC has reset all
1078 * resources assigned to us, so we have to trigger reallocation now.
1079 */
1080 if ((reset_type == RESET_TYPE_ALL ||
1081 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1082 efx_ef10_reset_mc_allocations(efx);
1083 return rc;
1084 }
1085
1086 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1087 [EF10_STAT_ ## ext_name] = \
1088 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1089 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1090 [EF10_STAT_ ## int_name] = \
1091 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1092 #define EF10_OTHER_STAT(ext_name) \
1093 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1094 #define GENERIC_SW_STAT(ext_name) \
1095 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1096
1097 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1098 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1099 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1100 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1101 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1102 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1103 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1104 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1105 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1106 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1107 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1108 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1109 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1110 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1111 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1112 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1113 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1114 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1115 EF10_OTHER_STAT(port_rx_good_bytes),
1116 EF10_OTHER_STAT(port_rx_bad_bytes),
1117 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1118 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1119 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1120 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1121 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1122 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1123 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1124 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1125 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1126 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1127 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1128 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1129 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1130 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1131 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1132 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1133 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1134 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1135 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1136 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1137 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1138 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1139 GENERIC_SW_STAT(rx_nodesc_trunc),
1140 GENERIC_SW_STAT(rx_noskb_drops),
1141 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1142 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1143 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1144 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1145 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1146 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1147 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1148 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1149 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1150 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1151 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1152 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1153 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1154 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1155 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1156 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1157 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1158 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1159 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1160 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1161 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1162 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1163 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1164 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1165 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1166 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1167 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1168 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1169 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1170 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1171 };
1172
1173 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1174 (1ULL << EF10_STAT_port_tx_packets) | \
1175 (1ULL << EF10_STAT_port_tx_pause) | \
1176 (1ULL << EF10_STAT_port_tx_unicast) | \
1177 (1ULL << EF10_STAT_port_tx_multicast) | \
1178 (1ULL << EF10_STAT_port_tx_broadcast) | \
1179 (1ULL << EF10_STAT_port_rx_bytes) | \
1180 (1ULL << \
1181 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1182 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1183 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1184 (1ULL << EF10_STAT_port_rx_packets) | \
1185 (1ULL << EF10_STAT_port_rx_good) | \
1186 (1ULL << EF10_STAT_port_rx_bad) | \
1187 (1ULL << EF10_STAT_port_rx_pause) | \
1188 (1ULL << EF10_STAT_port_rx_control) | \
1189 (1ULL << EF10_STAT_port_rx_unicast) | \
1190 (1ULL << EF10_STAT_port_rx_multicast) | \
1191 (1ULL << EF10_STAT_port_rx_broadcast) | \
1192 (1ULL << EF10_STAT_port_rx_lt64) | \
1193 (1ULL << EF10_STAT_port_rx_64) | \
1194 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1195 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1196 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1197 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1198 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1199 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1200 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1201 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1202 (1ULL << EF10_STAT_port_rx_overflow) | \
1203 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1204 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1205 (1ULL << GENERIC_STAT_rx_noskb_drops))
1206
1207 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1208 * switchable port we do not expose these because they might not
1209 * include all the packets they should.
1210 */
1211 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1212 (1ULL << EF10_STAT_port_tx_lt64) | \
1213 (1ULL << EF10_STAT_port_tx_64) | \
1214 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1215 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1216 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1217 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1218 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1219 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1220
1221 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1222 * switchable port we do expose these because the errors will otherwise
1223 * be silent.
1224 */
1225 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1226 (1ULL << EF10_STAT_port_rx_length_error))
1227
1228 /* These statistics are only provided if the firmware supports the
1229 * capability PM_AND_RXDP_COUNTERS.
1230 */
1231 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1232 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1233 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1234 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1235 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1236 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1237 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1238 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1239 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1240 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1241 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1242 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1243 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1244
1245 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1246 {
1247 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1248 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1249 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1250
1251 if (!(efx->mcdi->fn_flags &
1252 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1253 return 0;
1254
1255 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1256 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1257 else
1258 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1259
1260 if (nic_data->datapath_caps &
1261 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1262 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1263
1264 return raw_mask;
1265 }
1266
1267 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1268 {
1269 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1270 u64 raw_mask[2];
1271
1272 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1273
1274 /* Only show vadaptor stats when EVB capability is present */
1275 if (nic_data->datapath_caps &
1276 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1277 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1278 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1279 } else {
1280 raw_mask[1] = 0;
1281 }
1282
1283 #if BITS_PER_LONG == 64
1284 mask[0] = raw_mask[0];
1285 mask[1] = raw_mask[1];
1286 #else
1287 mask[0] = raw_mask[0] & 0xffffffff;
1288 mask[1] = raw_mask[0] >> 32;
1289 mask[2] = raw_mask[1] & 0xffffffff;
1290 mask[3] = raw_mask[1] >> 32;
1291 #endif
1292 }
1293
1294 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1295 {
1296 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1297
1298 efx_ef10_get_stat_mask(efx, mask);
1299 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1300 mask, names);
1301 }
1302
1303 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1304 struct rtnl_link_stats64 *core_stats)
1305 {
1306 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1307 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1308 u64 *stats = nic_data->stats;
1309 size_t stats_count = 0, index;
1310
1311 efx_ef10_get_stat_mask(efx, mask);
1312
1313 if (full_stats) {
1314 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1315 if (efx_ef10_stat_desc[index].name) {
1316 *full_stats++ = stats[index];
1317 ++stats_count;
1318 }
1319 }
1320 }
1321
1322 if (!core_stats)
1323 return stats_count;
1324
1325 if (nic_data->datapath_caps &
1326 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1327 /* Use vadaptor stats. */
1328 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1329 stats[EF10_STAT_rx_multicast] +
1330 stats[EF10_STAT_rx_broadcast];
1331 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1332 stats[EF10_STAT_tx_multicast] +
1333 stats[EF10_STAT_tx_broadcast];
1334 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1335 stats[EF10_STAT_rx_multicast_bytes] +
1336 stats[EF10_STAT_rx_broadcast_bytes];
1337 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1338 stats[EF10_STAT_tx_multicast_bytes] +
1339 stats[EF10_STAT_tx_broadcast_bytes];
1340 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1341 stats[GENERIC_STAT_rx_noskb_drops];
1342 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1343 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1344 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1345 core_stats->rx_errors = core_stats->rx_crc_errors;
1346 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1347 } else {
1348 /* Use port stats. */
1349 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1350 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1351 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1352 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1353 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1354 stats[GENERIC_STAT_rx_nodesc_trunc] +
1355 stats[GENERIC_STAT_rx_noskb_drops];
1356 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1357 core_stats->rx_length_errors =
1358 stats[EF10_STAT_port_rx_gtjumbo] +
1359 stats[EF10_STAT_port_rx_length_error];
1360 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1361 core_stats->rx_frame_errors =
1362 stats[EF10_STAT_port_rx_align_error];
1363 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1364 core_stats->rx_errors = (core_stats->rx_length_errors +
1365 core_stats->rx_crc_errors +
1366 core_stats->rx_frame_errors);
1367 }
1368
1369 return stats_count;
1370 }
1371
1372 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1373 {
1374 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1375 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1376 __le64 generation_start, generation_end;
1377 u64 *stats = nic_data->stats;
1378 __le64 *dma_stats;
1379
1380 efx_ef10_get_stat_mask(efx, mask);
1381
1382 dma_stats = efx->stats_buffer.addr;
1383 nic_data = efx->nic_data;
1384
1385 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1386 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1387 return 0;
1388 rmb();
1389 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1390 stats, efx->stats_buffer.addr, false);
1391 rmb();
1392 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1393 if (generation_end != generation_start)
1394 return -EAGAIN;
1395
1396 /* Update derived statistics */
1397 efx_nic_fix_nodesc_drop_stat(efx,
1398 &stats[EF10_STAT_port_rx_nodesc_drops]);
1399 stats[EF10_STAT_port_rx_good_bytes] =
1400 stats[EF10_STAT_port_rx_bytes] -
1401 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1402 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1403 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1404 efx_update_sw_stats(efx, stats);
1405 return 0;
1406 }
1407
1408
1409 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1410 struct rtnl_link_stats64 *core_stats)
1411 {
1412 int retry;
1413
1414 /* If we're unlucky enough to read statistics during the DMA, wait
1415 * up to 10ms for it to finish (typically takes <500us)
1416 */
1417 for (retry = 0; retry < 100; ++retry) {
1418 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1419 break;
1420 udelay(100);
1421 }
1422
1423 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1424 }
1425
1426 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1427 {
1428 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1429 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1430 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1431 __le64 generation_start, generation_end;
1432 u64 *stats = nic_data->stats;
1433 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1434 struct efx_buffer stats_buf;
1435 __le64 *dma_stats;
1436 int rc;
1437
1438 spin_unlock_bh(&efx->stats_lock);
1439
1440 if (in_interrupt()) {
1441 /* If in atomic context, cannot update stats. Just update the
1442 * software stats and return so the caller can continue.
1443 */
1444 spin_lock_bh(&efx->stats_lock);
1445 efx_update_sw_stats(efx, stats);
1446 return 0;
1447 }
1448
1449 efx_ef10_get_stat_mask(efx, mask);
1450
1451 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1452 if (rc) {
1453 spin_lock_bh(&efx->stats_lock);
1454 return rc;
1455 }
1456
1457 dma_stats = stats_buf.addr;
1458 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1459
1460 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1461 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1462 MAC_STATS_IN_DMA, 1);
1463 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1464 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1465
1466 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1467 NULL, 0, NULL);
1468 spin_lock_bh(&efx->stats_lock);
1469 if (rc) {
1470 /* Expect ENOENT if DMA queues have not been set up */
1471 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1472 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1473 sizeof(inbuf), NULL, 0, rc);
1474 goto out;
1475 }
1476
1477 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1478 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1479 WARN_ON_ONCE(1);
1480 goto out;
1481 }
1482 rmb();
1483 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1484 stats, stats_buf.addr, false);
1485 rmb();
1486 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1487 if (generation_end != generation_start) {
1488 rc = -EAGAIN;
1489 goto out;
1490 }
1491
1492 efx_update_sw_stats(efx, stats);
1493 out:
1494 efx_nic_free_buffer(efx, &stats_buf);
1495 return rc;
1496 }
1497
1498 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1499 struct rtnl_link_stats64 *core_stats)
1500 {
1501 if (efx_ef10_try_update_nic_stats_vf(efx))
1502 return 0;
1503
1504 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1505 }
1506
1507 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1508 {
1509 struct efx_nic *efx = channel->efx;
1510 unsigned int mode, value;
1511 efx_dword_t timer_cmd;
1512
1513 if (channel->irq_moderation) {
1514 mode = 3;
1515 value = channel->irq_moderation - 1;
1516 } else {
1517 mode = 0;
1518 value = 0;
1519 }
1520
1521 if (EFX_EF10_WORKAROUND_35388(efx)) {
1522 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1523 EFE_DD_EVQ_IND_TIMER_FLAGS,
1524 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1525 ERF_DD_EVQ_IND_TIMER_VAL, value);
1526 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1527 channel->channel);
1528 } else {
1529 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1530 ERF_DZ_TC_TIMER_VAL, value);
1531 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1532 channel->channel);
1533 }
1534 }
1535
1536 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1537 struct ethtool_wolinfo *wol) {}
1538
1539 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1540 {
1541 return -EOPNOTSUPP;
1542 }
1543
1544 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1545 {
1546 wol->supported = 0;
1547 wol->wolopts = 0;
1548 memset(&wol->sopass, 0, sizeof(wol->sopass));
1549 }
1550
1551 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1552 {
1553 if (type != 0)
1554 return -EINVAL;
1555 return 0;
1556 }
1557
1558 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1559 const efx_dword_t *hdr, size_t hdr_len,
1560 const efx_dword_t *sdu, size_t sdu_len)
1561 {
1562 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1563 u8 *pdu = nic_data->mcdi_buf.addr;
1564
1565 memcpy(pdu, hdr, hdr_len);
1566 memcpy(pdu + hdr_len, sdu, sdu_len);
1567 wmb();
1568
1569 /* The hardware provides 'low' and 'high' (doorbell) registers
1570 * for passing the 64-bit address of an MCDI request to
1571 * firmware. However the dwords are swapped by firmware. The
1572 * least significant bits of the doorbell are then 0 for all
1573 * MCDI requests due to alignment.
1574 */
1575 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1576 ER_DZ_MC_DB_LWRD);
1577 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1578 ER_DZ_MC_DB_HWRD);
1579 }
1580
1581 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1582 {
1583 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1584 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1585
1586 rmb();
1587 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1588 }
1589
1590 static void
1591 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1592 size_t offset, size_t outlen)
1593 {
1594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1595 const u8 *pdu = nic_data->mcdi_buf.addr;
1596
1597 memcpy(outbuf, pdu + offset, outlen);
1598 }
1599
1600 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1601 {
1602 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1603
1604 /* All our allocations have been reset */
1605 efx_ef10_reset_mc_allocations(efx);
1606
1607 /* The datapath firmware might have been changed */
1608 nic_data->must_check_datapath_caps = true;
1609
1610 /* MAC statistics have been cleared on the NIC; clear the local
1611 * statistic that we update with efx_update_diff_stat().
1612 */
1613 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1614 }
1615
1616 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1617 {
1618 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1619 int rc;
1620
1621 rc = efx_ef10_get_warm_boot_count(efx);
1622 if (rc < 0) {
1623 /* The firmware is presumably in the process of
1624 * rebooting. However, we are supposed to report each
1625 * reboot just once, so we must only do that once we
1626 * can read and store the updated warm boot count.
1627 */
1628 return 0;
1629 }
1630
1631 if (rc == nic_data->warm_boot_count)
1632 return 0;
1633
1634 nic_data->warm_boot_count = rc;
1635 efx_ef10_mcdi_reboot_detected(efx);
1636
1637 return -EIO;
1638 }
1639
1640 /* Handle an MSI interrupt
1641 *
1642 * Handle an MSI hardware interrupt. This routine schedules event
1643 * queue processing. No interrupt acknowledgement cycle is necessary.
1644 * Also, we never need to check that the interrupt is for us, since
1645 * MSI interrupts cannot be shared.
1646 */
1647 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1648 {
1649 struct efx_msi_context *context = dev_id;
1650 struct efx_nic *efx = context->efx;
1651
1652 netif_vdbg(efx, intr, efx->net_dev,
1653 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1654
1655 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1656 /* Note test interrupts */
1657 if (context->index == efx->irq_level)
1658 efx->last_irq_cpu = raw_smp_processor_id();
1659
1660 /* Schedule processing of the channel */
1661 efx_schedule_channel_irq(efx->channel[context->index]);
1662 }
1663
1664 return IRQ_HANDLED;
1665 }
1666
1667 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1668 {
1669 struct efx_nic *efx = dev_id;
1670 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1671 struct efx_channel *channel;
1672 efx_dword_t reg;
1673 u32 queues;
1674
1675 /* Read the ISR which also ACKs the interrupts */
1676 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1677 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1678
1679 if (queues == 0)
1680 return IRQ_NONE;
1681
1682 if (likely(soft_enabled)) {
1683 /* Note test interrupts */
1684 if (queues & (1U << efx->irq_level))
1685 efx->last_irq_cpu = raw_smp_processor_id();
1686
1687 efx_for_each_channel(channel, efx) {
1688 if (queues & 1)
1689 efx_schedule_channel_irq(channel);
1690 queues >>= 1;
1691 }
1692 }
1693
1694 netif_vdbg(efx, intr, efx->net_dev,
1695 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1696 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1697
1698 return IRQ_HANDLED;
1699 }
1700
1701 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1702 {
1703 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1704
1705 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1706
1707 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1708 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1709 inbuf, sizeof(inbuf), NULL, 0, NULL);
1710 }
1711
1712 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1713 {
1714 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1715 (tx_queue->ptr_mask + 1) *
1716 sizeof(efx_qword_t),
1717 GFP_KERNEL);
1718 }
1719
1720 /* This writes to the TX_DESC_WPTR and also pushes data */
1721 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1722 const efx_qword_t *txd)
1723 {
1724 unsigned int write_ptr;
1725 efx_oword_t reg;
1726
1727 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1728 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1729 reg.qword[0] = *txd;
1730 efx_writeo_page(tx_queue->efx, &reg,
1731 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1732 }
1733
1734 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1735 {
1736 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1737 EFX_BUF_SIZE));
1738 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1739 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1740 struct efx_channel *channel = tx_queue->channel;
1741 struct efx_nic *efx = tx_queue->efx;
1742 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1743 size_t inlen;
1744 dma_addr_t dma_addr;
1745 efx_qword_t *txd;
1746 int rc;
1747 int i;
1748 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1749
1750 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1751 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1752 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1753 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1754 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1755 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1756 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1759
1760 dma_addr = tx_queue->txd.buf.dma_addr;
1761
1762 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1763 tx_queue->queue, entries, (u64)dma_addr);
1764
1765 for (i = 0; i < entries; ++i) {
1766 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1767 dma_addr += EFX_BUF_SIZE;
1768 }
1769
1770 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1771
1772 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1773 NULL, 0, NULL);
1774 if (rc)
1775 goto fail;
1776
1777 /* A previous user of this TX queue might have set us up the
1778 * bomb by writing a descriptor to the TX push collector but
1779 * not the doorbell. (Each collector belongs to a port, not a
1780 * queue or function, so cannot easily be reset.) We must
1781 * attempt to push a no-op descriptor in its place.
1782 */
1783 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1784 tx_queue->insert_count = 1;
1785 txd = efx_tx_desc(tx_queue, 0);
1786 EFX_POPULATE_QWORD_4(*txd,
1787 ESF_DZ_TX_DESC_IS_OPT, true,
1788 ESF_DZ_TX_OPTION_TYPE,
1789 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1790 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1791 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1792 tx_queue->write_count = 1;
1793
1794 if (nic_data->datapath_caps &
1795 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
1796 tx_queue->tso_version = 1;
1797 }
1798
1799 wmb();
1800 efx_ef10_push_tx_desc(tx_queue, txd);
1801
1802 return;
1803
1804 fail:
1805 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1806 tx_queue->queue);
1807 }
1808
1809 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1810 {
1811 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1812 MCDI_DECLARE_BUF_ERR(outbuf);
1813 struct efx_nic *efx = tx_queue->efx;
1814 size_t outlen;
1815 int rc;
1816
1817 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1818 tx_queue->queue);
1819
1820 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1821 outbuf, sizeof(outbuf), &outlen);
1822
1823 if (rc && rc != -EALREADY)
1824 goto fail;
1825
1826 return;
1827
1828 fail:
1829 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1830 outbuf, outlen, rc);
1831 }
1832
1833 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1834 {
1835 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1836 }
1837
1838 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1839 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1840 {
1841 unsigned int write_ptr;
1842 efx_dword_t reg;
1843
1844 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1845 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1846 efx_writed_page(tx_queue->efx, &reg,
1847 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1848 }
1849
1850 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1851 {
1852 unsigned int old_write_count = tx_queue->write_count;
1853 struct efx_tx_buffer *buffer;
1854 unsigned int write_ptr;
1855 efx_qword_t *txd;
1856
1857 tx_queue->xmit_more_available = false;
1858 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1859 return;
1860
1861 do {
1862 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1863 buffer = &tx_queue->buffer[write_ptr];
1864 txd = efx_tx_desc(tx_queue, write_ptr);
1865 ++tx_queue->write_count;
1866
1867 /* Create TX descriptor ring entry */
1868 if (buffer->flags & EFX_TX_BUF_OPTION) {
1869 *txd = buffer->option;
1870 } else {
1871 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1872 EFX_POPULATE_QWORD_3(
1873 *txd,
1874 ESF_DZ_TX_KER_CONT,
1875 buffer->flags & EFX_TX_BUF_CONT,
1876 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1877 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1878 }
1879 } while (tx_queue->write_count != tx_queue->insert_count);
1880
1881 wmb(); /* Ensure descriptors are written before they are fetched */
1882
1883 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1884 txd = efx_tx_desc(tx_queue,
1885 old_write_count & tx_queue->ptr_mask);
1886 efx_ef10_push_tx_desc(tx_queue, txd);
1887 ++tx_queue->pushes;
1888 } else {
1889 efx_ef10_notify_tx_desc(tx_queue);
1890 }
1891 }
1892
1893 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1894 bool exclusive, unsigned *context_size)
1895 {
1896 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1897 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1898 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1899 size_t outlen;
1900 int rc;
1901 u32 alloc_type = exclusive ?
1902 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1903 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1904 unsigned rss_spread = exclusive ?
1905 efx->rss_spread :
1906 min(rounddown_pow_of_two(efx->rss_spread),
1907 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1908
1909 if (!exclusive && rss_spread == 1) {
1910 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1911 if (context_size)
1912 *context_size = 1;
1913 return 0;
1914 }
1915
1916 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1917 nic_data->vport_id);
1918 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1919 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1920
1921 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1922 outbuf, sizeof(outbuf), &outlen);
1923 if (rc != 0)
1924 return rc;
1925
1926 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1927 return -EIO;
1928
1929 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1930
1931 if (context_size)
1932 *context_size = rss_spread;
1933
1934 return 0;
1935 }
1936
1937 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1938 {
1939 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1940 int rc;
1941
1942 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1943 context);
1944
1945 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1946 NULL, 0, NULL);
1947 WARN_ON(rc != 0);
1948 }
1949
1950 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1951 const u32 *rx_indir_table)
1952 {
1953 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1954 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1955 int i, rc;
1956
1957 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1958 context);
1959 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1960 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1961
1962 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1963 MCDI_PTR(tablebuf,
1964 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1965 (u8) rx_indir_table[i];
1966
1967 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1968 sizeof(tablebuf), NULL, 0, NULL);
1969 if (rc != 0)
1970 return rc;
1971
1972 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1973 context);
1974 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1975 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1976 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1977 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1978 efx->rx_hash_key[i];
1979
1980 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1981 sizeof(keybuf), NULL, 0, NULL);
1982 }
1983
1984 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1985 {
1986 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1987
1988 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1989 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1990 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1991 }
1992
1993 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1994 unsigned *context_size)
1995 {
1996 u32 new_rx_rss_context;
1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1999 false, context_size);
2000
2001 if (rc != 0)
2002 return rc;
2003
2004 nic_data->rx_rss_context = new_rx_rss_context;
2005 nic_data->rx_rss_context_exclusive = false;
2006 efx_set_default_rx_indir_table(efx);
2007 return 0;
2008 }
2009
2010 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2011 const u32 *rx_indir_table)
2012 {
2013 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2014 int rc;
2015 u32 new_rx_rss_context;
2016
2017 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2018 !nic_data->rx_rss_context_exclusive) {
2019 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2020 true, NULL);
2021 if (rc == -EOPNOTSUPP)
2022 return rc;
2023 else if (rc != 0)
2024 goto fail1;
2025 } else {
2026 new_rx_rss_context = nic_data->rx_rss_context;
2027 }
2028
2029 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2030 rx_indir_table);
2031 if (rc != 0)
2032 goto fail2;
2033
2034 if (nic_data->rx_rss_context != new_rx_rss_context)
2035 efx_ef10_rx_free_indir_table(efx);
2036 nic_data->rx_rss_context = new_rx_rss_context;
2037 nic_data->rx_rss_context_exclusive = true;
2038 if (rx_indir_table != efx->rx_indir_table)
2039 memcpy(efx->rx_indir_table, rx_indir_table,
2040 sizeof(efx->rx_indir_table));
2041 return 0;
2042
2043 fail2:
2044 if (new_rx_rss_context != nic_data->rx_rss_context)
2045 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2046 fail1:
2047 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2048 return rc;
2049 }
2050
2051 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2052 const u32 *rx_indir_table)
2053 {
2054 int rc;
2055
2056 if (efx->rss_spread == 1)
2057 return 0;
2058
2059 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2060
2061 if (rc == -ENOBUFS && !user) {
2062 unsigned context_size;
2063 bool mismatch = false;
2064 size_t i;
2065
2066 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2067 i++)
2068 mismatch = rx_indir_table[i] !=
2069 ethtool_rxfh_indir_default(i, efx->rss_spread);
2070
2071 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2072 if (rc == 0) {
2073 if (context_size != efx->rss_spread)
2074 netif_warn(efx, probe, efx->net_dev,
2075 "Could not allocate an exclusive RSS"
2076 " context; allocated a shared one of"
2077 " different size."
2078 " Wanted %u, got %u.\n",
2079 efx->rss_spread, context_size);
2080 else if (mismatch)
2081 netif_warn(efx, probe, efx->net_dev,
2082 "Could not allocate an exclusive RSS"
2083 " context; allocated a shared one but"
2084 " could not apply custom"
2085 " indirection.\n");
2086 else
2087 netif_info(efx, probe, efx->net_dev,
2088 "Could not allocate an exclusive RSS"
2089 " context; allocated a shared one.\n");
2090 }
2091 }
2092 return rc;
2093 }
2094
2095 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2096 const u32 *rx_indir_table
2097 __attribute__ ((unused)))
2098 {
2099 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2100
2101 if (user)
2102 return -EOPNOTSUPP;
2103 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2104 return 0;
2105 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2106 }
2107
2108 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2109 {
2110 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2111 (rx_queue->ptr_mask + 1) *
2112 sizeof(efx_qword_t),
2113 GFP_KERNEL);
2114 }
2115
2116 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2117 {
2118 MCDI_DECLARE_BUF(inbuf,
2119 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2120 EFX_BUF_SIZE));
2121 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2122 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2123 struct efx_nic *efx = rx_queue->efx;
2124 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2125 size_t inlen;
2126 dma_addr_t dma_addr;
2127 int rc;
2128 int i;
2129 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2130
2131 rx_queue->scatter_n = 0;
2132 rx_queue->scatter_len = 0;
2133
2134 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2135 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2136 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2137 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2138 efx_rx_queue_index(rx_queue));
2139 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2140 INIT_RXQ_IN_FLAG_PREFIX, 1,
2141 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2142 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2143 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2144
2145 dma_addr = rx_queue->rxd.buf.dma_addr;
2146
2147 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2148 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2149
2150 for (i = 0; i < entries; ++i) {
2151 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2152 dma_addr += EFX_BUF_SIZE;
2153 }
2154
2155 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2156
2157 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2158 NULL, 0, NULL);
2159 if (rc)
2160 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2161 efx_rx_queue_index(rx_queue));
2162 }
2163
2164 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2165 {
2166 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2167 MCDI_DECLARE_BUF_ERR(outbuf);
2168 struct efx_nic *efx = rx_queue->efx;
2169 size_t outlen;
2170 int rc;
2171
2172 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2173 efx_rx_queue_index(rx_queue));
2174
2175 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2176 outbuf, sizeof(outbuf), &outlen);
2177
2178 if (rc && rc != -EALREADY)
2179 goto fail;
2180
2181 return;
2182
2183 fail:
2184 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2185 outbuf, outlen, rc);
2186 }
2187
2188 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2189 {
2190 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2191 }
2192
2193 /* This creates an entry in the RX descriptor queue */
2194 static inline void
2195 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2196 {
2197 struct efx_rx_buffer *rx_buf;
2198 efx_qword_t *rxd;
2199
2200 rxd = efx_rx_desc(rx_queue, index);
2201 rx_buf = efx_rx_buffer(rx_queue, index);
2202 EFX_POPULATE_QWORD_2(*rxd,
2203 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2204 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2205 }
2206
2207 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2208 {
2209 struct efx_nic *efx = rx_queue->efx;
2210 unsigned int write_count;
2211 efx_dword_t reg;
2212
2213 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2214 write_count = rx_queue->added_count & ~7;
2215 if (rx_queue->notified_count == write_count)
2216 return;
2217
2218 do
2219 efx_ef10_build_rx_desc(
2220 rx_queue,
2221 rx_queue->notified_count & rx_queue->ptr_mask);
2222 while (++rx_queue->notified_count != write_count);
2223
2224 wmb();
2225 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2226 write_count & rx_queue->ptr_mask);
2227 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2228 efx_rx_queue_index(rx_queue));
2229 }
2230
2231 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2232
2233 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2234 {
2235 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2236 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2237 efx_qword_t event;
2238
2239 EFX_POPULATE_QWORD_2(event,
2240 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2241 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2242
2243 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2244
2245 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2246 * already swapped the data to little-endian order.
2247 */
2248 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2249 sizeof(efx_qword_t));
2250
2251 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2252 inbuf, sizeof(inbuf), 0,
2253 efx_ef10_rx_defer_refill_complete, 0);
2254 }
2255
2256 static void
2257 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2258 int rc, efx_dword_t *outbuf,
2259 size_t outlen_actual)
2260 {
2261 /* nothing to do */
2262 }
2263
2264 static int efx_ef10_ev_probe(struct efx_channel *channel)
2265 {
2266 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2267 (channel->eventq_mask + 1) *
2268 sizeof(efx_qword_t),
2269 GFP_KERNEL);
2270 }
2271
2272 static void efx_ef10_ev_fini(struct efx_channel *channel)
2273 {
2274 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2275 MCDI_DECLARE_BUF_ERR(outbuf);
2276 struct efx_nic *efx = channel->efx;
2277 size_t outlen;
2278 int rc;
2279
2280 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2281
2282 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2283 outbuf, sizeof(outbuf), &outlen);
2284
2285 if (rc && rc != -EALREADY)
2286 goto fail;
2287
2288 return;
2289
2290 fail:
2291 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2292 outbuf, outlen, rc);
2293 }
2294
2295 static int efx_ef10_ev_init(struct efx_channel *channel)
2296 {
2297 MCDI_DECLARE_BUF(inbuf,
2298 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2299 EFX_BUF_SIZE));
2300 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2301 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2302 struct efx_nic *efx = channel->efx;
2303 struct efx_ef10_nic_data *nic_data;
2304 bool supports_rx_merge;
2305 size_t inlen, outlen;
2306 unsigned int enabled, implemented;
2307 dma_addr_t dma_addr;
2308 int rc;
2309 int i;
2310
2311 nic_data = efx->nic_data;
2312 supports_rx_merge =
2313 !!(nic_data->datapath_caps &
2314 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2315
2316 /* Fill event queue with all ones (i.e. empty events) */
2317 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2318
2319 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2320 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2321 /* INIT_EVQ expects index in vector table, not absolute */
2322 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2323 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2324 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2325 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2326 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2327 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2328 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2329 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2330 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2331 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2332 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2333 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2334 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2335
2336 dma_addr = channel->eventq.buf.dma_addr;
2337 for (i = 0; i < entries; ++i) {
2338 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2339 dma_addr += EFX_BUF_SIZE;
2340 }
2341
2342 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2343
2344 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2345 outbuf, sizeof(outbuf), &outlen);
2346 /* IRQ return is ignored */
2347 if (channel->channel || rc)
2348 return rc;
2349
2350 /* Successfully created event queue on channel 0 */
2351 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2352 if (rc == -ENOSYS) {
2353 /* GET_WORKAROUNDS was implemented before the bug26807
2354 * workaround, thus the latter must be unavailable in this fw
2355 */
2356 nic_data->workaround_26807 = false;
2357 rc = 0;
2358 } else if (rc) {
2359 goto fail;
2360 } else {
2361 nic_data->workaround_26807 =
2362 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2363
2364 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2365 !nic_data->workaround_26807) {
2366 unsigned int flags;
2367
2368 rc = efx_mcdi_set_workaround(efx,
2369 MC_CMD_WORKAROUND_BUG26807,
2370 true, &flags);
2371
2372 if (!rc) {
2373 if (flags &
2374 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2375 netif_info(efx, drv, efx->net_dev,
2376 "other functions on NIC have been reset\n");
2377
2378 /* With MCFW v4.6.x and earlier, the
2379 * boot count will have incremented,
2380 * so re-read the warm_boot_count
2381 * value now to ensure this function
2382 * doesn't think it has changed next
2383 * time it checks.
2384 */
2385 rc = efx_ef10_get_warm_boot_count(efx);
2386 if (rc >= 0) {
2387 nic_data->warm_boot_count = rc;
2388 rc = 0;
2389 }
2390 }
2391 nic_data->workaround_26807 = true;
2392 } else if (rc == -EPERM) {
2393 rc = 0;
2394 }
2395 }
2396 }
2397
2398 if (!rc)
2399 return 0;
2400
2401 fail:
2402 efx_ef10_ev_fini(channel);
2403 return rc;
2404 }
2405
2406 static void efx_ef10_ev_remove(struct efx_channel *channel)
2407 {
2408 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2409 }
2410
2411 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2412 unsigned int rx_queue_label)
2413 {
2414 struct efx_nic *efx = rx_queue->efx;
2415
2416 netif_info(efx, hw, efx->net_dev,
2417 "rx event arrived on queue %d labeled as queue %u\n",
2418 efx_rx_queue_index(rx_queue), rx_queue_label);
2419
2420 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2421 }
2422
2423 static void
2424 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2425 unsigned int actual, unsigned int expected)
2426 {
2427 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2428 struct efx_nic *efx = rx_queue->efx;
2429
2430 netif_info(efx, hw, efx->net_dev,
2431 "dropped %d events (index=%d expected=%d)\n",
2432 dropped, actual, expected);
2433
2434 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2435 }
2436
2437 /* partially received RX was aborted. clean up. */
2438 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2439 {
2440 unsigned int rx_desc_ptr;
2441
2442 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2443 "scattered RX aborted (dropping %u buffers)\n",
2444 rx_queue->scatter_n);
2445
2446 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2447
2448 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2449 0, EFX_RX_PKT_DISCARD);
2450
2451 rx_queue->removed_count += rx_queue->scatter_n;
2452 rx_queue->scatter_n = 0;
2453 rx_queue->scatter_len = 0;
2454 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2455 }
2456
2457 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2458 const efx_qword_t *event)
2459 {
2460 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2461 unsigned int n_descs, n_packets, i;
2462 struct efx_nic *efx = channel->efx;
2463 struct efx_rx_queue *rx_queue;
2464 bool rx_cont;
2465 u16 flags = 0;
2466
2467 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2468 return 0;
2469
2470 /* Basic packet information */
2471 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2472 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2473 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2474 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2475 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2476
2477 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2478 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2479 EFX_QWORD_FMT "\n",
2480 EFX_QWORD_VAL(*event));
2481
2482 rx_queue = efx_channel_get_rx_queue(channel);
2483
2484 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2485 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2486
2487 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2488 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2489
2490 if (n_descs != rx_queue->scatter_n + 1) {
2491 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2492
2493 /* detect rx abort */
2494 if (unlikely(n_descs == rx_queue->scatter_n)) {
2495 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2496 netdev_WARN(efx->net_dev,
2497 "invalid RX abort: scatter_n=%u event="
2498 EFX_QWORD_FMT "\n",
2499 rx_queue->scatter_n,
2500 EFX_QWORD_VAL(*event));
2501 efx_ef10_handle_rx_abort(rx_queue);
2502 return 0;
2503 }
2504
2505 /* Check that RX completion merging is valid, i.e.
2506 * the current firmware supports it and this is a
2507 * non-scattered packet.
2508 */
2509 if (!(nic_data->datapath_caps &
2510 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2511 rx_queue->scatter_n != 0 || rx_cont) {
2512 efx_ef10_handle_rx_bad_lbits(
2513 rx_queue, next_ptr_lbits,
2514 (rx_queue->removed_count +
2515 rx_queue->scatter_n + 1) &
2516 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2517 return 0;
2518 }
2519
2520 /* Merged completion for multiple non-scattered packets */
2521 rx_queue->scatter_n = 1;
2522 rx_queue->scatter_len = 0;
2523 n_packets = n_descs;
2524 ++channel->n_rx_merge_events;
2525 channel->n_rx_merge_packets += n_packets;
2526 flags |= EFX_RX_PKT_PREFIX_LEN;
2527 } else {
2528 ++rx_queue->scatter_n;
2529 rx_queue->scatter_len += rx_bytes;
2530 if (rx_cont)
2531 return 0;
2532 n_packets = 1;
2533 }
2534
2535 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2536 flags |= EFX_RX_PKT_DISCARD;
2537
2538 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2539 channel->n_rx_ip_hdr_chksum_err += n_packets;
2540 } else if (unlikely(EFX_QWORD_FIELD(*event,
2541 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2542 channel->n_rx_tcp_udp_chksum_err += n_packets;
2543 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2544 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2545 flags |= EFX_RX_PKT_CSUMMED;
2546 }
2547
2548 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2549 flags |= EFX_RX_PKT_TCP;
2550
2551 channel->irq_mod_score += 2 * n_packets;
2552
2553 /* Handle received packet(s) */
2554 for (i = 0; i < n_packets; i++) {
2555 efx_rx_packet(rx_queue,
2556 rx_queue->removed_count & rx_queue->ptr_mask,
2557 rx_queue->scatter_n, rx_queue->scatter_len,
2558 flags);
2559 rx_queue->removed_count += rx_queue->scatter_n;
2560 }
2561
2562 rx_queue->scatter_n = 0;
2563 rx_queue->scatter_len = 0;
2564
2565 return n_packets;
2566 }
2567
2568 static int
2569 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2570 {
2571 struct efx_nic *efx = channel->efx;
2572 struct efx_tx_queue *tx_queue;
2573 unsigned int tx_ev_desc_ptr;
2574 unsigned int tx_ev_q_label;
2575 int tx_descs = 0;
2576
2577 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2578 return 0;
2579
2580 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2581 return 0;
2582
2583 /* Transmit completion */
2584 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2585 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2586 tx_queue = efx_channel_get_tx_queue(channel,
2587 tx_ev_q_label % EFX_TXQ_TYPES);
2588 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2589 tx_queue->ptr_mask);
2590 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2591
2592 return tx_descs;
2593 }
2594
2595 static void
2596 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2597 {
2598 struct efx_nic *efx = channel->efx;
2599 int subcode;
2600
2601 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2602
2603 switch (subcode) {
2604 case ESE_DZ_DRV_TIMER_EV:
2605 case ESE_DZ_DRV_WAKE_UP_EV:
2606 break;
2607 case ESE_DZ_DRV_START_UP_EV:
2608 /* event queue init complete. ok. */
2609 break;
2610 default:
2611 netif_err(efx, hw, efx->net_dev,
2612 "channel %d unknown driver event type %d"
2613 " (data " EFX_QWORD_FMT ")\n",
2614 channel->channel, subcode,
2615 EFX_QWORD_VAL(*event));
2616
2617 }
2618 }
2619
2620 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2621 efx_qword_t *event)
2622 {
2623 struct efx_nic *efx = channel->efx;
2624 u32 subcode;
2625
2626 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2627
2628 switch (subcode) {
2629 case EFX_EF10_TEST:
2630 channel->event_test_cpu = raw_smp_processor_id();
2631 break;
2632 case EFX_EF10_REFILL:
2633 /* The queue must be empty, so we won't receive any rx
2634 * events, so efx_process_channel() won't refill the
2635 * queue. Refill it here
2636 */
2637 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2638 break;
2639 default:
2640 netif_err(efx, hw, efx->net_dev,
2641 "channel %d unknown driver event type %u"
2642 " (data " EFX_QWORD_FMT ")\n",
2643 channel->channel, (unsigned) subcode,
2644 EFX_QWORD_VAL(*event));
2645 }
2646 }
2647
2648 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2649 {
2650 struct efx_nic *efx = channel->efx;
2651 efx_qword_t event, *p_event;
2652 unsigned int read_ptr;
2653 int ev_code;
2654 int tx_descs = 0;
2655 int spent = 0;
2656
2657 if (quota <= 0)
2658 return spent;
2659
2660 read_ptr = channel->eventq_read_ptr;
2661
2662 for (;;) {
2663 p_event = efx_event(channel, read_ptr);
2664 event = *p_event;
2665
2666 if (!efx_event_present(&event))
2667 break;
2668
2669 EFX_SET_QWORD(*p_event);
2670
2671 ++read_ptr;
2672
2673 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2674
2675 netif_vdbg(efx, drv, efx->net_dev,
2676 "processing event on %d " EFX_QWORD_FMT "\n",
2677 channel->channel, EFX_QWORD_VAL(event));
2678
2679 switch (ev_code) {
2680 case ESE_DZ_EV_CODE_MCDI_EV:
2681 efx_mcdi_process_event(channel, &event);
2682 break;
2683 case ESE_DZ_EV_CODE_RX_EV:
2684 spent += efx_ef10_handle_rx_event(channel, &event);
2685 if (spent >= quota) {
2686 /* XXX can we split a merged event to
2687 * avoid going over-quota?
2688 */
2689 spent = quota;
2690 goto out;
2691 }
2692 break;
2693 case ESE_DZ_EV_CODE_TX_EV:
2694 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2695 if (tx_descs > efx->txq_entries) {
2696 spent = quota;
2697 goto out;
2698 } else if (++spent == quota) {
2699 goto out;
2700 }
2701 break;
2702 case ESE_DZ_EV_CODE_DRIVER_EV:
2703 efx_ef10_handle_driver_event(channel, &event);
2704 if (++spent == quota)
2705 goto out;
2706 break;
2707 case EFX_EF10_DRVGEN_EV:
2708 efx_ef10_handle_driver_generated_event(channel, &event);
2709 break;
2710 default:
2711 netif_err(efx, hw, efx->net_dev,
2712 "channel %d unknown event type %d"
2713 " (data " EFX_QWORD_FMT ")\n",
2714 channel->channel, ev_code,
2715 EFX_QWORD_VAL(event));
2716 }
2717 }
2718
2719 out:
2720 channel->eventq_read_ptr = read_ptr;
2721 return spent;
2722 }
2723
2724 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2725 {
2726 struct efx_nic *efx = channel->efx;
2727 efx_dword_t rptr;
2728
2729 if (EFX_EF10_WORKAROUND_35388(efx)) {
2730 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2731 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2732 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2733 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2734
2735 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2736 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2737 ERF_DD_EVQ_IND_RPTR,
2738 (channel->eventq_read_ptr &
2739 channel->eventq_mask) >>
2740 ERF_DD_EVQ_IND_RPTR_WIDTH);
2741 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2742 channel->channel);
2743 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2744 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2745 ERF_DD_EVQ_IND_RPTR,
2746 channel->eventq_read_ptr &
2747 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2748 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2749 channel->channel);
2750 } else {
2751 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2752 channel->eventq_read_ptr &
2753 channel->eventq_mask);
2754 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2755 }
2756 }
2757
2758 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2759 {
2760 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2761 struct efx_nic *efx = channel->efx;
2762 efx_qword_t event;
2763 int rc;
2764
2765 EFX_POPULATE_QWORD_2(event,
2766 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2767 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2768
2769 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2770
2771 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2772 * already swapped the data to little-endian order.
2773 */
2774 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2775 sizeof(efx_qword_t));
2776
2777 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2778 NULL, 0, NULL);
2779 if (rc != 0)
2780 goto fail;
2781
2782 return;
2783
2784 fail:
2785 WARN_ON(true);
2786 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2787 }
2788
2789 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2790 {
2791 if (atomic_dec_and_test(&efx->active_queues))
2792 wake_up(&efx->flush_wq);
2793
2794 WARN_ON(atomic_read(&efx->active_queues) < 0);
2795 }
2796
2797 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2798 {
2799 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2800 struct efx_channel *channel;
2801 struct efx_tx_queue *tx_queue;
2802 struct efx_rx_queue *rx_queue;
2803 int pending;
2804
2805 /* If the MC has just rebooted, the TX/RX queues will have already been
2806 * torn down, but efx->active_queues needs to be set to zero.
2807 */
2808 if (nic_data->must_realloc_vis) {
2809 atomic_set(&efx->active_queues, 0);
2810 return 0;
2811 }
2812
2813 /* Do not attempt to write to the NIC during EEH recovery */
2814 if (efx->state != STATE_RECOVERY) {
2815 efx_for_each_channel(channel, efx) {
2816 efx_for_each_channel_rx_queue(rx_queue, channel)
2817 efx_ef10_rx_fini(rx_queue);
2818 efx_for_each_channel_tx_queue(tx_queue, channel)
2819 efx_ef10_tx_fini(tx_queue);
2820 }
2821
2822 wait_event_timeout(efx->flush_wq,
2823 atomic_read(&efx->active_queues) == 0,
2824 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2825 pending = atomic_read(&efx->active_queues);
2826 if (pending) {
2827 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2828 pending);
2829 return -ETIMEDOUT;
2830 }
2831 }
2832
2833 return 0;
2834 }
2835
2836 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2837 {
2838 atomic_set(&efx->active_queues, 0);
2839 }
2840
2841 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2842 const struct efx_filter_spec *right)
2843 {
2844 if ((left->match_flags ^ right->match_flags) |
2845 ((left->flags ^ right->flags) &
2846 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2847 return false;
2848
2849 return memcmp(&left->outer_vid, &right->outer_vid,
2850 sizeof(struct efx_filter_spec) -
2851 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2852 }
2853
2854 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2855 {
2856 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2857 return jhash2((const u32 *)&spec->outer_vid,
2858 (sizeof(struct efx_filter_spec) -
2859 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2860 0);
2861 /* XXX should we randomise the initval? */
2862 }
2863
2864 /* Decide whether a filter should be exclusive or else should allow
2865 * delivery to additional recipients. Currently we decide that
2866 * filters for specific local unicast MAC and IP addresses are
2867 * exclusive.
2868 */
2869 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2870 {
2871 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2872 !is_multicast_ether_addr(spec->loc_mac))
2873 return true;
2874
2875 if ((spec->match_flags &
2876 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2877 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2878 if (spec->ether_type == htons(ETH_P_IP) &&
2879 !ipv4_is_multicast(spec->loc_host[0]))
2880 return true;
2881 if (spec->ether_type == htons(ETH_P_IPV6) &&
2882 ((const u8 *)spec->loc_host)[0] != 0xff)
2883 return true;
2884 }
2885
2886 return false;
2887 }
2888
2889 static struct efx_filter_spec *
2890 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2891 unsigned int filter_idx)
2892 {
2893 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2894 ~EFX_EF10_FILTER_FLAGS);
2895 }
2896
2897 static unsigned int
2898 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2899 unsigned int filter_idx)
2900 {
2901 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2902 }
2903
2904 static void
2905 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2906 unsigned int filter_idx,
2907 const struct efx_filter_spec *spec,
2908 unsigned int flags)
2909 {
2910 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2911 }
2912
2913 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2914 const struct efx_filter_spec *spec,
2915 efx_dword_t *inbuf, u64 handle,
2916 bool replacing)
2917 {
2918 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2919
2920 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2921
2922 if (replacing) {
2923 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2924 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2925 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2926 } else {
2927 u32 match_fields = 0;
2928
2929 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2930 efx_ef10_filter_is_exclusive(spec) ?
2931 MC_CMD_FILTER_OP_IN_OP_INSERT :
2932 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2933
2934 /* Convert match flags and values. Unlike almost
2935 * everything else in MCDI, these fields are in
2936 * network byte order.
2937 */
2938 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2939 match_fields |=
2940 is_multicast_ether_addr(spec->loc_mac) ?
2941 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2942 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2943 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2944 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2945 match_fields |= \
2946 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2947 mcdi_field ## _LBN; \
2948 BUILD_BUG_ON( \
2949 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2950 sizeof(spec->gen_field)); \
2951 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2952 &spec->gen_field, sizeof(spec->gen_field)); \
2953 }
2954 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2955 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2956 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2957 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2958 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2959 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2960 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2961 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2962 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2963 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2964 #undef COPY_FIELD
2965 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2966 match_fields);
2967 }
2968
2969 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2970 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2971 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2972 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2973 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2974 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2975 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2976 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2977 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2978 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2979 0 : spec->dmaq_id);
2980 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2981 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2982 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2983 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2984 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2985 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2986 spec->rss_context !=
2987 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2988 spec->rss_context : nic_data->rx_rss_context);
2989 }
2990
2991 static int efx_ef10_filter_push(struct efx_nic *efx,
2992 const struct efx_filter_spec *spec,
2993 u64 *handle, bool replacing)
2994 {
2995 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2996 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2997 int rc;
2998
2999 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3000 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3001 outbuf, sizeof(outbuf), NULL);
3002 if (rc == 0)
3003 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3004 if (rc == -ENOSPC)
3005 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3006 return rc;
3007 }
3008
3009 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
3010 enum efx_filter_match_flags match_flags)
3011 {
3012 unsigned int match_pri;
3013
3014 for (match_pri = 0;
3015 match_pri < table->rx_match_count;
3016 match_pri++)
3017 if (table->rx_match_flags[match_pri] == match_flags)
3018 return match_pri;
3019
3020 return -EPROTONOSUPPORT;
3021 }
3022
3023 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3024 struct efx_filter_spec *spec,
3025 bool replace_equal)
3026 {
3027 struct efx_ef10_filter_table *table = efx->filter_state;
3028 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3029 struct efx_filter_spec *saved_spec;
3030 unsigned int match_pri, hash;
3031 unsigned int priv_flags;
3032 bool replacing = false;
3033 int ins_index = -1;
3034 DEFINE_WAIT(wait);
3035 bool is_mc_recip;
3036 s32 rc;
3037
3038 /* For now, only support RX filters */
3039 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3040 EFX_FILTER_FLAG_RX)
3041 return -EINVAL;
3042
3043 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3044 if (rc < 0)
3045 return rc;
3046 match_pri = rc;
3047
3048 hash = efx_ef10_filter_hash(spec);
3049 is_mc_recip = efx_filter_is_mc_recipient(spec);
3050 if (is_mc_recip)
3051 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3052
3053 /* Find any existing filters with the same match tuple or
3054 * else a free slot to insert at. If any of them are busy,
3055 * we have to wait and retry.
3056 */
3057 for (;;) {
3058 unsigned int depth = 1;
3059 unsigned int i;
3060
3061 spin_lock_bh(&efx->filter_lock);
3062
3063 for (;;) {
3064 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3065 saved_spec = efx_ef10_filter_entry_spec(table, i);
3066
3067 if (!saved_spec) {
3068 if (ins_index < 0)
3069 ins_index = i;
3070 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3071 if (table->entry[i].spec &
3072 EFX_EF10_FILTER_FLAG_BUSY)
3073 break;
3074 if (spec->priority < saved_spec->priority &&
3075 spec->priority != EFX_FILTER_PRI_AUTO) {
3076 rc = -EPERM;
3077 goto out_unlock;
3078 }
3079 if (!is_mc_recip) {
3080 /* This is the only one */
3081 if (spec->priority ==
3082 saved_spec->priority &&
3083 !replace_equal) {
3084 rc = -EEXIST;
3085 goto out_unlock;
3086 }
3087 ins_index = i;
3088 goto found;
3089 } else if (spec->priority >
3090 saved_spec->priority ||
3091 (spec->priority ==
3092 saved_spec->priority &&
3093 replace_equal)) {
3094 if (ins_index < 0)
3095 ins_index = i;
3096 else
3097 __set_bit(depth, mc_rem_map);
3098 }
3099 }
3100
3101 /* Once we reach the maximum search depth, use
3102 * the first suitable slot or return -EBUSY if
3103 * there was none
3104 */
3105 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3106 if (ins_index < 0) {
3107 rc = -EBUSY;
3108 goto out_unlock;
3109 }
3110 goto found;
3111 }
3112
3113 ++depth;
3114 }
3115
3116 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3117 spin_unlock_bh(&efx->filter_lock);
3118 schedule();
3119 }
3120
3121 found:
3122 /* Create a software table entry if necessary, and mark it
3123 * busy. We might yet fail to insert, but any attempt to
3124 * insert a conflicting filter while we're waiting for the
3125 * firmware must find the busy entry.
3126 */
3127 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3128 if (saved_spec) {
3129 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3130 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3131 /* Just make sure it won't be removed */
3132 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3133 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3134 table->entry[ins_index].spec &=
3135 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3136 rc = ins_index;
3137 goto out_unlock;
3138 }
3139 replacing = true;
3140 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3141 } else {
3142 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3143 if (!saved_spec) {
3144 rc = -ENOMEM;
3145 goto out_unlock;
3146 }
3147 *saved_spec = *spec;
3148 priv_flags = 0;
3149 }
3150 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3151 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3152
3153 /* Mark lower-priority multicast recipients busy prior to removal */
3154 if (is_mc_recip) {
3155 unsigned int depth, i;
3156
3157 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3158 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3159 if (test_bit(depth, mc_rem_map))
3160 table->entry[i].spec |=
3161 EFX_EF10_FILTER_FLAG_BUSY;
3162 }
3163 }
3164
3165 spin_unlock_bh(&efx->filter_lock);
3166
3167 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3168 replacing);
3169
3170 /* Finalise the software table entry */
3171 spin_lock_bh(&efx->filter_lock);
3172 if (rc == 0) {
3173 if (replacing) {
3174 /* Update the fields that may differ */
3175 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3176 saved_spec->flags |=
3177 EFX_FILTER_FLAG_RX_OVER_AUTO;
3178 saved_spec->priority = spec->priority;
3179 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3180 saved_spec->flags |= spec->flags;
3181 saved_spec->rss_context = spec->rss_context;
3182 saved_spec->dmaq_id = spec->dmaq_id;
3183 }
3184 } else if (!replacing) {
3185 kfree(saved_spec);
3186 saved_spec = NULL;
3187 }
3188 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3189
3190 /* Remove and finalise entries for lower-priority multicast
3191 * recipients
3192 */
3193 if (is_mc_recip) {
3194 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3195 unsigned int depth, i;
3196
3197 memset(inbuf, 0, sizeof(inbuf));
3198
3199 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3200 if (!test_bit(depth, mc_rem_map))
3201 continue;
3202
3203 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3204 saved_spec = efx_ef10_filter_entry_spec(table, i);
3205 priv_flags = efx_ef10_filter_entry_flags(table, i);
3206
3207 if (rc == 0) {
3208 spin_unlock_bh(&efx->filter_lock);
3209 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3210 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3211 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3212 table->entry[i].handle);
3213 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3214 inbuf, sizeof(inbuf),
3215 NULL, 0, NULL);
3216 spin_lock_bh(&efx->filter_lock);
3217 }
3218
3219 if (rc == 0) {
3220 kfree(saved_spec);
3221 saved_spec = NULL;
3222 priv_flags = 0;
3223 } else {
3224 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3225 }
3226 efx_ef10_filter_set_entry(table, i, saved_spec,
3227 priv_flags);
3228 }
3229 }
3230
3231 /* If successful, return the inserted filter ID */
3232 if (rc == 0)
3233 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3234
3235 wake_up_all(&table->waitq);
3236 out_unlock:
3237 spin_unlock_bh(&efx->filter_lock);
3238 finish_wait(&table->waitq, &wait);
3239 return rc;
3240 }
3241
3242 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3243 {
3244 /* no need to do anything here on EF10 */
3245 }
3246
3247 /* Remove a filter.
3248 * If !by_index, remove by ID
3249 * If by_index, remove by index
3250 * Filter ID may come from userland and must be range-checked.
3251 */
3252 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3253 unsigned int priority_mask,
3254 u32 filter_id, bool by_index)
3255 {
3256 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3257 struct efx_ef10_filter_table *table = efx->filter_state;
3258 MCDI_DECLARE_BUF(inbuf,
3259 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3260 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3261 struct efx_filter_spec *spec;
3262 DEFINE_WAIT(wait);
3263 int rc;
3264
3265 /* Find the software table entry and mark it busy. Don't
3266 * remove it yet; any attempt to update while we're waiting
3267 * for the firmware must find the busy entry.
3268 */
3269 for (;;) {
3270 spin_lock_bh(&efx->filter_lock);
3271 if (!(table->entry[filter_idx].spec &
3272 EFX_EF10_FILTER_FLAG_BUSY))
3273 break;
3274 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3275 spin_unlock_bh(&efx->filter_lock);
3276 schedule();
3277 }
3278
3279 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3280 if (!spec ||
3281 (!by_index &&
3282 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3283 filter_id / HUNT_FILTER_TBL_ROWS)) {
3284 rc = -ENOENT;
3285 goto out_unlock;
3286 }
3287
3288 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3289 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3290 /* Just remove flags */
3291 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3292 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3293 rc = 0;
3294 goto out_unlock;
3295 }
3296
3297 if (!(priority_mask & (1U << spec->priority))) {
3298 rc = -ENOENT;
3299 goto out_unlock;
3300 }
3301
3302 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3303 spin_unlock_bh(&efx->filter_lock);
3304
3305 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3306 /* Reset to an automatic filter */
3307
3308 struct efx_filter_spec new_spec = *spec;
3309
3310 new_spec.priority = EFX_FILTER_PRI_AUTO;
3311 new_spec.flags = (EFX_FILTER_FLAG_RX |
3312 EFX_FILTER_FLAG_RX_RSS);
3313 new_spec.dmaq_id = 0;
3314 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3315 rc = efx_ef10_filter_push(efx, &new_spec,
3316 &table->entry[filter_idx].handle,
3317 true);
3318
3319 spin_lock_bh(&efx->filter_lock);
3320 if (rc == 0)
3321 *spec = new_spec;
3322 } else {
3323 /* Really remove the filter */
3324
3325 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3326 efx_ef10_filter_is_exclusive(spec) ?
3327 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3328 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3329 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3330 table->entry[filter_idx].handle);
3331 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3332 inbuf, sizeof(inbuf), NULL, 0, NULL);
3333
3334 spin_lock_bh(&efx->filter_lock);
3335 if (rc == 0) {
3336 kfree(spec);
3337 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3338 }
3339 }
3340
3341 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3342 wake_up_all(&table->waitq);
3343 out_unlock:
3344 spin_unlock_bh(&efx->filter_lock);
3345 finish_wait(&table->waitq, &wait);
3346 return rc;
3347 }
3348
3349 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3350 enum efx_filter_priority priority,
3351 u32 filter_id)
3352 {
3353 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3354 filter_id, false);
3355 }
3356
3357 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3358 {
3359 return filter_id % HUNT_FILTER_TBL_ROWS;
3360 }
3361
3362 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3363 enum efx_filter_priority priority,
3364 u32 filter_id)
3365 {
3366 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3367 filter_id, true);
3368 }
3369
3370 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3371 enum efx_filter_priority priority,
3372 u32 filter_id, struct efx_filter_spec *spec)
3373 {
3374 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3375 struct efx_ef10_filter_table *table = efx->filter_state;
3376 const struct efx_filter_spec *saved_spec;
3377 int rc;
3378
3379 spin_lock_bh(&efx->filter_lock);
3380 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3381 if (saved_spec && saved_spec->priority == priority &&
3382 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3383 filter_id / HUNT_FILTER_TBL_ROWS) {
3384 *spec = *saved_spec;
3385 rc = 0;
3386 } else {
3387 rc = -ENOENT;
3388 }
3389 spin_unlock_bh(&efx->filter_lock);
3390 return rc;
3391 }
3392
3393 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3394 enum efx_filter_priority priority)
3395 {
3396 unsigned int priority_mask;
3397 unsigned int i;
3398 int rc;
3399
3400 priority_mask = (((1U << (priority + 1)) - 1) &
3401 ~(1U << EFX_FILTER_PRI_AUTO));
3402
3403 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3404 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3405 i, true);
3406 if (rc && rc != -ENOENT)
3407 return rc;
3408 }
3409
3410 return 0;
3411 }
3412
3413 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3414 enum efx_filter_priority priority)
3415 {
3416 struct efx_ef10_filter_table *table = efx->filter_state;
3417 unsigned int filter_idx;
3418 s32 count = 0;
3419
3420 spin_lock_bh(&efx->filter_lock);
3421 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3422 if (table->entry[filter_idx].spec &&
3423 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3424 priority)
3425 ++count;
3426 }
3427 spin_unlock_bh(&efx->filter_lock);
3428 return count;
3429 }
3430
3431 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3432 {
3433 struct efx_ef10_filter_table *table = efx->filter_state;
3434
3435 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3436 }
3437
3438 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3439 enum efx_filter_priority priority,
3440 u32 *buf, u32 size)
3441 {
3442 struct efx_ef10_filter_table *table = efx->filter_state;
3443 struct efx_filter_spec *spec;
3444 unsigned int filter_idx;
3445 s32 count = 0;
3446
3447 spin_lock_bh(&efx->filter_lock);
3448 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3449 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3450 if (spec && spec->priority == priority) {
3451 if (count == size) {
3452 count = -EMSGSIZE;
3453 break;
3454 }
3455 buf[count++] = (efx_ef10_filter_rx_match_pri(
3456 table, spec->match_flags) *
3457 HUNT_FILTER_TBL_ROWS +
3458 filter_idx);
3459 }
3460 }
3461 spin_unlock_bh(&efx->filter_lock);
3462 return count;
3463 }
3464
3465 #ifdef CONFIG_RFS_ACCEL
3466
3467 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3468
3469 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3470 struct efx_filter_spec *spec)
3471 {
3472 struct efx_ef10_filter_table *table = efx->filter_state;
3473 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3474 struct efx_filter_spec *saved_spec;
3475 unsigned int hash, i, depth = 1;
3476 bool replacing = false;
3477 int ins_index = -1;
3478 u64 cookie;
3479 s32 rc;
3480
3481 /* Must be an RX filter without RSS and not for a multicast
3482 * destination address (RFS only works for connected sockets).
3483 * These restrictions allow us to pass only a tiny amount of
3484 * data through to the completion function.
3485 */
3486 EFX_WARN_ON_PARANOID(spec->flags !=
3487 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3488 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3489 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3490
3491 hash = efx_ef10_filter_hash(spec);
3492
3493 spin_lock_bh(&efx->filter_lock);
3494
3495 /* Find any existing filter with the same match tuple or else
3496 * a free slot to insert at. If an existing filter is busy,
3497 * we have to give up.
3498 */
3499 for (;;) {
3500 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3501 saved_spec = efx_ef10_filter_entry_spec(table, i);
3502
3503 if (!saved_spec) {
3504 if (ins_index < 0)
3505 ins_index = i;
3506 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3507 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3508 rc = -EBUSY;
3509 goto fail_unlock;
3510 }
3511 if (spec->priority < saved_spec->priority) {
3512 rc = -EPERM;
3513 goto fail_unlock;
3514 }
3515 ins_index = i;
3516 break;
3517 }
3518
3519 /* Once we reach the maximum search depth, use the
3520 * first suitable slot or return -EBUSY if there was
3521 * none
3522 */
3523 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3524 if (ins_index < 0) {
3525 rc = -EBUSY;
3526 goto fail_unlock;
3527 }
3528 break;
3529 }
3530
3531 ++depth;
3532 }
3533
3534 /* Create a software table entry if necessary, and mark it
3535 * busy. We might yet fail to insert, but any attempt to
3536 * insert a conflicting filter while we're waiting for the
3537 * firmware must find the busy entry.
3538 */
3539 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3540 if (saved_spec) {
3541 replacing = true;
3542 } else {
3543 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3544 if (!saved_spec) {
3545 rc = -ENOMEM;
3546 goto fail_unlock;
3547 }
3548 *saved_spec = *spec;
3549 }
3550 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3551 EFX_EF10_FILTER_FLAG_BUSY);
3552
3553 spin_unlock_bh(&efx->filter_lock);
3554
3555 /* Pack up the variables needed on completion */
3556 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3557
3558 efx_ef10_filter_push_prep(efx, spec, inbuf,
3559 table->entry[ins_index].handle, replacing);
3560 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3561 MC_CMD_FILTER_OP_OUT_LEN,
3562 efx_ef10_filter_rfs_insert_complete, cookie);
3563
3564 return ins_index;
3565
3566 fail_unlock:
3567 spin_unlock_bh(&efx->filter_lock);
3568 return rc;
3569 }
3570
3571 static void
3572 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3573 int rc, efx_dword_t *outbuf,
3574 size_t outlen_actual)
3575 {
3576 struct efx_ef10_filter_table *table = efx->filter_state;
3577 unsigned int ins_index, dmaq_id;
3578 struct efx_filter_spec *spec;
3579 bool replacing;
3580
3581 /* Unpack the cookie */
3582 replacing = cookie >> 31;
3583 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3584 dmaq_id = cookie & 0xffff;
3585
3586 spin_lock_bh(&efx->filter_lock);
3587 spec = efx_ef10_filter_entry_spec(table, ins_index);
3588 if (rc == 0) {
3589 table->entry[ins_index].handle =
3590 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3591 if (replacing)
3592 spec->dmaq_id = dmaq_id;
3593 } else if (!replacing) {
3594 kfree(spec);
3595 spec = NULL;
3596 }
3597 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3598 spin_unlock_bh(&efx->filter_lock);
3599
3600 wake_up_all(&table->waitq);
3601 }
3602
3603 static void
3604 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3605 unsigned long filter_idx,
3606 int rc, efx_dword_t *outbuf,
3607 size_t outlen_actual);
3608
3609 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3610 unsigned int filter_idx)
3611 {
3612 struct efx_ef10_filter_table *table = efx->filter_state;
3613 struct efx_filter_spec *spec =
3614 efx_ef10_filter_entry_spec(table, filter_idx);
3615 MCDI_DECLARE_BUF(inbuf,
3616 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3617 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3618
3619 if (!spec ||
3620 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3621 spec->priority != EFX_FILTER_PRI_HINT ||
3622 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3623 flow_id, filter_idx))
3624 return false;
3625
3626 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3627 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3628 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3629 table->entry[filter_idx].handle);
3630 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3631 efx_ef10_filter_rfs_expire_complete, filter_idx))
3632 return false;
3633
3634 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3635 return true;
3636 }
3637
3638 static void
3639 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3640 unsigned long filter_idx,
3641 int rc, efx_dword_t *outbuf,
3642 size_t outlen_actual)
3643 {
3644 struct efx_ef10_filter_table *table = efx->filter_state;
3645 struct efx_filter_spec *spec =
3646 efx_ef10_filter_entry_spec(table, filter_idx);
3647
3648 spin_lock_bh(&efx->filter_lock);
3649 if (rc == 0) {
3650 kfree(spec);
3651 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3652 }
3653 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3654 wake_up_all(&table->waitq);
3655 spin_unlock_bh(&efx->filter_lock);
3656 }
3657
3658 #endif /* CONFIG_RFS_ACCEL */
3659
3660 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3661 {
3662 int match_flags = 0;
3663
3664 #define MAP_FLAG(gen_flag, mcdi_field) { \
3665 u32 old_mcdi_flags = mcdi_flags; \
3666 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3667 mcdi_field ## _LBN); \
3668 if (mcdi_flags != old_mcdi_flags) \
3669 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3670 }
3671 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3672 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3673 MAP_FLAG(REM_HOST, SRC_IP);
3674 MAP_FLAG(LOC_HOST, DST_IP);
3675 MAP_FLAG(REM_MAC, SRC_MAC);
3676 MAP_FLAG(REM_PORT, SRC_PORT);
3677 MAP_FLAG(LOC_MAC, DST_MAC);
3678 MAP_FLAG(LOC_PORT, DST_PORT);
3679 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3680 MAP_FLAG(INNER_VID, INNER_VLAN);
3681 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3682 MAP_FLAG(IP_PROTO, IP_PROTO);
3683 #undef MAP_FLAG
3684
3685 /* Did we map them all? */
3686 if (mcdi_flags)
3687 return -EINVAL;
3688
3689 return match_flags;
3690 }
3691
3692 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3693 {
3694 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3695 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3696 unsigned int pd_match_pri, pd_match_count;
3697 struct efx_ef10_filter_table *table;
3698 size_t outlen;
3699 int rc;
3700
3701 table = kzalloc(sizeof(*table), GFP_KERNEL);
3702 if (!table)
3703 return -ENOMEM;
3704
3705 /* Find out which RX filter types are supported, and their priorities */
3706 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3707 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3708 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3709 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3710 &outlen);
3711 if (rc)
3712 goto fail;
3713 pd_match_count = MCDI_VAR_ARRAY_LEN(
3714 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3715 table->rx_match_count = 0;
3716
3717 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3718 u32 mcdi_flags =
3719 MCDI_ARRAY_DWORD(
3720 outbuf,
3721 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3722 pd_match_pri);
3723 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3724 if (rc < 0) {
3725 netif_dbg(efx, probe, efx->net_dev,
3726 "%s: fw flags %#x pri %u not supported in driver\n",
3727 __func__, mcdi_flags, pd_match_pri);
3728 } else {
3729 netif_dbg(efx, probe, efx->net_dev,
3730 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3731 __func__, mcdi_flags, pd_match_pri,
3732 rc, table->rx_match_count);
3733 table->rx_match_flags[table->rx_match_count++] = rc;
3734 }
3735 }
3736
3737 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3738 if (!table->entry) {
3739 rc = -ENOMEM;
3740 goto fail;
3741 }
3742
3743 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3744 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3745 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3746
3747 efx->filter_state = table;
3748 init_waitqueue_head(&table->waitq);
3749 return 0;
3750
3751 fail:
3752 kfree(table);
3753 return rc;
3754 }
3755
3756 /* Caller must hold efx->filter_sem for read if race against
3757 * efx_ef10_filter_table_remove() is possible
3758 */
3759 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3760 {
3761 struct efx_ef10_filter_table *table = efx->filter_state;
3762 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3763 struct efx_filter_spec *spec;
3764 unsigned int filter_idx;
3765 bool failed = false;
3766 int rc;
3767
3768 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3769
3770 if (!nic_data->must_restore_filters)
3771 return;
3772
3773 if (!table)
3774 return;
3775
3776 spin_lock_bh(&efx->filter_lock);
3777
3778 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3779 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3780 if (!spec)
3781 continue;
3782
3783 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3784 spin_unlock_bh(&efx->filter_lock);
3785
3786 rc = efx_ef10_filter_push(efx, spec,
3787 &table->entry[filter_idx].handle,
3788 false);
3789 if (rc)
3790 failed = true;
3791
3792 spin_lock_bh(&efx->filter_lock);
3793 if (rc) {
3794 kfree(spec);
3795 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3796 } else {
3797 table->entry[filter_idx].spec &=
3798 ~EFX_EF10_FILTER_FLAG_BUSY;
3799 }
3800 }
3801
3802 spin_unlock_bh(&efx->filter_lock);
3803
3804 if (failed)
3805 netif_err(efx, hw, efx->net_dev,
3806 "unable to restore all filters\n");
3807 else
3808 nic_data->must_restore_filters = false;
3809 }
3810
3811 /* Caller must hold efx->filter_sem for write */
3812 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3813 {
3814 struct efx_ef10_filter_table *table = efx->filter_state;
3815 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3816 struct efx_filter_spec *spec;
3817 unsigned int filter_idx;
3818 int rc;
3819
3820 efx->filter_state = NULL;
3821 if (!table)
3822 return;
3823
3824 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3825 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3826 if (!spec)
3827 continue;
3828
3829 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3830 efx_ef10_filter_is_exclusive(spec) ?
3831 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3832 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3833 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3834 table->entry[filter_idx].handle);
3835 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3836 NULL, 0, NULL);
3837 if (rc)
3838 netdev_WARN(efx->net_dev,
3839 "filter_idx=%#x handle=%#llx\n",
3840 filter_idx,
3841 table->entry[filter_idx].handle);
3842 kfree(spec);
3843 }
3844
3845 vfree(table->entry);
3846 kfree(table);
3847 }
3848
3849 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3850 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3851 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3852 WARN_ON(!table->entry[filter_idx].spec); \
3853 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3854 }
3855 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
3856 {
3857 struct efx_ef10_filter_table *table = efx->filter_state;
3858 unsigned int filter_idx, i;
3859
3860 if (!table)
3861 return;
3862
3863 /* Mark old filters that may need to be removed */
3864 spin_lock_bh(&efx->filter_lock);
3865 for (i = 0; i < table->dev_uc_count; i++)
3866 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3867 for (i = 0; i < table->dev_mc_count; i++)
3868 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3869 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3870 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3871 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
3872 spin_unlock_bh(&efx->filter_lock);
3873 }
3874 #undef EFX_EF10_FILTER_DO_MARK_OLD
3875
3876 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3877 {
3878 struct efx_ef10_filter_table *table = efx->filter_state;
3879 struct net_device *net_dev = efx->net_dev;
3880 struct netdev_hw_addr *uc;
3881 int addr_count;
3882 unsigned int i;
3883
3884 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3885 addr_count = netdev_uc_count(net_dev);
3886 if (net_dev->flags & IFF_PROMISC)
3887 *promisc = true;
3888 table->dev_uc_count = 1 + addr_count;
3889 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3890 i = 1;
3891 netdev_for_each_uc_addr(uc, net_dev) {
3892 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3893 *promisc = true;
3894 break;
3895 }
3896 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3897 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3898 i++;
3899 }
3900 }
3901
3902 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3903 {
3904 struct efx_ef10_filter_table *table = efx->filter_state;
3905 struct net_device *net_dev = efx->net_dev;
3906 struct netdev_hw_addr *mc;
3907 unsigned int i, addr_count;
3908
3909 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3910 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3911 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
3912 *promisc = true;
3913
3914 addr_count = netdev_mc_count(net_dev);
3915 i = 0;
3916 netdev_for_each_mc_addr(mc, net_dev) {
3917 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3918 *promisc = true;
3919 break;
3920 }
3921 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3922 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3923 i++;
3924 }
3925
3926 table->dev_mc_count = i;
3927 }
3928
3929 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3930 bool multicast, bool rollback)
3931 {
3932 struct efx_ef10_filter_table *table = efx->filter_state;
3933 struct efx_ef10_dev_addr *addr_list;
3934 struct efx_filter_spec spec;
3935 u8 baddr[ETH_ALEN];
3936 unsigned int i, j;
3937 int addr_count;
3938 int rc;
3939
3940 if (multicast) {
3941 addr_list = table->dev_mc_list;
3942 addr_count = table->dev_mc_count;
3943 } else {
3944 addr_list = table->dev_uc_list;
3945 addr_count = table->dev_uc_count;
3946 }
3947
3948 /* Insert/renew filters */
3949 for (i = 0; i < addr_count; i++) {
3950 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3951 EFX_FILTER_FLAG_RX_RSS,
3952 0);
3953 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3954 addr_list[i].addr);
3955 rc = efx_ef10_filter_insert(efx, &spec, true);
3956 if (rc < 0) {
3957 if (rollback) {
3958 netif_info(efx, drv, efx->net_dev,
3959 "efx_ef10_filter_insert failed rc=%d\n",
3960 rc);
3961 /* Fall back to promiscuous */
3962 for (j = 0; j < i; j++) {
3963 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3964 continue;
3965 efx_ef10_filter_remove_unsafe(
3966 efx, EFX_FILTER_PRI_AUTO,
3967 addr_list[j].id);
3968 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3969 }
3970 return rc;
3971 } else {
3972 /* mark as not inserted, and carry on */
3973 rc = EFX_EF10_FILTER_ID_INVALID;
3974 }
3975 }
3976 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
3977 }
3978
3979 if (multicast && rollback) {
3980 /* Also need an Ethernet broadcast filter */
3981 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3982 EFX_FILTER_FLAG_RX_RSS,
3983 0);
3984 eth_broadcast_addr(baddr);
3985 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
3986 rc = efx_ef10_filter_insert(efx, &spec, true);
3987 if (rc < 0) {
3988 netif_warn(efx, drv, efx->net_dev,
3989 "Broadcast filter insert failed rc=%d\n", rc);
3990 /* Fall back to promiscuous */
3991 for (j = 0; j < i; j++) {
3992 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3993 continue;
3994 efx_ef10_filter_remove_unsafe(
3995 efx, EFX_FILTER_PRI_AUTO,
3996 addr_list[j].id);
3997 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3998 }
3999 return rc;
4000 } else {
4001 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4002 }
4003 }
4004
4005 return 0;
4006 }
4007
4008 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
4009 bool rollback)
4010 {
4011 struct efx_ef10_filter_table *table = efx->filter_state;
4012 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4013 struct efx_filter_spec spec;
4014 u8 baddr[ETH_ALEN];
4015 int rc;
4016
4017 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4018 EFX_FILTER_FLAG_RX_RSS,
4019 0);
4020
4021 if (multicast)
4022 efx_filter_set_mc_def(&spec);
4023 else
4024 efx_filter_set_uc_def(&spec);
4025
4026 rc = efx_ef10_filter_insert(efx, &spec, true);
4027 if (rc < 0) {
4028 netif_warn(efx, drv, efx->net_dev,
4029 "%scast mismatch filter insert failed rc=%d\n",
4030 multicast ? "Multi" : "Uni", rc);
4031 } else if (multicast) {
4032 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4033 if (!nic_data->workaround_26807) {
4034 /* Also need an Ethernet broadcast filter */
4035 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4036 EFX_FILTER_FLAG_RX_RSS,
4037 0);
4038 eth_broadcast_addr(baddr);
4039 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4040 baddr);
4041 rc = efx_ef10_filter_insert(efx, &spec, true);
4042 if (rc < 0) {
4043 netif_warn(efx, drv, efx->net_dev,
4044 "Broadcast filter insert failed rc=%d\n",
4045 rc);
4046 if (rollback) {
4047 /* Roll back the mc_def filter */
4048 efx_ef10_filter_remove_unsafe(
4049 efx, EFX_FILTER_PRI_AUTO,
4050 table->mcdef_id);
4051 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4052 return rc;
4053 }
4054 } else {
4055 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4056 }
4057 }
4058 rc = 0;
4059 } else {
4060 table->ucdef_id = rc;
4061 rc = 0;
4062 }
4063 return rc;
4064 }
4065
4066 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4067 * flag or removes these filters, we don't need to hold the filter_lock while
4068 * scanning for these filters.
4069 */
4070 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4071 {
4072 struct efx_ef10_filter_table *table = efx->filter_state;
4073 bool remove_failed = false;
4074 int i;
4075
4076 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4077 if (ACCESS_ONCE(table->entry[i].spec) &
4078 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4079 if (efx_ef10_filter_remove_internal(
4080 efx, 1U << EFX_FILTER_PRI_AUTO,
4081 i, true) < 0)
4082 remove_failed = true;
4083 }
4084 }
4085 WARN_ON(remove_failed);
4086 }
4087
4088 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4089 {
4090 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4091 u8 mac_old[ETH_ALEN];
4092 int rc, rc2;
4093
4094 /* Only reconfigure a PF-created vport */
4095 if (is_zero_ether_addr(nic_data->vport_mac))
4096 return 0;
4097
4098 efx_device_detach_sync(efx);
4099 efx_net_stop(efx->net_dev);
4100 down_write(&efx->filter_sem);
4101 efx_ef10_filter_table_remove(efx);
4102 up_write(&efx->filter_sem);
4103
4104 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4105 if (rc)
4106 goto restore_filters;
4107
4108 ether_addr_copy(mac_old, nic_data->vport_mac);
4109 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4110 nic_data->vport_mac);
4111 if (rc)
4112 goto restore_vadaptor;
4113
4114 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4115 efx->net_dev->dev_addr);
4116 if (!rc) {
4117 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4118 } else {
4119 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4120 if (rc2) {
4121 /* Failed to add original MAC, so clear vport_mac */
4122 eth_zero_addr(nic_data->vport_mac);
4123 goto reset_nic;
4124 }
4125 }
4126
4127 restore_vadaptor:
4128 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4129 if (rc2)
4130 goto reset_nic;
4131 restore_filters:
4132 down_write(&efx->filter_sem);
4133 rc2 = efx_ef10_filter_table_probe(efx);
4134 up_write(&efx->filter_sem);
4135 if (rc2)
4136 goto reset_nic;
4137
4138 rc2 = efx_net_open(efx->net_dev);
4139 if (rc2)
4140 goto reset_nic;
4141
4142 netif_device_attach(efx->net_dev);
4143
4144 return rc;
4145
4146 reset_nic:
4147 netif_err(efx, drv, efx->net_dev,
4148 "Failed to restore when changing MAC address - scheduling reset\n");
4149 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4150
4151 return rc ? rc : rc2;
4152 }
4153
4154 /* Caller must hold efx->filter_sem for read if race against
4155 * efx_ef10_filter_table_remove() is possible
4156 */
4157 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4158 {
4159 struct efx_ef10_filter_table *table = efx->filter_state;
4160 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4161 struct net_device *net_dev = efx->net_dev;
4162 bool uc_promisc = false, mc_promisc = false;
4163
4164 if (!efx_dev_registered(efx))
4165 return;
4166
4167 if (!table)
4168 return;
4169
4170 efx_ef10_filter_mark_old(efx);
4171
4172 /* Copy/convert the address lists; add the primary station
4173 * address and broadcast address
4174 */
4175 netif_addr_lock_bh(net_dev);
4176 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4177 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4178 netif_addr_unlock_bh(net_dev);
4179
4180 /* Insert/renew unicast filters */
4181 if (uc_promisc) {
4182 efx_ef10_filter_insert_def(efx, false, false);
4183 efx_ef10_filter_insert_addr_list(efx, false, false);
4184 } else {
4185 /* If any of the filters failed to insert, fall back to
4186 * promiscuous mode - add in the uc_def filter. But keep
4187 * our individual unicast filters.
4188 */
4189 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4190 efx_ef10_filter_insert_def(efx, false, false);
4191 }
4192
4193 /* Insert/renew multicast filters */
4194 /* If changing promiscuous state with cascaded multicast filters, remove
4195 * old filters first, so that packets are dropped rather than duplicated
4196 */
4197 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4198 efx_ef10_filter_remove_old(efx);
4199 if (mc_promisc) {
4200 if (nic_data->workaround_26807) {
4201 /* If we failed to insert promiscuous filters, rollback
4202 * and fall back to individual multicast filters
4203 */
4204 if (efx_ef10_filter_insert_def(efx, true, true)) {
4205 /* Changing promisc state, so remove old filters */
4206 efx_ef10_filter_remove_old(efx);
4207 efx_ef10_filter_insert_addr_list(efx, true, false);
4208 }
4209 } else {
4210 /* If we failed to insert promiscuous filters, don't
4211 * rollback. Regardless, also insert the mc_list
4212 */
4213 efx_ef10_filter_insert_def(efx, true, false);
4214 efx_ef10_filter_insert_addr_list(efx, true, false);
4215 }
4216 } else {
4217 /* If any filters failed to insert, rollback and fall back to
4218 * promiscuous mode - mc_def filter and maybe broadcast. If
4219 * that fails, roll back again and insert as many of our
4220 * individual multicast filters as we can.
4221 */
4222 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4223 /* Changing promisc state, so remove old filters */
4224 if (nic_data->workaround_26807)
4225 efx_ef10_filter_remove_old(efx);
4226 if (efx_ef10_filter_insert_def(efx, true, true))
4227 efx_ef10_filter_insert_addr_list(efx, true, false);
4228 }
4229 }
4230
4231 efx_ef10_filter_remove_old(efx);
4232 efx->mc_promisc = mc_promisc;
4233 }
4234
4235 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4236 {
4237 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4239 bool was_enabled = efx->port_enabled;
4240 int rc;
4241
4242 efx_device_detach_sync(efx);
4243 efx_net_stop(efx->net_dev);
4244 down_write(&efx->filter_sem);
4245 efx_ef10_filter_table_remove(efx);
4246
4247 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4248 efx->net_dev->dev_addr);
4249 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4250 nic_data->vport_id);
4251 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4252 sizeof(inbuf), NULL, 0, NULL);
4253
4254 efx_ef10_filter_table_probe(efx);
4255 up_write(&efx->filter_sem);
4256 if (was_enabled)
4257 efx_net_open(efx->net_dev);
4258 netif_device_attach(efx->net_dev);
4259
4260 #ifdef CONFIG_SFC_SRIOV
4261 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4262 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4263
4264 if (rc == -EPERM) {
4265 struct efx_nic *efx_pf;
4266
4267 /* Switch to PF and change MAC address on vport */
4268 efx_pf = pci_get_drvdata(pci_dev_pf);
4269
4270 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4271 nic_data->vf_index,
4272 efx->net_dev->dev_addr);
4273 } else if (!rc) {
4274 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4275 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4276 unsigned int i;
4277
4278 /* MAC address successfully changed by VF (with MAC
4279 * spoofing) so update the parent PF if possible.
4280 */
4281 for (i = 0; i < efx_pf->vf_count; ++i) {
4282 struct ef10_vf *vf = nic_data->vf + i;
4283
4284 if (vf->efx == efx) {
4285 ether_addr_copy(vf->mac,
4286 efx->net_dev->dev_addr);
4287 return 0;
4288 }
4289 }
4290 }
4291 } else
4292 #endif
4293 if (rc == -EPERM) {
4294 netif_err(efx, drv, efx->net_dev,
4295 "Cannot change MAC address; use sfboot to enable"
4296 " mac-spoofing on this interface\n");
4297 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4298 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4299 * fall-back to the method of changing the MAC address on the
4300 * vport. This only applies to PFs because such versions of
4301 * MCFW do not support VFs.
4302 */
4303 rc = efx_ef10_vport_set_mac_address(efx);
4304 } else {
4305 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4306 sizeof(inbuf), NULL, 0, rc);
4307 }
4308
4309 return rc;
4310 }
4311
4312 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4313 {
4314 efx_ef10_filter_sync_rx_mode(efx);
4315
4316 return efx_mcdi_set_mac(efx);
4317 }
4318
4319 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4320 {
4321 efx_ef10_filter_sync_rx_mode(efx);
4322
4323 return 0;
4324 }
4325
4326 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4327 {
4328 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4329
4330 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4331 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4332 NULL, 0, NULL);
4333 }
4334
4335 /* MC BISTs follow a different poll mechanism to phy BISTs.
4336 * The BIST is done in the poll handler on the MC, and the MCDI command
4337 * will block until the BIST is done.
4338 */
4339 static int efx_ef10_poll_bist(struct efx_nic *efx)
4340 {
4341 int rc;
4342 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4343 size_t outlen;
4344 u32 result;
4345
4346 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4347 outbuf, sizeof(outbuf), &outlen);
4348 if (rc != 0)
4349 return rc;
4350
4351 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4352 return -EIO;
4353
4354 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4355 switch (result) {
4356 case MC_CMD_POLL_BIST_PASSED:
4357 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4358 return 0;
4359 case MC_CMD_POLL_BIST_TIMEOUT:
4360 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4361 return -EIO;
4362 case MC_CMD_POLL_BIST_FAILED:
4363 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4364 return -EIO;
4365 default:
4366 netif_err(efx, hw, efx->net_dev,
4367 "BIST returned unknown result %u", result);
4368 return -EIO;
4369 }
4370 }
4371
4372 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4373 {
4374 int rc;
4375
4376 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4377
4378 rc = efx_ef10_start_bist(efx, bist_type);
4379 if (rc != 0)
4380 return rc;
4381
4382 return efx_ef10_poll_bist(efx);
4383 }
4384
4385 static int
4386 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4387 {
4388 int rc, rc2;
4389
4390 efx_reset_down(efx, RESET_TYPE_WORLD);
4391
4392 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4393 NULL, 0, NULL, 0, NULL);
4394 if (rc != 0)
4395 goto out;
4396
4397 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4398 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4399
4400 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4401
4402 out:
4403 if (rc == -EPERM)
4404 rc = 0;
4405 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4406 return rc ? rc : rc2;
4407 }
4408
4409 #ifdef CONFIG_SFC_MTD
4410
4411 struct efx_ef10_nvram_type_info {
4412 u16 type, type_mask;
4413 u8 port;
4414 const char *name;
4415 };
4416
4417 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4418 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4419 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4420 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4421 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4422 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4423 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4424 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4425 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4426 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
4427 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
4428 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4429 };
4430
4431 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4432 struct efx_mcdi_mtd_partition *part,
4433 unsigned int type)
4434 {
4435 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4436 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4437 const struct efx_ef10_nvram_type_info *info;
4438 size_t size, erase_size, outlen;
4439 bool protected;
4440 int rc;
4441
4442 for (info = efx_ef10_nvram_types; ; info++) {
4443 if (info ==
4444 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4445 return -ENODEV;
4446 if ((type & ~info->type_mask) == info->type)
4447 break;
4448 }
4449 if (info->port != efx_port_num(efx))
4450 return -ENODEV;
4451
4452 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4453 if (rc)
4454 return rc;
4455 if (protected)
4456 return -ENODEV; /* hide it */
4457
4458 part->nvram_type = type;
4459
4460 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4461 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4462 outbuf, sizeof(outbuf), &outlen);
4463 if (rc)
4464 return rc;
4465 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4466 return -EIO;
4467 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4468 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4469 part->fw_subtype = MCDI_DWORD(outbuf,
4470 NVRAM_METADATA_OUT_SUBTYPE);
4471
4472 part->common.dev_type_name = "EF10 NVRAM manager";
4473 part->common.type_name = info->name;
4474
4475 part->common.mtd.type = MTD_NORFLASH;
4476 part->common.mtd.flags = MTD_CAP_NORFLASH;
4477 part->common.mtd.size = size;
4478 part->common.mtd.erasesize = erase_size;
4479
4480 return 0;
4481 }
4482
4483 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4484 {
4485 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4486 struct efx_mcdi_mtd_partition *parts;
4487 size_t outlen, n_parts_total, i, n_parts;
4488 unsigned int type;
4489 int rc;
4490
4491 ASSERT_RTNL();
4492
4493 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4494 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4495 outbuf, sizeof(outbuf), &outlen);
4496 if (rc)
4497 return rc;
4498 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4499 return -EIO;
4500
4501 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4502 if (n_parts_total >
4503 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4504 return -EIO;
4505
4506 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4507 if (!parts)
4508 return -ENOMEM;
4509
4510 n_parts = 0;
4511 for (i = 0; i < n_parts_total; i++) {
4512 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4513 i);
4514 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4515 if (rc == 0)
4516 n_parts++;
4517 else if (rc != -ENODEV)
4518 goto fail;
4519 }
4520
4521 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4522 fail:
4523 if (rc)
4524 kfree(parts);
4525 return rc;
4526 }
4527
4528 #endif /* CONFIG_SFC_MTD */
4529
4530 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4531 {
4532 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4533 }
4534
4535 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4536 u32 host_time) {}
4537
4538 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4539 bool temp)
4540 {
4541 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4542 int rc;
4543
4544 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4545 channel->sync_events_state == SYNC_EVENTS_VALID ||
4546 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4547 return 0;
4548 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4549
4550 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4551 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4552 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4553 channel->channel);
4554
4555 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4556 inbuf, sizeof(inbuf), NULL, 0, NULL);
4557
4558 if (rc != 0)
4559 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4560 SYNC_EVENTS_DISABLED;
4561
4562 return rc;
4563 }
4564
4565 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4566 bool temp)
4567 {
4568 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4569 int rc;
4570
4571 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4572 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4573 return 0;
4574 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4575 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4576 return 0;
4577 }
4578 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4579 SYNC_EVENTS_DISABLED;
4580
4581 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4582 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4583 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4584 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4585 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4586 channel->channel);
4587
4588 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4589 inbuf, sizeof(inbuf), NULL, 0, NULL);
4590
4591 return rc;
4592 }
4593
4594 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4595 bool temp)
4596 {
4597 int (*set)(struct efx_channel *channel, bool temp);
4598 struct efx_channel *channel;
4599
4600 set = en ?
4601 efx_ef10_rx_enable_timestamping :
4602 efx_ef10_rx_disable_timestamping;
4603
4604 efx_for_each_channel(channel, efx) {
4605 int rc = set(channel, temp);
4606 if (en && rc != 0) {
4607 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4608 return rc;
4609 }
4610 }
4611
4612 return 0;
4613 }
4614
4615 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4616 struct hwtstamp_config *init)
4617 {
4618 return -EOPNOTSUPP;
4619 }
4620
4621 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4622 struct hwtstamp_config *init)
4623 {
4624 int rc;
4625
4626 switch (init->rx_filter) {
4627 case HWTSTAMP_FILTER_NONE:
4628 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4629 /* if TX timestamping is still requested then leave PTP on */
4630 return efx_ptp_change_mode(efx,
4631 init->tx_type != HWTSTAMP_TX_OFF, 0);
4632 case HWTSTAMP_FILTER_ALL:
4633 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4634 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4635 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4636 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4637 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4638 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4639 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4640 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4641 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4642 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4643 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4644 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4645 init->rx_filter = HWTSTAMP_FILTER_ALL;
4646 rc = efx_ptp_change_mode(efx, true, 0);
4647 if (!rc)
4648 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4649 if (rc)
4650 efx_ptp_change_mode(efx, false, 0);
4651 return rc;
4652 default:
4653 return -ERANGE;
4654 }
4655 }
4656
4657 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4658 .is_vf = true,
4659 .mem_bar = EFX_MEM_VF_BAR,
4660 .mem_map_size = efx_ef10_mem_map_size,
4661 .probe = efx_ef10_probe_vf,
4662 .remove = efx_ef10_remove,
4663 .dimension_resources = efx_ef10_dimension_resources,
4664 .init = efx_ef10_init_nic,
4665 .fini = efx_port_dummy_op_void,
4666 .map_reset_reason = efx_ef10_map_reset_reason,
4667 .map_reset_flags = efx_ef10_map_reset_flags,
4668 .reset = efx_ef10_reset,
4669 .probe_port = efx_mcdi_port_probe,
4670 .remove_port = efx_mcdi_port_remove,
4671 .fini_dmaq = efx_ef10_fini_dmaq,
4672 .prepare_flr = efx_ef10_prepare_flr,
4673 .finish_flr = efx_port_dummy_op_void,
4674 .describe_stats = efx_ef10_describe_stats,
4675 .update_stats = efx_ef10_update_stats_vf,
4676 .start_stats = efx_port_dummy_op_void,
4677 .pull_stats = efx_port_dummy_op_void,
4678 .stop_stats = efx_port_dummy_op_void,
4679 .set_id_led = efx_mcdi_set_id_led,
4680 .push_irq_moderation = efx_ef10_push_irq_moderation,
4681 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4682 .check_mac_fault = efx_mcdi_mac_check_fault,
4683 .reconfigure_port = efx_mcdi_port_reconfigure,
4684 .get_wol = efx_ef10_get_wol_vf,
4685 .set_wol = efx_ef10_set_wol_vf,
4686 .resume_wol = efx_port_dummy_op_void,
4687 .mcdi_request = efx_ef10_mcdi_request,
4688 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4689 .mcdi_read_response = efx_ef10_mcdi_read_response,
4690 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4691 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4692 .irq_enable_master = efx_port_dummy_op_void,
4693 .irq_test_generate = efx_ef10_irq_test_generate,
4694 .irq_disable_non_ev = efx_port_dummy_op_void,
4695 .irq_handle_msi = efx_ef10_msi_interrupt,
4696 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4697 .tx_probe = efx_ef10_tx_probe,
4698 .tx_init = efx_ef10_tx_init,
4699 .tx_remove = efx_ef10_tx_remove,
4700 .tx_write = efx_ef10_tx_write,
4701 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4702 .rx_probe = efx_ef10_rx_probe,
4703 .rx_init = efx_ef10_rx_init,
4704 .rx_remove = efx_ef10_rx_remove,
4705 .rx_write = efx_ef10_rx_write,
4706 .rx_defer_refill = efx_ef10_rx_defer_refill,
4707 .ev_probe = efx_ef10_ev_probe,
4708 .ev_init = efx_ef10_ev_init,
4709 .ev_fini = efx_ef10_ev_fini,
4710 .ev_remove = efx_ef10_ev_remove,
4711 .ev_process = efx_ef10_ev_process,
4712 .ev_read_ack = efx_ef10_ev_read_ack,
4713 .ev_test_generate = efx_ef10_ev_test_generate,
4714 .filter_table_probe = efx_ef10_filter_table_probe,
4715 .filter_table_restore = efx_ef10_filter_table_restore,
4716 .filter_table_remove = efx_ef10_filter_table_remove,
4717 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4718 .filter_insert = efx_ef10_filter_insert,
4719 .filter_remove_safe = efx_ef10_filter_remove_safe,
4720 .filter_get_safe = efx_ef10_filter_get_safe,
4721 .filter_clear_rx = efx_ef10_filter_clear_rx,
4722 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4723 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4724 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4725 #ifdef CONFIG_RFS_ACCEL
4726 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4727 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4728 #endif
4729 #ifdef CONFIG_SFC_MTD
4730 .mtd_probe = efx_port_dummy_op_int,
4731 #endif
4732 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4733 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4734 #ifdef CONFIG_SFC_SRIOV
4735 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4736 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4737 .vswitching_remove = efx_ef10_vswitching_remove_vf,
4738 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4739 #endif
4740 .get_mac_address = efx_ef10_get_mac_address_vf,
4741 .set_mac_address = efx_ef10_set_mac_address,
4742
4743 .revision = EFX_REV_HUNT_A0,
4744 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4745 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4746 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4747 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4748 .can_rx_scatter = true,
4749 .always_rx_scatter = true,
4750 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4751 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4752 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4753 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4754 .mcdi_max_ver = 2,
4755 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4756 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4757 1 << HWTSTAMP_FILTER_ALL,
4758 };
4759
4760 const struct efx_nic_type efx_hunt_a0_nic_type = {
4761 .is_vf = false,
4762 .mem_bar = EFX_MEM_BAR,
4763 .mem_map_size = efx_ef10_mem_map_size,
4764 .probe = efx_ef10_probe_pf,
4765 .remove = efx_ef10_remove,
4766 .dimension_resources = efx_ef10_dimension_resources,
4767 .init = efx_ef10_init_nic,
4768 .fini = efx_port_dummy_op_void,
4769 .map_reset_reason = efx_ef10_map_reset_reason,
4770 .map_reset_flags = efx_ef10_map_reset_flags,
4771 .reset = efx_ef10_reset,
4772 .probe_port = efx_mcdi_port_probe,
4773 .remove_port = efx_mcdi_port_remove,
4774 .fini_dmaq = efx_ef10_fini_dmaq,
4775 .prepare_flr = efx_ef10_prepare_flr,
4776 .finish_flr = efx_port_dummy_op_void,
4777 .describe_stats = efx_ef10_describe_stats,
4778 .update_stats = efx_ef10_update_stats_pf,
4779 .start_stats = efx_mcdi_mac_start_stats,
4780 .pull_stats = efx_mcdi_mac_pull_stats,
4781 .stop_stats = efx_mcdi_mac_stop_stats,
4782 .set_id_led = efx_mcdi_set_id_led,
4783 .push_irq_moderation = efx_ef10_push_irq_moderation,
4784 .reconfigure_mac = efx_ef10_mac_reconfigure,
4785 .check_mac_fault = efx_mcdi_mac_check_fault,
4786 .reconfigure_port = efx_mcdi_port_reconfigure,
4787 .get_wol = efx_ef10_get_wol,
4788 .set_wol = efx_ef10_set_wol,
4789 .resume_wol = efx_port_dummy_op_void,
4790 .test_chip = efx_ef10_test_chip,
4791 .test_nvram = efx_mcdi_nvram_test_all,
4792 .mcdi_request = efx_ef10_mcdi_request,
4793 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4794 .mcdi_read_response = efx_ef10_mcdi_read_response,
4795 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4796 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4797 .irq_enable_master = efx_port_dummy_op_void,
4798 .irq_test_generate = efx_ef10_irq_test_generate,
4799 .irq_disable_non_ev = efx_port_dummy_op_void,
4800 .irq_handle_msi = efx_ef10_msi_interrupt,
4801 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4802 .tx_probe = efx_ef10_tx_probe,
4803 .tx_init = efx_ef10_tx_init,
4804 .tx_remove = efx_ef10_tx_remove,
4805 .tx_write = efx_ef10_tx_write,
4806 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4807 .rx_probe = efx_ef10_rx_probe,
4808 .rx_init = efx_ef10_rx_init,
4809 .rx_remove = efx_ef10_rx_remove,
4810 .rx_write = efx_ef10_rx_write,
4811 .rx_defer_refill = efx_ef10_rx_defer_refill,
4812 .ev_probe = efx_ef10_ev_probe,
4813 .ev_init = efx_ef10_ev_init,
4814 .ev_fini = efx_ef10_ev_fini,
4815 .ev_remove = efx_ef10_ev_remove,
4816 .ev_process = efx_ef10_ev_process,
4817 .ev_read_ack = efx_ef10_ev_read_ack,
4818 .ev_test_generate = efx_ef10_ev_test_generate,
4819 .filter_table_probe = efx_ef10_filter_table_probe,
4820 .filter_table_restore = efx_ef10_filter_table_restore,
4821 .filter_table_remove = efx_ef10_filter_table_remove,
4822 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4823 .filter_insert = efx_ef10_filter_insert,
4824 .filter_remove_safe = efx_ef10_filter_remove_safe,
4825 .filter_get_safe = efx_ef10_filter_get_safe,
4826 .filter_clear_rx = efx_ef10_filter_clear_rx,
4827 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4828 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4829 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4830 #ifdef CONFIG_RFS_ACCEL
4831 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4832 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4833 #endif
4834 #ifdef CONFIG_SFC_MTD
4835 .mtd_probe = efx_ef10_mtd_probe,
4836 .mtd_rename = efx_mcdi_mtd_rename,
4837 .mtd_read = efx_mcdi_mtd_read,
4838 .mtd_erase = efx_mcdi_mtd_erase,
4839 .mtd_write = efx_mcdi_mtd_write,
4840 .mtd_sync = efx_mcdi_mtd_sync,
4841 #endif
4842 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4843 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4844 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4845 #ifdef CONFIG_SFC_SRIOV
4846 .sriov_configure = efx_ef10_sriov_configure,
4847 .sriov_init = efx_ef10_sriov_init,
4848 .sriov_fini = efx_ef10_sriov_fini,
4849 .sriov_wanted = efx_ef10_sriov_wanted,
4850 .sriov_reset = efx_ef10_sriov_reset,
4851 .sriov_flr = efx_ef10_sriov_flr,
4852 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4853 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4854 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4855 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4856 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4857 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4858 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4859 .vswitching_remove = efx_ef10_vswitching_remove_pf,
4860 #endif
4861 .get_mac_address = efx_ef10_get_mac_address_pf,
4862 .set_mac_address = efx_ef10_set_mac_address,
4863
4864 .revision = EFX_REV_HUNT_A0,
4865 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4866 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4867 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4868 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4869 .can_rx_scatter = true,
4870 .always_rx_scatter = true,
4871 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4872 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4873 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4874 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4875 .mcdi_max_ver = 2,
4876 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4877 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4878 1 << HWTSTAMP_FILTER_ALL,
4879 };
Linux with added FPC-III support