Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / crypto / nx / nx_csbcpb.h
bloba304f956d6f8d0cfc41cc0ecd4bbd0a333660234
2 #ifndef __NX_CSBCPB_H__
3 #define __NX_CSBCPB_H__
5 struct cop_symcpb_aes_ecb {
6 u8 key[32];
7 u8 __rsvd[80];
8 } __packed;
10 struct cop_symcpb_aes_cbc {
11 u8 iv[16];
12 u8 key[32];
13 u8 cv[16];
14 u32 spbc;
15 u8 __rsvd[44];
16 } __packed;
18 struct cop_symcpb_aes_gca {
19 u8 in_pat[16];
20 u8 key[32];
21 u8 out_pat[16];
22 u32 spbc;
23 u8 __rsvd[44];
24 } __packed;
26 struct cop_symcpb_aes_gcm {
27 u8 in_pat_or_aad[16];
28 u8 iv_or_cnt[16];
29 u64 bit_length_aad;
30 u64 bit_length_data;
31 u8 in_s0[16];
32 u8 key[32];
33 u8 __rsvd1[16];
34 u8 out_pat_or_mac[16];
35 u8 out_s0[16];
36 u8 out_cnt[16];
37 u32 spbc;
38 u8 __rsvd2[12];
39 } __packed;
41 struct cop_symcpb_aes_ctr {
42 u8 iv[16];
43 u8 key[32];
44 u8 cv[16];
45 u32 spbc;
46 u8 __rsvd2[44];
47 } __packed;
49 struct cop_symcpb_aes_cca {
50 u8 b0[16];
51 u8 b1[16];
52 u8 key[16];
53 u8 out_pat_or_b0[16];
54 u32 spbc;
55 u8 __rsvd[44];
56 } __packed;
58 struct cop_symcpb_aes_ccm {
59 u8 in_pat_or_b0[16];
60 u8 iv_or_ctr[16];
61 u8 in_s0[16];
62 u8 key[16];
63 u8 __rsvd1[48];
64 u8 out_pat_or_mac[16];
65 u8 out_s0[16];
66 u8 out_ctr[16];
67 u32 spbc;
68 u8 __rsvd2[12];
69 } __packed;
71 struct cop_symcpb_aes_xcbc {
72 u8 cv[16];
73 u8 key[16];
74 u8 __rsvd1[16];
75 u8 out_cv_mac[16];
76 u32 spbc;
77 u8 __rsvd2[44];
78 } __packed;
80 struct cop_symcpb_sha256 {
81 u64 message_bit_length;
82 u64 __rsvd1;
83 u8 input_partial_digest[32];
84 u8 message_digest[32];
85 u32 spbc;
86 u8 __rsvd2[44];
87 } __packed;
89 struct cop_symcpb_sha512 {
90 u64 message_bit_length_hi;
91 u64 message_bit_length_lo;
92 u8 input_partial_digest[64];
93 u8 __rsvd1[32];
94 u8 message_digest[64];
95 u32 spbc;
96 u8 __rsvd2[76];
97 } __packed;
99 #define NX_FDM_INTERMEDIATE 0x01
100 #define NX_FDM_CONTINUATION 0x02
101 #define NX_FDM_ENDE_ENCRYPT 0x80
103 #define NX_CPB_FDM(c) ((c)->cpb.hdr.fdm)
104 #define NX_CPB_KS_DS(c) ((c)->cpb.hdr.ks_ds)
106 #define NX_CPB_KEY_SIZE(c) (NX_CPB_KS_DS(c) >> 4)
107 #define NX_CPB_SET_KEY_SIZE(c, x) NX_CPB_KS_DS(c) |= ((x) << 4)
108 #define NX_CPB_SET_DIGEST_SIZE(c, x) NX_CPB_KS_DS(c) |= (x)
110 struct cop_symcpb_header {
111 u8 mode;
112 u8 fdm;
113 u8 ks_ds;
114 u8 pad_byte;
115 u8 __rsvd[12];
116 } __packed;
118 struct cop_parameter_block {
119 struct cop_symcpb_header hdr;
120 union {
121 struct cop_symcpb_aes_ecb aes_ecb;
122 struct cop_symcpb_aes_cbc aes_cbc;
123 struct cop_symcpb_aes_gca aes_gca;
124 struct cop_symcpb_aes_gcm aes_gcm;
125 struct cop_symcpb_aes_cca aes_cca;
126 struct cop_symcpb_aes_ccm aes_ccm;
127 struct cop_symcpb_aes_ctr aes_ctr;
128 struct cop_symcpb_aes_xcbc aes_xcbc;
129 struct cop_symcpb_sha256 sha256;
130 struct cop_symcpb_sha512 sha512;
132 } __packed;
134 #define NX_CSB_VALID_BIT 0x80
136 /* co-processor status block */
137 struct cop_status_block {
138 u8 valid;
139 u8 crb_seq_number;
140 u8 completion_code;
141 u8 completion_extension;
142 u32 processed_byte_count;
143 u64 address;
144 } __packed;
146 /* Nest accelerator workbook section 4.4 */
147 struct nx_csbcpb {
148 unsigned char __rsvd[112];
149 struct cop_status_block csb;
150 struct cop_parameter_block cpb;
151 } __packed;
153 /* nx_csbcpb related definitions */
154 #define NX_MODE_AES_ECB 0
155 #define NX_MODE_AES_CBC 1
156 #define NX_MODE_AES_GMAC 2
157 #define NX_MODE_AES_GCA 3
158 #define NX_MODE_AES_GCM 4
159 #define NX_MODE_AES_CCA 5
160 #define NX_MODE_AES_CCM 6
161 #define NX_MODE_AES_CTR 7
162 #define NX_MODE_AES_XCBC_MAC 20
163 #define NX_MODE_SHA 0
164 #define NX_MODE_SHA_HMAC 1
165 #define NX_MODE_AES_CBC_HMAC_ETA 8
166 #define NX_MODE_AES_CBC_HMAC_ATE 9
167 #define NX_MODE_AES_CBC_HMAC_EAA 10
168 #define NX_MODE_AES_CTR_HMAC_ETA 12
169 #define NX_MODE_AES_CTR_HMAC_ATE 13
170 #define NX_MODE_AES_CTR_HMAC_EAA 14
172 #define NX_FDM_CI_FULL 0
173 #define NX_FDM_CI_FIRST 1
174 #define NX_FDM_CI_LAST 2
175 #define NX_FDM_CI_MIDDLE 3
177 #define NX_FDM_PR_NONE 0
178 #define NX_FDM_PR_PAD 1
180 #define NX_KS_AES_128 1
181 #define NX_KS_AES_192 2
182 #define NX_KS_AES_256 3
184 #define NX_DS_SHA256 2
185 #define NX_DS_SHA512 3
187 #define NX_FC_AES 0
188 #define NX_FC_SHA 2
189 #define NX_FC_AES_HMAC 6
191 #define NX_MAX_FC (NX_FC_AES_HMAC + 1)
192 #define NX_MAX_MODE (NX_MODE_AES_XCBC_MAC + 1)
194 #define HCOP_FC_AES NX_FC_AES
195 #define HCOP_FC_SHA NX_FC_SHA
196 #define HCOP_FC_AES_HMAC NX_FC_AES_HMAC
198 /* indices into the array of algorithm properties */
199 #define NX_PROPS_AES_128 0
200 #define NX_PROPS_AES_192 1
201 #define NX_PROPS_AES_256 2
202 #define NX_PROPS_SHA256 1
203 #define NX_PROPS_SHA512 2
205 #endif