2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2012 Sean Young <sean@mess.org>
11 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
13 * Dedicated to my daughter Matilda, without whose loving attention this
14 * driver would have been finished in half the time and with a fraction
18 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
19 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
25 * o Wake-On-CIR functionality
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License as published by
30 * the Free Software Foundation; either version 2 of the License, or
31 * (at your option) any later version.
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/pnp.h>
47 #include <linux/interrupt.h>
48 #include <linux/timer.h>
49 #include <linux/leds.h>
50 #include <linux/spinlock.h>
51 #include <linux/pci_ids.h>
53 #include <linux/bitrev.h>
54 #include <linux/slab.h>
55 #include <linux/wait.h>
56 #include <linux/sched.h>
57 #include <media/rc-core.h>
59 #define DRVNAME "winbond-cir"
61 /* CEIR Wake-Up Registers, relative to data->wbase */
62 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
63 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
64 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
65 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
66 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
67 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
68 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
69 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
70 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
71 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
73 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
74 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
75 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
76 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
77 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
78 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
80 /* SP3 Banked Registers, relative to data->sbase */
81 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
83 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
84 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
85 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
86 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
87 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
88 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
89 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
90 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
91 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
93 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
94 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
95 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
96 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
97 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
98 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
100 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
101 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
102 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
104 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
106 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
108 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
109 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
111 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
112 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
113 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
114 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
115 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
118 * Magic values follow
121 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
122 #define WBCIR_IRQ_NONE 0x00
123 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
124 #define WBCIR_IRQ_RX 0x01
125 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
126 #define WBCIR_IRQ_TX_LOW 0x02
127 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
128 #define WBCIR_IRQ_ERR 0x04
129 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
130 #define WBCIR_IRQ_TX_EMPTY 0x20
131 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
132 #define WBCIR_LED_ENABLE 0x80
133 /* RX data available bit for WBCIR_REG_SP3_LSR */
134 #define WBCIR_RX_AVAIL 0x01
135 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
136 #define WBCIR_RX_OVERRUN 0x02
137 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
138 #define WBCIR_TX_EOT 0x04
139 /* RX disable bit for WBCIR_REG_SP3_ASCR */
140 #define WBCIR_RX_DISABLE 0x20
141 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
142 #define WBCIR_TX_UNDERRUN 0x40
143 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
144 #define WBCIR_EXT_ENABLE 0x01
145 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
146 #define WBCIR_REGSEL_COMPARE 0x10
147 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
148 #define WBCIR_REGSEL_MASK 0x20
149 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
150 #define WBCIR_REG_ADDR0 0x00
151 /* Enable carrier counter */
152 #define WBCIR_CNTR_EN 0x01
153 /* Reset carrier counter */
154 #define WBCIR_CNTR_R 0x02
156 #define WBCIR_IRTX_INV 0x04
157 /* Receiver oversampling */
158 #define WBCIR_RX_T_OV 0x40
160 /* Valid banks for the SP3 UART */
172 /* Supported power-on IR Protocols */
173 enum wbcir_protocol
{
174 IR_PROTOCOL_RC5
= 0x0,
175 IR_PROTOCOL_NEC
= 0x1,
176 IR_PROTOCOL_RC6
= 0x2,
179 /* Possible states for IR reception */
181 WBCIR_RXSTATE_INACTIVE
= 0,
182 WBCIR_RXSTATE_ACTIVE
,
186 /* Possible states for IR transmission */
188 WBCIR_TXSTATE_INACTIVE
= 0,
189 WBCIR_TXSTATE_ACTIVE
,
194 #define WBCIR_NAME "Winbond CIR"
195 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
196 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
197 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
198 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
199 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
200 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
202 /* Per-device data */
206 struct led_classdev led
;
208 unsigned long wbase
; /* Wake-Up Baseaddr */
209 unsigned long ebase
; /* Enhanced Func. Baseaddr */
210 unsigned long sbase
; /* Serial Port Baseaddr */
211 unsigned int irq
; /* Serial Port IRQ */
215 enum wbcir_rxstate rxstate
;
216 int carrier_report_enabled
;
220 enum wbcir_txstate txstate
;
228 static enum wbcir_protocol protocol
= IR_PROTOCOL_RC6
;
229 module_param(protocol
, uint
, 0444);
230 MODULE_PARM_DESC(protocol
, "IR protocol to use for the power-on command "
231 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
233 static bool invert
; /* default = 0 */
234 module_param(invert
, bool, 0444);
235 MODULE_PARM_DESC(invert
, "Invert the signal from the IR receiver");
237 static bool txandrx
; /* default = 0 */
238 module_param(txandrx
, bool, 0444);
239 MODULE_PARM_DESC(txandrx
, "Allow simultaneous TX and RX");
241 static unsigned int wake_sc
= 0x800F040C;
242 module_param(wake_sc
, uint
, 0644);
243 MODULE_PARM_DESC(wake_sc
, "Scancode of the power-on IR command");
245 static unsigned int wake_rc6mode
= 6;
246 module_param(wake_rc6mode
, uint
, 0644);
247 MODULE_PARM_DESC(wake_rc6mode
, "RC6 mode for the power-on command "
248 "(0 = 0, 6 = 6A, default)");
252 /*****************************************************************************
256 *****************************************************************************/
258 /* Caller needs to hold wbcir_lock */
260 wbcir_set_bits(unsigned long addr
, u8 bits
, u8 mask
)
265 val
= ((val
& ~mask
) | (bits
& mask
));
269 /* Selects the register bank for the serial port */
271 wbcir_select_bank(struct wbcir_data
*data
, enum wbcir_bank bank
)
273 outb(bank
, data
->sbase
+ WBCIR_REG_SP3_BSR
);
277 wbcir_set_irqmask(struct wbcir_data
*data
, u8 irqmask
)
279 if (data
->irqmask
== irqmask
)
282 wbcir_select_bank(data
, WBCIR_BANK_0
);
283 outb(irqmask
, data
->sbase
+ WBCIR_REG_SP3_IER
);
284 data
->irqmask
= irqmask
;
287 static enum led_brightness
288 wbcir_led_brightness_get(struct led_classdev
*led_cdev
)
290 struct wbcir_data
*data
= container_of(led_cdev
,
294 if (inb(data
->ebase
+ WBCIR_REG_ECEIR_CTS
) & WBCIR_LED_ENABLE
)
301 wbcir_led_brightness_set(struct led_classdev
*led_cdev
,
302 enum led_brightness brightness
)
304 struct wbcir_data
*data
= container_of(led_cdev
,
308 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CTS
,
309 brightness
== LED_OFF
? 0x00 : WBCIR_LED_ENABLE
,
313 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
315 wbcir_to_rc6cells(u8 val
)
321 for (i
= 0; i
< 4; i
++) {
323 coded
|= 0x02 << (i
* 2);
325 coded
|= 0x01 << (i
* 2);
332 /*****************************************************************************
334 * INTERRUPT FUNCTIONS
336 *****************************************************************************/
339 wbcir_carrier_report(struct wbcir_data
*data
)
341 unsigned counter
= inb(data
->ebase
+ WBCIR_REG_ECEIR_CNT_LO
) |
342 inb(data
->ebase
+ WBCIR_REG_ECEIR_CNT_HI
) << 8;
344 if (counter
> 0 && counter
< 0xffff) {
345 DEFINE_IR_RAW_EVENT(ev
);
347 ev
.carrier_report
= 1;
348 ev
.carrier
= DIV_ROUND_CLOSEST(counter
* 1000000u,
349 data
->pulse_duration
);
351 ir_raw_event_store(data
->dev
, &ev
);
354 /* reset and restart the counter */
355 data
->pulse_duration
= 0;
356 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_R
,
357 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
358 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_EN
,
359 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
363 wbcir_idle_rx(struct rc_dev
*dev
, bool idle
)
365 struct wbcir_data
*data
= dev
->priv
;
367 if (!idle
&& data
->rxstate
== WBCIR_RXSTATE_INACTIVE
)
368 data
->rxstate
= WBCIR_RXSTATE_ACTIVE
;
370 if (idle
&& data
->rxstate
!= WBCIR_RXSTATE_INACTIVE
) {
371 data
->rxstate
= WBCIR_RXSTATE_INACTIVE
;
373 if (data
->carrier_report_enabled
)
374 wbcir_carrier_report(data
);
376 /* Tell hardware to go idle by setting RXINACTIVE */
377 outb(WBCIR_RX_DISABLE
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
382 wbcir_irq_rx(struct wbcir_data
*data
, struct pnp_dev
*device
)
385 DEFINE_IR_RAW_EVENT(rawir
);
388 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
389 while (inb(data
->sbase
+ WBCIR_REG_SP3_LSR
) & WBCIR_RX_AVAIL
) {
390 irdata
= inb(data
->sbase
+ WBCIR_REG_SP3_RXDATA
);
391 if (data
->rxstate
== WBCIR_RXSTATE_ERROR
)
394 duration
= ((irdata
& 0x7F) + 1) *
395 (data
->carrier_report_enabled
? 2 : 10);
396 rawir
.pulse
= irdata
& 0x80 ? false : true;
397 rawir
.duration
= US_TO_NS(duration
);
400 data
->pulse_duration
+= duration
;
402 ir_raw_event_store_with_filter(data
->dev
, &rawir
);
405 ir_raw_event_handle(data
->dev
);
409 wbcir_irq_tx(struct wbcir_data
*data
)
419 switch (data
->txstate
) {
420 case WBCIR_TXSTATE_INACTIVE
:
424 case WBCIR_TXSTATE_ACTIVE
:
425 /* TX FIFO low (3 bytes or less) */
428 case WBCIR_TXSTATE_ERROR
:
436 * TX data is run-length coded in bytes: YXXXXXXX
437 * Y = space (1) or pulse (0)
438 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
440 for (used
= 0; used
< space
&& data
->txoff
!= data
->txlen
; used
++) {
441 if (data
->txbuf
[data
->txoff
] == 0) {
445 byte
= min((u32
)0x80, data
->txbuf
[data
->txoff
]);
446 data
->txbuf
[data
->txoff
] -= byte
;
448 byte
|= (data
->txoff
% 2 ? 0x80 : 0x00); /* pulse/space */
452 while (data
->txbuf
[data
->txoff
] == 0 && data
->txoff
!= data
->txlen
)
457 if (data
->txstate
== WBCIR_TXSTATE_ERROR
)
458 /* Clear TX underrun bit */
459 outb(WBCIR_TX_UNDERRUN
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
460 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
);
463 data
->txstate
= WBCIR_TXSTATE_INACTIVE
;
464 } else if (data
->txoff
== data
->txlen
) {
465 /* At the end of transmission, tell the hw before last byte */
466 outsb(data
->sbase
+ WBCIR_REG_SP3_TXDATA
, bytes
, used
- 1);
467 outb(WBCIR_TX_EOT
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
468 outb(bytes
[used
- 1], data
->sbase
+ WBCIR_REG_SP3_TXDATA
);
469 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
|
472 /* More data to follow... */
473 outsb(data
->sbase
+ WBCIR_REG_SP3_RXDATA
, bytes
, used
);
474 if (data
->txstate
== WBCIR_TXSTATE_INACTIVE
) {
475 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
|
477 data
->txstate
= WBCIR_TXSTATE_ACTIVE
;
483 wbcir_irq_handler(int irqno
, void *cookie
)
485 struct pnp_dev
*device
= cookie
;
486 struct wbcir_data
*data
= pnp_get_drvdata(device
);
490 spin_lock_irqsave(&data
->spinlock
, flags
);
491 wbcir_select_bank(data
, WBCIR_BANK_0
);
492 status
= inb(data
->sbase
+ WBCIR_REG_SP3_EIR
);
493 status
&= data
->irqmask
;
496 spin_unlock_irqrestore(&data
->spinlock
, flags
);
500 if (status
& WBCIR_IRQ_ERR
) {
501 /* RX overflow? (read clears bit) */
502 if (inb(data
->sbase
+ WBCIR_REG_SP3_LSR
) & WBCIR_RX_OVERRUN
) {
503 data
->rxstate
= WBCIR_RXSTATE_ERROR
;
504 ir_raw_event_reset(data
->dev
);
508 if (inb(data
->sbase
+ WBCIR_REG_SP3_ASCR
) & WBCIR_TX_UNDERRUN
)
509 data
->txstate
= WBCIR_TXSTATE_ERROR
;
512 if (status
& WBCIR_IRQ_RX
)
513 wbcir_irq_rx(data
, device
);
515 if (status
& (WBCIR_IRQ_TX_LOW
| WBCIR_IRQ_TX_EMPTY
))
518 spin_unlock_irqrestore(&data
->spinlock
, flags
);
522 /*****************************************************************************
524 * RC-CORE INTERFACE FUNCTIONS
526 *****************************************************************************/
529 wbcir_set_carrier_report(struct rc_dev
*dev
, int enable
)
531 struct wbcir_data
*data
= dev
->priv
;
534 spin_lock_irqsave(&data
->spinlock
, flags
);
536 if (data
->carrier_report_enabled
== enable
) {
537 spin_unlock_irqrestore(&data
->spinlock
, flags
);
541 data
->pulse_duration
= 0;
542 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_R
,
543 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
545 if (enable
&& data
->dev
->idle
)
546 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
,
547 WBCIR_CNTR_EN
, WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
549 /* Set a higher sampling resolution if carrier reports are enabled */
550 wbcir_select_bank(data
, WBCIR_BANK_2
);
551 data
->dev
->rx_resolution
= US_TO_NS(enable
? 2 : 10);
552 outb(enable
? 0x03 : 0x0f, data
->sbase
+ WBCIR_REG_SP3_BGDL
);
553 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_BGDH
);
555 /* Enable oversampling if carrier reports are enabled */
556 wbcir_select_bank(data
, WBCIR_BANK_7
);
557 wbcir_set_bits(data
->sbase
+ WBCIR_REG_SP3_RCCFG
,
558 enable
? WBCIR_RX_T_OV
: 0, WBCIR_RX_T_OV
);
560 data
->carrier_report_enabled
= enable
;
561 spin_unlock_irqrestore(&data
->spinlock
, flags
);
567 wbcir_txcarrier(struct rc_dev
*dev
, u32 carrier
)
569 struct wbcir_data
*data
= dev
->priv
;
574 freq
= DIV_ROUND_CLOSEST(carrier
, 1000);
575 if (freq
< 30 || freq
> 60)
595 spin_lock_irqsave(&data
->spinlock
, flags
);
596 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
597 spin_unlock_irqrestore(&data
->spinlock
, flags
);
601 if (data
->txcarrier
!= freq
) {
602 wbcir_select_bank(data
, WBCIR_BANK_7
);
603 wbcir_set_bits(data
->sbase
+ WBCIR_REG_SP3_IRTXMC
, val
, 0x1F);
604 data
->txcarrier
= freq
;
607 spin_unlock_irqrestore(&data
->spinlock
, flags
);
612 wbcir_txmask(struct rc_dev
*dev
, u32 mask
)
614 struct wbcir_data
*data
= dev
->priv
;
618 /* return the number of transmitters */
622 /* Four outputs, only one output can be enabled at a time */
640 spin_lock_irqsave(&data
->spinlock
, flags
);
641 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
642 spin_unlock_irqrestore(&data
->spinlock
, flags
);
646 if (data
->txmask
!= mask
) {
647 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CTS
, val
, 0x0c);
651 spin_unlock_irqrestore(&data
->spinlock
, flags
);
656 wbcir_tx(struct rc_dev
*dev
, unsigned *b
, unsigned count
)
658 struct wbcir_data
*data
= dev
->priv
;
663 buf
= kmalloc(count
* sizeof(*b
), GFP_KERNEL
);
667 /* Convert values to multiples of 10us */
668 for (i
= 0; i
< count
; i
++)
669 buf
[i
] = DIV_ROUND_CLOSEST(b
[i
], 10);
671 /* Not sure if this is possible, but better safe than sorry */
672 spin_lock_irqsave(&data
->spinlock
, flags
);
673 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
674 spin_unlock_irqrestore(&data
->spinlock
, flags
);
679 /* Fill the TX fifo once, the irq handler will do the rest */
686 spin_unlock_irqrestore(&data
->spinlock
, flags
);
690 /*****************************************************************************
692 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
694 *****************************************************************************/
697 wbcir_shutdown(struct pnp_dev
*device
)
699 struct device
*dev
= &device
->dev
;
700 struct wbcir_data
*data
= pnp_get_drvdata(device
);
707 memset(match
, 0, sizeof(match
));
708 memset(mask
, 0, sizeof(mask
));
710 if (wake_sc
== INVALID_SCANCODE
|| !device_may_wakeup(dev
)) {
716 case IR_PROTOCOL_RC5
:
717 if (wake_sc
> 0xFFF) {
719 dev_err(dev
, "RC5 - Invalid wake scancode\n");
723 /* Mask = 13 bits, ex toggle */
727 match
[0] = (wake_sc
& 0x003F); /* 6 command bits */
728 match
[0] |= (wake_sc
& 0x0180) >> 1; /* 2 address bits */
729 match
[1] = (wake_sc
& 0x0E00) >> 9; /* 3 address bits */
730 if (!(wake_sc
& 0x0040)) /* 2nd start bit */
735 case IR_PROTOCOL_NEC
:
736 if (wake_sc
> 0xFFFFFF) {
738 dev_err(dev
, "NEC - Invalid wake scancode\n");
742 mask
[0] = mask
[1] = mask
[2] = mask
[3] = 0xFF;
744 match
[1] = bitrev8((wake_sc
& 0xFF));
745 match
[0] = ~match
[1];
747 match
[3] = bitrev8((wake_sc
& 0xFF00) >> 8);
748 if (wake_sc
> 0xFFFF)
749 match
[2] = bitrev8((wake_sc
& 0xFF0000) >> 16);
751 match
[2] = ~match
[3];
755 case IR_PROTOCOL_RC6
:
757 if (wake_rc6mode
== 0) {
758 if (wake_sc
> 0xFFFF) {
760 dev_err(dev
, "RC6 - Invalid wake scancode\n");
765 match
[0] = wbcir_to_rc6cells(wake_sc
>> 0);
767 match
[1] = wbcir_to_rc6cells(wake_sc
>> 4);
771 match
[2] = wbcir_to_rc6cells(wake_sc
>> 8);
773 match
[3] = wbcir_to_rc6cells(wake_sc
>> 12);
777 match
[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
779 match
[5] = 0x09; /* start bit = 1, mode2 = 0 */
784 } else if (wake_rc6mode
== 6) {
788 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 0);
790 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 4);
793 /* Address + Toggle */
794 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 8);
796 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 12);
799 /* Customer bits 7 - 0 */
800 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 16);
802 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 20);
805 if (wake_sc
& 0x80000000) {
806 /* Customer range bit and bits 15 - 8 */
807 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 24);
809 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 28);
812 } else if (wake_sc
<= 0x007FFFFF) {
816 dev_err(dev
, "RC6 - Invalid wake scancode\n");
821 match
[i
] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
823 match
[i
] = 0x0A; /* start bit = 1, mode2 = 1 */
828 dev_err(dev
, "RC6 - Invalid wake mode\n");
840 /* Set compare and compare mask */
841 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_INDEX
,
842 WBCIR_REGSEL_COMPARE
| WBCIR_REG_ADDR0
,
844 outsb(data
->wbase
+ WBCIR_REG_WCEIR_DATA
, match
, 11);
845 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_INDEX
,
846 WBCIR_REGSEL_MASK
| WBCIR_REG_ADDR0
,
848 outsb(data
->wbase
+ WBCIR_REG_WCEIR_DATA
, mask
, 11);
850 /* RC6 Compare String Len */
851 outb(rc6_csl
, data
->wbase
+ WBCIR_REG_WCEIR_CSL
);
853 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
854 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
856 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
857 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x01, 0x07);
860 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, 0x01, 0x01);
863 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
864 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
867 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, 0x00, 0x01);
871 * ACPI will set the HW disable bit for SP3 which means that the
872 * output signals are left in an undefined state which may cause
873 * spurious interrupts which we need to ignore until the hardware
876 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
877 disable_irq(data
->irq
);
881 wbcir_suspend(struct pnp_dev
*device
, pm_message_t state
)
883 struct wbcir_data
*data
= pnp_get_drvdata(device
);
884 led_classdev_suspend(&data
->led
);
885 wbcir_shutdown(device
);
890 wbcir_init_hw(struct wbcir_data
*data
)
894 /* Disable interrupts */
895 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
897 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
901 outb(tmp
, data
->wbase
+ WBCIR_REG_WCEIR_CTL
);
903 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
904 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
906 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
907 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
909 /* Set RC5 cell time to correspond to 36 kHz */
910 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CFG1
, 0x4A, 0x7F);
914 outb(WBCIR_IRTX_INV
, data
->ebase
+ WBCIR_REG_ECEIR_CCTL
);
916 outb(0x00, data
->ebase
+ WBCIR_REG_ECEIR_CCTL
);
919 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
920 * set SP3_IRRX_SW to binary 01, helpfully not documented
922 outb(0x10, data
->ebase
+ WBCIR_REG_ECEIR_CTS
);
925 /* Enable extended mode */
926 wbcir_select_bank(data
, WBCIR_BANK_2
);
927 outb(WBCIR_EXT_ENABLE
, data
->sbase
+ WBCIR_REG_SP3_EXCR1
);
930 * Configure baud generator, IR data will be sampled at
931 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
933 * The ECIR registers include a flag to change the
934 * 24Mhz clock freq to 48Mhz.
936 * It's not documented in the specs, but fifo levels
937 * other than 16 seems to be unsupported.
940 /* prescaler 1.0, tx/rx fifo lvl 16 */
941 outb(0x30, data
->sbase
+ WBCIR_REG_SP3_EXCR2
);
943 /* Set baud divisor to sample every 10 us */
944 outb(0x0f, data
->sbase
+ WBCIR_REG_SP3_BGDL
);
945 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_BGDH
);
948 wbcir_select_bank(data
, WBCIR_BANK_0
);
949 outb(0xC0, data
->sbase
+ WBCIR_REG_SP3_MCR
);
950 inb(data
->sbase
+ WBCIR_REG_SP3_LSR
); /* Clear LSR */
951 inb(data
->sbase
+ WBCIR_REG_SP3_MSR
); /* Clear MSR */
953 /* Disable RX demod, enable run-length enc/dec, set freq span */
954 wbcir_select_bank(data
, WBCIR_BANK_7
);
955 outb(0x90, data
->sbase
+ WBCIR_REG_SP3_RCCFG
);
958 wbcir_select_bank(data
, WBCIR_BANK_4
);
959 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_IRCR1
);
961 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
962 wbcir_select_bank(data
, WBCIR_BANK_5
);
963 outb(txandrx
? 0x03 : 0x02, data
->sbase
+ WBCIR_REG_SP3_IRCR2
);
966 wbcir_select_bank(data
, WBCIR_BANK_6
);
967 outb(0x20, data
->sbase
+ WBCIR_REG_SP3_IRCR3
);
969 /* Set RX demodulation freq, not really used */
970 wbcir_select_bank(data
, WBCIR_BANK_7
);
971 outb(0xF2, data
->sbase
+ WBCIR_REG_SP3_IRRXDC
);
973 /* Set TX modulation, 36kHz, 7us pulse width */
974 outb(0x69, data
->sbase
+ WBCIR_REG_SP3_IRTXMC
);
975 data
->txcarrier
= 36000;
977 /* Set invert and pin direction */
979 outb(0x10, data
->sbase
+ WBCIR_REG_SP3_IRCFG4
);
981 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_IRCFG4
);
983 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
984 wbcir_select_bank(data
, WBCIR_BANK_0
);
985 outb(0x97, data
->sbase
+ WBCIR_REG_SP3_FCR
);
987 /* Clear AUX status bits */
988 outb(0xE0, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
991 data
->rxstate
= WBCIR_RXSTATE_INACTIVE
;
992 ir_raw_event_reset(data
->dev
);
993 ir_raw_event_set_idle(data
->dev
, true);
996 if (data
->txstate
== WBCIR_TXSTATE_ACTIVE
) {
999 data
->txstate
= WBCIR_TXSTATE_INACTIVE
;
1002 /* Enable interrupts */
1003 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
);
1007 wbcir_resume(struct pnp_dev
*device
)
1009 struct wbcir_data
*data
= pnp_get_drvdata(device
);
1011 wbcir_init_hw(data
);
1012 enable_irq(data
->irq
);
1013 led_classdev_resume(&data
->led
);
1019 wbcir_probe(struct pnp_dev
*device
, const struct pnp_device_id
*dev_id
)
1021 struct device
*dev
= &device
->dev
;
1022 struct wbcir_data
*data
;
1025 if (!(pnp_port_len(device
, 0) == EHFUNC_IOMEM_LEN
&&
1026 pnp_port_len(device
, 1) == WAKEUP_IOMEM_LEN
&&
1027 pnp_port_len(device
, 2) == SP_IOMEM_LEN
)) {
1028 dev_err(dev
, "Invalid resources\n");
1032 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1038 pnp_set_drvdata(device
, data
);
1040 spin_lock_init(&data
->spinlock
);
1041 data
->ebase
= pnp_port_start(device
, 0);
1042 data
->wbase
= pnp_port_start(device
, 1);
1043 data
->sbase
= pnp_port_start(device
, 2);
1044 data
->irq
= pnp_irq(device
, 0);
1046 if (data
->wbase
== 0 || data
->ebase
== 0 ||
1047 data
->sbase
== 0 || data
->irq
== 0) {
1049 dev_err(dev
, "Invalid resources\n");
1050 goto exit_free_data
;
1053 dev_dbg(&device
->dev
, "Found device "
1054 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1055 data
->wbase
, data
->ebase
, data
->sbase
, data
->irq
);
1057 data
->led
.name
= "cir::activity";
1058 data
->led
.default_trigger
= "rc-feedback";
1059 data
->led
.brightness_set
= wbcir_led_brightness_set
;
1060 data
->led
.brightness_get
= wbcir_led_brightness_get
;
1061 err
= led_classdev_register(&device
->dev
, &data
->led
);
1063 goto exit_free_data
;
1065 data
->dev
= rc_allocate_device();
1068 goto exit_unregister_led
;
1071 data
->dev
->driver_type
= RC_DRIVER_IR_RAW
;
1072 data
->dev
->driver_name
= DRVNAME
;
1073 data
->dev
->input_name
= WBCIR_NAME
;
1074 data
->dev
->input_phys
= "wbcir/cir0";
1075 data
->dev
->input_id
.bustype
= BUS_HOST
;
1076 data
->dev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND
;
1077 data
->dev
->input_id
.product
= WBCIR_ID_FAMILY
;
1078 data
->dev
->input_id
.version
= WBCIR_ID_CHIP
;
1079 data
->dev
->map_name
= RC_MAP_RC6_MCE
;
1080 data
->dev
->s_idle
= wbcir_idle_rx
;
1081 data
->dev
->s_carrier_report
= wbcir_set_carrier_report
;
1082 data
->dev
->s_tx_mask
= wbcir_txmask
;
1083 data
->dev
->s_tx_carrier
= wbcir_txcarrier
;
1084 data
->dev
->tx_ir
= wbcir_tx
;
1085 data
->dev
->priv
= data
;
1086 data
->dev
->dev
.parent
= &device
->dev
;
1087 data
->dev
->timeout
= MS_TO_NS(100);
1088 data
->dev
->rx_resolution
= US_TO_NS(2);
1089 data
->dev
->allowed_protocols
= RC_BIT_ALL
;
1091 err
= rc_register_device(data
->dev
);
1095 if (!request_region(data
->wbase
, WAKEUP_IOMEM_LEN
, DRVNAME
)) {
1096 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1097 data
->wbase
, data
->wbase
+ WAKEUP_IOMEM_LEN
- 1);
1099 goto exit_unregister_device
;
1102 if (!request_region(data
->ebase
, EHFUNC_IOMEM_LEN
, DRVNAME
)) {
1103 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1104 data
->ebase
, data
->ebase
+ EHFUNC_IOMEM_LEN
- 1);
1106 goto exit_release_wbase
;
1109 if (!request_region(data
->sbase
, SP_IOMEM_LEN
, DRVNAME
)) {
1110 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1111 data
->sbase
, data
->sbase
+ SP_IOMEM_LEN
- 1);
1113 goto exit_release_ebase
;
1116 err
= request_irq(data
->irq
, wbcir_irq_handler
,
1117 0, DRVNAME
, device
);
1119 dev_err(dev
, "Failed to claim IRQ %u\n", data
->irq
);
1121 goto exit_release_sbase
;
1124 device_init_wakeup(&device
->dev
, 1);
1126 wbcir_init_hw(data
);
1131 release_region(data
->sbase
, SP_IOMEM_LEN
);
1133 release_region(data
->ebase
, EHFUNC_IOMEM_LEN
);
1135 release_region(data
->wbase
, WAKEUP_IOMEM_LEN
);
1136 exit_unregister_device
:
1137 rc_unregister_device(data
->dev
);
1140 rc_free_device(data
->dev
);
1141 exit_unregister_led
:
1142 led_classdev_unregister(&data
->led
);
1145 pnp_set_drvdata(device
, NULL
);
1151 wbcir_remove(struct pnp_dev
*device
)
1153 struct wbcir_data
*data
= pnp_get_drvdata(device
);
1155 /* Disable interrupts */
1156 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
1157 free_irq(data
->irq
, device
);
1159 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1160 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
1163 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, 0x00, 0x01);
1165 /* Clear BUFF_EN, END_EN, MATCH_EN */
1166 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
1168 rc_unregister_device(data
->dev
);
1170 led_classdev_unregister(&data
->led
);
1172 /* This is ok since &data->led isn't actually used */
1173 wbcir_led_brightness_set(&data
->led
, LED_OFF
);
1175 release_region(data
->wbase
, WAKEUP_IOMEM_LEN
);
1176 release_region(data
->ebase
, EHFUNC_IOMEM_LEN
);
1177 release_region(data
->sbase
, SP_IOMEM_LEN
);
1181 pnp_set_drvdata(device
, NULL
);
1184 static const struct pnp_device_id wbcir_ids
[] = {
1188 MODULE_DEVICE_TABLE(pnp
, wbcir_ids
);
1190 static struct pnp_driver wbcir_driver
= {
1192 .id_table
= wbcir_ids
,
1193 .probe
= wbcir_probe
,
1194 .remove
= wbcir_remove
,
1195 .suspend
= wbcir_suspend
,
1196 .resume
= wbcir_resume
,
1197 .shutdown
= wbcir_shutdown
1206 case IR_PROTOCOL_RC5
:
1207 case IR_PROTOCOL_NEC
:
1208 case IR_PROTOCOL_RC6
:
1211 pr_err("Invalid power-on protocol\n");
1214 ret
= pnp_register_driver(&wbcir_driver
);
1216 pr_err("Unable to register driver\n");
1224 pnp_unregister_driver(&wbcir_driver
);
1227 module_init(wbcir_init
);
1228 module_exit(wbcir_exit
);
1230 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1231 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1232 MODULE_LICENSE("GPL");