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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / scsi / mpt3sas / mpi / mpi2.h
bloba9a659fc2812a422dff8c5f1d923733e6cabf4c0
1 /*
2 * Copyright 2000-2015 Avago Technologies. All rights reserved.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
11 * mpi2.h Version: 02.00.42
12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
94 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
95 * 11-18-14 02.00.36 Updated copyright information.
96 * Bumped MPI2_HEADER_VERSION_UNIT.
97 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
98 * Added Scratchpad registers to
99 * MPI2_SYSTEM_INTERFACE_REGS.
100 * Added MPI2_DIAG_SBR_RELOAD.
101 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
102 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT.
103 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
105 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
106 * --------------------------------------------------------------------------
107 */
108
109 #ifndef MPI2_H
110 #define MPI2_H
111
112 /*****************************************************************************
113 *
114 * MPI Version Definitions
115 *
116 *****************************************************************************/
117
118 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
119 #define MPI2_VERSION_MAJOR_SHIFT (8)
120 #define MPI2_VERSION_MINOR_MASK (0x00FF)
121 #define MPI2_VERSION_MINOR_SHIFT (0)
122
123 /*major version for all MPI v2.x */
124 #define MPI2_VERSION_MAJOR (0x02)
125
126 /*minor version for MPI v2.0 compatible products */
127 #define MPI2_VERSION_MINOR (0x00)
128 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
129 MPI2_VERSION_MINOR)
130 #define MPI2_VERSION_02_00 (0x0200)
131
132 /*minor version for MPI v2.5 compatible products */
133 #define MPI25_VERSION_MINOR (0x05)
134 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
135 MPI25_VERSION_MINOR)
136 #define MPI2_VERSION_02_05 (0x0205)
137
138 /*minor version for MPI v2.6 compatible products */
139 #define MPI26_VERSION_MINOR (0x06)
140 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
141 MPI26_VERSION_MINOR)
142 #define MPI2_VERSION_02_06 (0x0206)
143
144 /*Unit and Dev versioning for this MPI header set */
145 #define MPI2_HEADER_VERSION_UNIT (0x2A)
146 #define MPI2_HEADER_VERSION_DEV (0x00)
147 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
148 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
149 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
150 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
151 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
152 MPI2_HEADER_VERSION_DEV)
153
154 /*****************************************************************************
155 *
156 * IOC State Definitions
157 *
158 *****************************************************************************/
159
160 #define MPI2_IOC_STATE_RESET (0x00000000)
161 #define MPI2_IOC_STATE_READY (0x10000000)
162 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
163 #define MPI2_IOC_STATE_FAULT (0x40000000)
164
165 #define MPI2_IOC_STATE_MASK (0xF0000000)
166 #define MPI2_IOC_STATE_SHIFT (28)
167
168 /*Fault state range for prodcut specific codes */
169 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
170 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
171
172 /*****************************************************************************
173 *
174 * System Interface Register Definitions
175 *
176 *****************************************************************************/
177
178 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
179 U32 Doorbell; /*0x00 */
180 U32 WriteSequence; /*0x04 */
181 U32 HostDiagnostic; /*0x08 */
182 U32 Reserved1; /*0x0C */
183 U32 DiagRWData; /*0x10 */
184 U32 DiagRWAddressLow; /*0x14 */
185 U32 DiagRWAddressHigh; /*0x18 */
186 U32 Reserved2[5]; /*0x1C */
187 U32 HostInterruptStatus; /*0x30 */
188 U32 HostInterruptMask; /*0x34 */
189 U32 DCRData; /*0x38 */
190 U32 DCRAddress; /*0x3C */
191 U32 Reserved3[2]; /*0x40 */
192 U32 ReplyFreeHostIndex; /*0x48 */
193 U32 Reserved4[8]; /*0x4C */
194 U32 ReplyPostHostIndex; /*0x6C */
195 U32 Reserved5; /*0x70 */
196 U32 HCBSize; /*0x74 */
197 U32 HCBAddressLow; /*0x78 */
198 U32 HCBAddressHigh; /*0x7C */
199 U32 Reserved6[12]; /*0x80 */
200 U32 Scratchpad[4]; /*0xB0 */
201 U32 RequestDescriptorPostLow; /*0xC0 */
202 U32 RequestDescriptorPostHigh; /*0xC4 */
203 U32 AtomicRequestDescriptorPost;/*0xC8 */
204 U32 Reserved7[13]; /*0xCC */
205 } MPI2_SYSTEM_INTERFACE_REGS,
206 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
207 Mpi2SystemInterfaceRegs_t,
208 *pMpi2SystemInterfaceRegs_t;
209
210 /*
211 *Defines for working with the Doorbell register.
212 */
213 #define MPI2_DOORBELL_OFFSET (0x00000000)
214
215 /*IOC --> System values */
216 #define MPI2_DOORBELL_USED (0x08000000)
217 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
218 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
219 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
220 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
221
222 /*System --> IOC values */
223 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
224 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
225 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
226 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
227
228 /*
229 *Defines for the WriteSequence register
230 */
231 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
232 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
233 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
234 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
235 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
236 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
237 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
238 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
239 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
240
241 /*
242 *Defines for the HostDiagnostic register
243 */
244 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
245
246 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
247
248 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
249 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
250 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
251
252 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
253 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
254 #define MPI2_DIAG_HCB_MODE (0x00000100)
255 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
256 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
257 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
258 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
259 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
260 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
261
262 /*
263 *Offsets for DiagRWData and address
264 */
265 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
266 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
267 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
268
269 /*
270 *Defines for the HostInterruptStatus register
271 */
272 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
273 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
274 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
275 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
276 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
277 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
278 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
279
280 /*
281 *Defines for the HostInterruptMask register
282 */
283 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
284 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
285 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
286 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
287 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
288 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
289
290 /*
291 *Offsets for DCRData and address
292 */
293 #define MPI2_DCR_DATA_OFFSET (0x00000038)
294 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
295
296 /*
297 *Offset for the Reply Free Queue
298 */
299 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
300
301 /*
302 *Defines for the Reply Descriptor Post Queue
303 */
304 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
305 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
306 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
307 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
308 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
309
310
311 /*
312 *Defines for the HCBSize and address
313 */
314 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
315 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
316 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
317
318 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
319 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
320
321 /*
322 *Offsets for the Scratchpad registers
323 */
324 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
325 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
326 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
327 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
328
329 /*
330 *Offsets for the Request Descriptor Post Queue
331 */
332 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
333 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
334 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
335
336 /*Hard Reset delay timings */
337 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
338 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
339 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
340
341 /*****************************************************************************
342 *
343 * Message Descriptors
344 *
345 *****************************************************************************/
346
347 /*Request Descriptors */
348
349 /*Default Request Descriptor */
350 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
351 U8 RequestFlags; /*0x00 */
352 U8 MSIxIndex; /*0x01 */
353 U16 SMID; /*0x02 */
354 U16 LMID; /*0x04 */
355 U16 DescriptorTypeDependent; /*0x06 */
356 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
357 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
358 Mpi2DefaultRequestDescriptor_t,
359 *pMpi2DefaultRequestDescriptor_t;
360
361 /*defines for the RequestFlags field */
362 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
363 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
364 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
365 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
366 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
367 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
368 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
369 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
370
371 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
372
373 /*High Priority Request Descriptor */
374 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
375 U8 RequestFlags; /*0x00 */
376 U8 MSIxIndex; /*0x01 */
377 U16 SMID; /*0x02 */
378 U16 LMID; /*0x04 */
379 U16 Reserved1; /*0x06 */
380 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
381 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
382 Mpi2HighPriorityRequestDescriptor_t,
383 *pMpi2HighPriorityRequestDescriptor_t;
384
385 /*SCSI IO Request Descriptor */
386 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
387 U8 RequestFlags; /*0x00 */
388 U8 MSIxIndex; /*0x01 */
389 U16 SMID; /*0x02 */
390 U16 LMID; /*0x04 */
391 U16 DevHandle; /*0x06 */
392 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
393 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
394 Mpi2SCSIIORequestDescriptor_t,
395 *pMpi2SCSIIORequestDescriptor_t;
396
397 /*SCSI Target Request Descriptor */
398 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
399 U8 RequestFlags; /*0x00 */
400 U8 MSIxIndex; /*0x01 */
401 U16 SMID; /*0x02 */
402 U16 LMID; /*0x04 */
403 U16 IoIndex; /*0x06 */
404 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
405 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
406 Mpi2SCSITargetRequestDescriptor_t,
407 *pMpi2SCSITargetRequestDescriptor_t;
408
409 /*RAID Accelerator Request Descriptor */
410 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
411 U8 RequestFlags; /*0x00 */
412 U8 MSIxIndex; /*0x01 */
413 U16 SMID; /*0x02 */
414 U16 LMID; /*0x04 */
415 U16 Reserved; /*0x06 */
416 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
417 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
418 Mpi2RAIDAcceleratorRequestDescriptor_t,
419 *pMpi2RAIDAcceleratorRequestDescriptor_t;
420
421 /*Fast Path SCSI IO Request Descriptor */
422 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
423 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
424 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
425 Mpi25FastPathSCSIIORequestDescriptor_t,
426 *pMpi25FastPathSCSIIORequestDescriptor_t;
427
428 /*union of Request Descriptors */
429 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
430 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
431 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
432 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
433 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
434 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
435 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
436 U64 Words;
437 } MPI2_REQUEST_DESCRIPTOR_UNION,
438 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
439 Mpi2RequestDescriptorUnion_t,
440 *pMpi2RequestDescriptorUnion_t;
441
442 /*Atomic Request Descriptors */
443
444 /*
445 * All Atomic Request Descriptors have the same format, so the following
446 * structure is used for all Atomic Request Descriptors:
447 * Atomic Default Request Descriptor
448 * Atomic High Priority Request Descriptor
449 * Atomic SCSI IO Request Descriptor
450 * Atomic SCSI Target Request Descriptor
451 * Atomic RAID Accelerator Request Descriptor
452 * Atomic Fast Path SCSI IO Request Descriptor
453 */
454
455 /*Atomic Request Descriptor */
456 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
457 U8 RequestFlags; /* 0x00 */
458 U8 MSIxIndex; /* 0x01 */
459 U16 SMID; /* 0x02 */
460 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
461 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
462 Mpi26AtomicRequestDescriptor_t,
463 *pMpi26AtomicRequestDescriptor_t;
464
465 /*for the RequestFlags field, use the same
466 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
467 */
468
469 /*Reply Descriptors */
470
471 /*Default Reply Descriptor */
472 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
473 U8 ReplyFlags; /*0x00 */
474 U8 MSIxIndex; /*0x01 */
475 U16 DescriptorTypeDependent1; /*0x02 */
476 U32 DescriptorTypeDependent2; /*0x04 */
477 } MPI2_DEFAULT_REPLY_DESCRIPTOR,
478 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
479 Mpi2DefaultReplyDescriptor_t,
480 *pMpi2DefaultReplyDescriptor_t;
481
482 /*defines for the ReplyFlags field */
483 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
484 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
485 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
486 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
487 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
488 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
489 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
490 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
491
492 /*values for marking a reply descriptor as unused */
493 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
494 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
495
496 /*Address Reply Descriptor */
497 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
498 U8 ReplyFlags; /*0x00 */
499 U8 MSIxIndex; /*0x01 */
500 U16 SMID; /*0x02 */
501 U32 ReplyFrameAddress; /*0x04 */
502 } MPI2_ADDRESS_REPLY_DESCRIPTOR,
503 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
504 Mpi2AddressReplyDescriptor_t,
505 *pMpi2AddressReplyDescriptor_t;
506
507 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
508
509 /*SCSI IO Success Reply Descriptor */
510 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
511 U8 ReplyFlags; /*0x00 */
512 U8 MSIxIndex; /*0x01 */
513 U16 SMID; /*0x02 */
514 U16 TaskTag; /*0x04 */
515 U16 Reserved1; /*0x06 */
516 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
517 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
518 Mpi2SCSIIOSuccessReplyDescriptor_t,
519 *pMpi2SCSIIOSuccessReplyDescriptor_t;
520
521 /*TargetAssist Success Reply Descriptor */
522 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
523 U8 ReplyFlags; /*0x00 */
524 U8 MSIxIndex; /*0x01 */
525 U16 SMID; /*0x02 */
526 U8 SequenceNumber; /*0x04 */
527 U8 Reserved1; /*0x05 */
528 U16 IoIndex; /*0x06 */
529 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
530 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
531 Mpi2TargetAssistSuccessReplyDescriptor_t,
532 *pMpi2TargetAssistSuccessReplyDescriptor_t;
533
534 /*Target Command Buffer Reply Descriptor */
535 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
536 U8 ReplyFlags; /*0x00 */
537 U8 MSIxIndex; /*0x01 */
538 U8 VP_ID; /*0x02 */
539 U8 Flags; /*0x03 */
540 U16 InitiatorDevHandle; /*0x04 */
541 U16 IoIndex; /*0x06 */
542 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
543 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
544 Mpi2TargetCommandBufferReplyDescriptor_t,
545 *pMpi2TargetCommandBufferReplyDescriptor_t;
546
547 /*defines for Flags field */
548 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
549
550 /*RAID Accelerator Success Reply Descriptor */
551 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
552 U8 ReplyFlags; /*0x00 */
553 U8 MSIxIndex; /*0x01 */
554 U16 SMID; /*0x02 */
555 U32 Reserved; /*0x04 */
556 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
557 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
558 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
559 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
560
561 /*Fast Path SCSI IO Success Reply Descriptor */
562 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
563 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
564 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
565 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
566 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
567
568 /*union of Reply Descriptors */
569 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
570 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
571 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
572 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
573 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
574 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
575 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
576 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
577 U64 Words;
578 } MPI2_REPLY_DESCRIPTORS_UNION,
579 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
580 Mpi2ReplyDescriptorsUnion_t,
581 *pMpi2ReplyDescriptorsUnion_t;
582
583 /*****************************************************************************
584 *
585 * Message Functions
586 *
587 *****************************************************************************/
588
589 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
590 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
591 #define MPI2_FUNCTION_IOC_INIT (0x02)
592 #define MPI2_FUNCTION_IOC_FACTS (0x03)
593 #define MPI2_FUNCTION_CONFIG (0x04)
594 #define MPI2_FUNCTION_PORT_FACTS (0x05)
595 #define MPI2_FUNCTION_PORT_ENABLE (0x06)
596 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
597 #define MPI2_FUNCTION_EVENT_ACK (0x08)
598 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
599 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
600 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
601 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
602 #define MPI2_FUNCTION_FW_UPLOAD (0x12)
603 #define MPI2_FUNCTION_RAID_ACTION (0x15)
604 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
605 #define MPI2_FUNCTION_TOOLBOX (0x17)
606 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
607 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
608 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
609 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
610 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
611 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
612 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
613 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
614 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
615 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
616 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
617 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
618 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
619 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
620 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
621
622 /*Doorbell functions */
623 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
624 #define MPI2_FUNCTION_HANDSHAKE (0x42)
625
626 /*****************************************************************************
627 *
628 * IOC Status Values
629 *
630 *****************************************************************************/
631
632 /*mask for IOCStatus status value */
633 #define MPI2_IOCSTATUS_MASK (0x7FFF)
634
635 /****************************************************************************
636 * Common IOCStatus values for all replies
637 ****************************************************************************/
638
639 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
640 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
641 #define MPI2_IOCSTATUS_BUSY (0x0002)
642 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
643 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
644 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
645 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
646 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
647 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
648 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
649 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
650
651 /****************************************************************************
652 * Config IOCStatus values
653 ****************************************************************************/
654
655 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
656 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
657 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
658 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
659 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
660 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
661
662 /****************************************************************************
663 * SCSI IO Reply
664 ****************************************************************************/
665
666 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
667 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
668 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
669 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
670 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
671 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
672 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
673 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
674 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
675 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
676 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
677 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
678
679 /****************************************************************************
680 * For use by SCSI Initiator and SCSI Target end-to-end data protection
681 ****************************************************************************/
682
683 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
684 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
685 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
686
687 /****************************************************************************
688 * SCSI Target values
689 ****************************************************************************/
690
691 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
692 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
693 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
694 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
695 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
696 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
697 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
698 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
699 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
700 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
701
702 /****************************************************************************
703 * Serial Attached SCSI values
704 ****************************************************************************/
705
706 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
707 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
708
709 /****************************************************************************
710 * Diagnostic Buffer Post / Diagnostic Release values
711 ****************************************************************************/
712
713 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
714
715 /****************************************************************************
716 * RAID Accelerator values
717 ****************************************************************************/
718
719 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
720
721 /****************************************************************************
722 * IOCStatus flag to indicate that log info is available
723 ****************************************************************************/
724
725 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
726
727 /****************************************************************************
728 * IOCLogInfo Types
729 ****************************************************************************/
730
731 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
732 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
733 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
734 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
735 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
736 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
737 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
738 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
739
740 /*****************************************************************************
741 *
742 * Standard Message Structures
743 *
744 *****************************************************************************/
745
746 /****************************************************************************
747 *Request Message Header for all request messages
748 ****************************************************************************/
749
750 typedef struct _MPI2_REQUEST_HEADER {
751 U16 FunctionDependent1; /*0x00 */
752 U8 ChainOffset; /*0x02 */
753 U8 Function; /*0x03 */
754 U16 FunctionDependent2; /*0x04 */
755 U8 FunctionDependent3; /*0x06 */
756 U8 MsgFlags; /*0x07 */
757 U8 VP_ID; /*0x08 */
758 U8 VF_ID; /*0x09 */
759 U16 Reserved1; /*0x0A */
760 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
761 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
762
763 /****************************************************************************
764 * Default Reply
765 ****************************************************************************/
766
767 typedef struct _MPI2_DEFAULT_REPLY {
768 U16 FunctionDependent1; /*0x00 */
769 U8 MsgLength; /*0x02 */
770 U8 Function; /*0x03 */
771 U16 FunctionDependent2; /*0x04 */
772 U8 FunctionDependent3; /*0x06 */
773 U8 MsgFlags; /*0x07 */
774 U8 VP_ID; /*0x08 */
775 U8 VF_ID; /*0x09 */
776 U16 Reserved1; /*0x0A */
777 U16 FunctionDependent5; /*0x0C */
778 U16 IOCStatus; /*0x0E */
779 U32 IOCLogInfo; /*0x10 */
780 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
781 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
782
783 /*common version structure/union used in messages and configuration pages */
784
785 typedef struct _MPI2_VERSION_STRUCT {
786 U8 Dev; /*0x00 */
787 U8 Unit; /*0x01 */
788 U8 Minor; /*0x02 */
789 U8 Major; /*0x03 */
790 } MPI2_VERSION_STRUCT;
791
792 typedef union _MPI2_VERSION_UNION {
793 MPI2_VERSION_STRUCT Struct;
794 U32 Word;
795 } MPI2_VERSION_UNION;
796
797 /*LUN field defines, common to many structures */
798 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
799 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
800 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
801 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
802 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
803 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
804
805 /*****************************************************************************
806 *
807 * Fusion-MPT MPI Scatter Gather Elements
808 *
809 *****************************************************************************/
810
811 /****************************************************************************
812 * MPI Simple Element structures
813 ****************************************************************************/
814
815 typedef struct _MPI2_SGE_SIMPLE32 {
816 U32 FlagsLength;
817 U32 Address;
818 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
819 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
820
821 typedef struct _MPI2_SGE_SIMPLE64 {
822 U32 FlagsLength;
823 U64 Address;
824 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
825 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
826
827 typedef struct _MPI2_SGE_SIMPLE_UNION {
828 U32 FlagsLength;
829 union {
830 U32 Address32;
831 U64 Address64;
832 } u;
833 } MPI2_SGE_SIMPLE_UNION,
834 *PTR_MPI2_SGE_SIMPLE_UNION,
835 Mpi2SGESimpleUnion_t,
836 *pMpi2SGESimpleUnion_t;
837
838 /****************************************************************************
839 * MPI Chain Element structures - for MPI v2.0 products only
840 ****************************************************************************/
841
842 typedef struct _MPI2_SGE_CHAIN32 {
843 U16 Length;
844 U8 NextChainOffset;
845 U8 Flags;
846 U32 Address;
847 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
848 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
849
850 typedef struct _MPI2_SGE_CHAIN64 {
851 U16 Length;
852 U8 NextChainOffset;
853 U8 Flags;
854 U64 Address;
855 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
856 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
857
858 typedef struct _MPI2_SGE_CHAIN_UNION {
859 U16 Length;
860 U8 NextChainOffset;
861 U8 Flags;
862 union {
863 U32 Address32;
864 U64 Address64;
865 } u;
866 } MPI2_SGE_CHAIN_UNION,
867 *PTR_MPI2_SGE_CHAIN_UNION,
868 Mpi2SGEChainUnion_t,
869 *pMpi2SGEChainUnion_t;
870
871 /****************************************************************************
872 * MPI Transaction Context Element structures - for MPI v2.0 products only
873 ****************************************************************************/
874
875 typedef struct _MPI2_SGE_TRANSACTION32 {
876 U8 Reserved;
877 U8 ContextSize;
878 U8 DetailsLength;
879 U8 Flags;
880 U32 TransactionContext[1];
881 U32 TransactionDetails[1];
882 } MPI2_SGE_TRANSACTION32,
883 *PTR_MPI2_SGE_TRANSACTION32,
884 Mpi2SGETransaction32_t,
885 *pMpi2SGETransaction32_t;
886
887 typedef struct _MPI2_SGE_TRANSACTION64 {
888 U8 Reserved;
889 U8 ContextSize;
890 U8 DetailsLength;
891 U8 Flags;
892 U32 TransactionContext[2];
893 U32 TransactionDetails[1];
894 } MPI2_SGE_TRANSACTION64,
895 *PTR_MPI2_SGE_TRANSACTION64,
896 Mpi2SGETransaction64_t,
897 *pMpi2SGETransaction64_t;
898
899 typedef struct _MPI2_SGE_TRANSACTION96 {
900 U8 Reserved;
901 U8 ContextSize;
902 U8 DetailsLength;
903 U8 Flags;
904 U32 TransactionContext[3];
905 U32 TransactionDetails[1];
906 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
907 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
908
909 typedef struct _MPI2_SGE_TRANSACTION128 {
910 U8 Reserved;
911 U8 ContextSize;
912 U8 DetailsLength;
913 U8 Flags;
914 U32 TransactionContext[4];
915 U32 TransactionDetails[1];
916 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
917 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
918
919 typedef struct _MPI2_SGE_TRANSACTION_UNION {
920 U8 Reserved;
921 U8 ContextSize;
922 U8 DetailsLength;
923 U8 Flags;
924 union {
925 U32 TransactionContext32[1];
926 U32 TransactionContext64[2];
927 U32 TransactionContext96[3];
928 U32 TransactionContext128[4];
929 } u;
930 U32 TransactionDetails[1];
931 } MPI2_SGE_TRANSACTION_UNION,
932 *PTR_MPI2_SGE_TRANSACTION_UNION,
933 Mpi2SGETransactionUnion_t,
934 *pMpi2SGETransactionUnion_t;
935
936 /****************************************************************************
937 * MPI SGE union for IO SGL's - for MPI v2.0 products only
938 ****************************************************************************/
939
940 typedef struct _MPI2_MPI_SGE_IO_UNION {
941 union {
942 MPI2_SGE_SIMPLE_UNION Simple;
943 MPI2_SGE_CHAIN_UNION Chain;
944 } u;
945 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
946 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
947
948 /****************************************************************************
949 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
950 ****************************************************************************/
951
952 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
953 union {
954 MPI2_SGE_SIMPLE_UNION Simple;
955 MPI2_SGE_TRANSACTION_UNION Transaction;
956 } u;
957 } MPI2_SGE_TRANS_SIMPLE_UNION,
958 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
959 Mpi2SGETransSimpleUnion_t,
960 *pMpi2SGETransSimpleUnion_t;
961
962 /****************************************************************************
963 * All MPI SGE types union
964 ****************************************************************************/
965
966 typedef struct _MPI2_MPI_SGE_UNION {
967 union {
968 MPI2_SGE_SIMPLE_UNION Simple;
969 MPI2_SGE_CHAIN_UNION Chain;
970 MPI2_SGE_TRANSACTION_UNION Transaction;
971 } u;
972 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
973 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
974
975 /****************************************************************************
976 * MPI SGE field definition and masks
977 ****************************************************************************/
978
979 /*Flags field bit definitions */
980
981 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
982 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
983 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
984 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
985 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
986 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
987 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
988
989 #define MPI2_SGE_FLAGS_SHIFT (24)
990
991 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
992 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
993
994 /*Element Type */
995
996 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
997 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
998 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
999 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1000
1001 /*Address location */
1002
1003 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1004
1005 /*Direction */
1006
1007 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1008 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1009
1010 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1011 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1012
1013 /*Address Size */
1014
1015 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1016 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1017
1018 /*Context Size */
1019
1020 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1021 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1022 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1023 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1024
1025 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1026 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1027
1028 /****************************************************************************
1029 * MPI SGE operation Macros
1030 ****************************************************************************/
1031
1032 /*SIMPLE FlagsLength manipulations... */
1033 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1034 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1035 MPI2_SGE_FLAGS_SHIFT)
1036 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1037 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1038
1039 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1040 MPI2_SGE_LENGTH(l))
1041
1042 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1043 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1044 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1045 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1046
1047 /*CAUTION - The following are READ-MODIFY-WRITE! */
1048 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1049 MPI2_SGE_SET_FLAGS(f))
1050 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1051 MPI2_SGE_LENGTH(l))
1052
1053 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1054 MPI2_SGE_CHAIN_OFFSET_SHIFT)
1055
1056 /*****************************************************************************
1057 *
1058 * Fusion-MPT IEEE Scatter Gather Elements
1059 *
1060 *****************************************************************************/
1061
1062 /****************************************************************************
1063 * IEEE Simple Element structures
1064 ****************************************************************************/
1065
1066 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1067 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1068 U32 Address;
1069 U32 FlagsLength;
1070 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1071 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1072
1073 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1074 U64 Address;
1075 U32 Length;
1076 U16 Reserved1;
1077 U8 Reserved2;
1078 U8 Flags;
1079 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1080 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1081
1082 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1083 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1084 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1085 } MPI2_IEEE_SGE_SIMPLE_UNION,
1086 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1087 Mpi2IeeeSgeSimpleUnion_t,
1088 *pMpi2IeeeSgeSimpleUnion_t;
1089
1090 /****************************************************************************
1091 * IEEE Chain Element structures
1092 ****************************************************************************/
1093
1094 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1095 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1096
1097 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1098 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1099
1100 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1101 MPI2_IEEE_SGE_CHAIN32 Chain32;
1102 MPI2_IEEE_SGE_CHAIN64 Chain64;
1103 } MPI2_IEEE_SGE_CHAIN_UNION,
1104 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1105 Mpi2IeeeSgeChainUnion_t,
1106 *pMpi2IeeeSgeChainUnion_t;
1107
1108 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1109 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1110 U64 Address;
1111 U32 Length;
1112 U16 Reserved1;
1113 U8 NextChainOffset;
1114 U8 Flags;
1115 } MPI25_IEEE_SGE_CHAIN64,
1116 *PTR_MPI25_IEEE_SGE_CHAIN64,
1117 Mpi25IeeeSgeChain64_t,
1118 *pMpi25IeeeSgeChain64_t;
1119
1120 /****************************************************************************
1121 * All IEEE SGE types union
1122 ****************************************************************************/
1123
1124 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1125 typedef struct _MPI2_IEEE_SGE_UNION {
1126 union {
1127 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1128 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1129 } u;
1130 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1131 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1132
1133 /****************************************************************************
1134 * IEEE SGE union for IO SGL's
1135 ****************************************************************************/
1136
1137 typedef union _MPI25_SGE_IO_UNION {
1138 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1139 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1140 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1141 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1142
1143 /****************************************************************************
1144 * IEEE SGE field definitions and masks
1145 ****************************************************************************/
1146
1147 /*Flags field bit definitions */
1148
1149 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1150 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1151
1152 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1153
1154 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1155
1156 /*Element Type */
1157
1158 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1159 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1160
1161 /*Next Segment Format */
1162
1163 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1164 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1165
1166 /*Data Location Address Space */
1167
1168 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1169 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1170 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1171 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1172 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1173 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1174 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1175 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1176 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1177
1178 /****************************************************************************
1179 * IEEE SGE operation Macros
1180 ****************************************************************************/
1181
1182 /*SIMPLE FlagsLength manipulations... */
1183 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1184 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1185 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1186 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1187
1188 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1189 MPI2_IEEE32_SGE_LENGTH(l))
1190
1191 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1192 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1193 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1194 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1195 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1196 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1197
1198 /*CAUTION - The following are READ-MODIFY-WRITE! */
1199 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1200 MPI2_IEEE32_SGE_SET_FLAGS(f))
1201 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1202 MPI2_IEEE32_SGE_LENGTH(l))
1203
1204 /*****************************************************************************
1205 *
1206 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1207 *
1208 *****************************************************************************/
1209
1210 typedef union _MPI2_SIMPLE_SGE_UNION {
1211 MPI2_SGE_SIMPLE_UNION MpiSimple;
1212 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1213 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1214 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1215
1216 typedef union _MPI2_SGE_IO_UNION {
1217 MPI2_SGE_SIMPLE_UNION MpiSimple;
1218 MPI2_SGE_CHAIN_UNION MpiChain;
1219 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1220 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1221 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1222 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1223
1224 /****************************************************************************
1225 *
1226 * Values for SGLFlags field, used in many request messages with an SGL
1227 *
1228 ****************************************************************************/
1229
1230 /*values for MPI SGL Data Location Address Space subfield */
1231 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1232 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1233 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1234 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1235 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1236 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1237 /*values for SGL Type subfield */
1238 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1239 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1240 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1241 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1242
1243 #endif
Linux with added FPC-III support