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b43: N-PHY: use helper for checking IPA
[linux/fpc-iii.git] / drivers / dma / coh901318.c
bloba92d95eac86b204fcb62dd1dafbe8a7150957807
1 /*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/scatterlist.h>
15 #include <linux/slab.h> /* kmalloc() */
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/irqreturn.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/uaccess.h>
23 #include <linux/debugfs.h>
24 #include <mach/coh901318.h>
25
26 #include "coh901318_lli.h"
27
28 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
29
30 #ifdef VERBOSE_DEBUG
31 #define COH_DBG(x) ({ if (1) x; 0; })
32 #else
33 #define COH_DBG(x) ({ if (0) x; 0; })
34 #endif
35
36 struct coh901318_desc {
37 struct dma_async_tx_descriptor desc;
38 struct list_head node;
39 struct scatterlist *sg;
40 unsigned int sg_len;
41 struct coh901318_lli *lli;
42 enum dma_data_direction dir;
43 unsigned long flags;
44 };
45
46 struct coh901318_base {
47 struct device *dev;
48 void __iomem *virtbase;
49 struct coh901318_pool pool;
50 struct powersave pm;
51 struct dma_device dma_slave;
52 struct dma_device dma_memcpy;
53 struct coh901318_chan *chans;
54 struct coh901318_platform *platform;
55 };
56
57 struct coh901318_chan {
58 spinlock_t lock;
59 int allocated;
60 int completed;
61 int id;
62 int stopped;
63
64 struct work_struct free_work;
65 struct dma_chan chan;
66
67 struct tasklet_struct tasklet;
68
69 struct list_head active;
70 struct list_head queue;
71 struct list_head free;
72
73 unsigned long nbr_active_done;
74 unsigned long busy;
75
76 u32 runtime_addr;
77 u32 runtime_ctrl;
78
79 struct coh901318_base *base;
80 };
81
82 static void coh901318_list_print(struct coh901318_chan *cohc,
83 struct coh901318_lli *lli)
84 {
85 struct coh901318_lli *l = lli;
86 int i = 0;
87
88 while (l) {
89 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
90 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
91 i, l, l->control, l->src_addr, l->dst_addr,
92 l->link_addr, l->virt_link_addr);
93 i++;
94 l = l->virt_link_addr;
95 }
96 }
97
98 #ifdef CONFIG_DEBUG_FS
99
100 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
101
102 static struct coh901318_base *debugfs_dma_base;
103 static struct dentry *dma_dentry;
104
105 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
106 {
107
108 file->private_data = inode->i_private;
109 return 0;
110 }
111
112 static int coh901318_debugfs_read(struct file *file, char __user *buf,
113 size_t count, loff_t *f_pos)
114 {
115 u64 started_channels = debugfs_dma_base->pm.started_channels;
116 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
117 int i;
118 int ret = 0;
119 char *dev_buf;
120 char *tmp;
121 int dev_size;
122
123 dev_buf = kmalloc(4*1024, GFP_KERNEL);
124 if (dev_buf == NULL)
125 goto err_kmalloc;
126 tmp = dev_buf;
127
128 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
129
130 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
131 if (started_channels & (1 << i))
132 tmp += sprintf(tmp, "channel %d\n", i);
133
134 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
135 dev_size = tmp - dev_buf;
136
137 /* No more to read if offset != 0 */
138 if (*f_pos > dev_size)
139 goto out;
140
141 if (count > dev_size - *f_pos)
142 count = dev_size - *f_pos;
143
144 if (copy_to_user(buf, dev_buf + *f_pos, count))
145 ret = -EINVAL;
146 ret = count;
147 *f_pos += count;
148
149 out:
150 kfree(dev_buf);
151 return ret;
152
153 err_kmalloc:
154 return 0;
155 }
156
157 static const struct file_operations coh901318_debugfs_status_operations = {
158 .owner = THIS_MODULE,
159 .open = coh901318_debugfs_open,
160 .read = coh901318_debugfs_read,
161 .llseek = default_llseek,
162 };
163
164
165 static int __init init_coh901318_debugfs(void)
166 {
167
168 dma_dentry = debugfs_create_dir("dma", NULL);
169
170 (void) debugfs_create_file("status",
171 S_IFREG | S_IRUGO,
172 dma_dentry, NULL,
173 &coh901318_debugfs_status_operations);
174 return 0;
175 }
176
177 static void __exit exit_coh901318_debugfs(void)
178 {
179 debugfs_remove_recursive(dma_dentry);
180 }
181
182 module_init(init_coh901318_debugfs);
183 module_exit(exit_coh901318_debugfs);
184 #else
185
186 #define COH901318_DEBUGFS_ASSIGN(x, y)
187
188 #endif /* CONFIG_DEBUG_FS */
189
190 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
191 {
192 return container_of(chan, struct coh901318_chan, chan);
193 }
194
195 static inline dma_addr_t
196 cohc_dev_addr(struct coh901318_chan *cohc)
197 {
198 /* Runtime supplied address will take precedence */
199 if (cohc->runtime_addr)
200 return cohc->runtime_addr;
201 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
202 }
203
204 static inline const struct coh901318_params *
205 cohc_chan_param(struct coh901318_chan *cohc)
206 {
207 return &cohc->base->platform->chan_conf[cohc->id].param;
208 }
209
210 static inline const struct coh_dma_channel *
211 cohc_chan_conf(struct coh901318_chan *cohc)
212 {
213 return &cohc->base->platform->chan_conf[cohc->id];
214 }
215
216 static void enable_powersave(struct coh901318_chan *cohc)
217 {
218 unsigned long flags;
219 struct powersave *pm = &cohc->base->pm;
220
221 spin_lock_irqsave(&pm->lock, flags);
222
223 pm->started_channels &= ~(1ULL << cohc->id);
224
225 if (!pm->started_channels) {
226 /* DMA no longer intends to access memory */
227 cohc->base->platform->access_memory_state(cohc->base->dev,
228 false);
229 }
230
231 spin_unlock_irqrestore(&pm->lock, flags);
232 }
233 static void disable_powersave(struct coh901318_chan *cohc)
234 {
235 unsigned long flags;
236 struct powersave *pm = &cohc->base->pm;
237
238 spin_lock_irqsave(&pm->lock, flags);
239
240 if (!pm->started_channels) {
241 /* DMA intends to access memory */
242 cohc->base->platform->access_memory_state(cohc->base->dev,
243 true);
244 }
245
246 pm->started_channels |= (1ULL << cohc->id);
247
248 spin_unlock_irqrestore(&pm->lock, flags);
249 }
250
251 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
252 {
253 int channel = cohc->id;
254 void __iomem *virtbase = cohc->base->virtbase;
255
256 writel(control,
257 virtbase + COH901318_CX_CTRL +
258 COH901318_CX_CTRL_SPACING * channel);
259 return 0;
260 }
261
262 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
263 {
264 int channel = cohc->id;
265 void __iomem *virtbase = cohc->base->virtbase;
266
267 writel(conf,
268 virtbase + COH901318_CX_CFG +
269 COH901318_CX_CFG_SPACING*channel);
270 return 0;
271 }
272
273
274 static int coh901318_start(struct coh901318_chan *cohc)
275 {
276 u32 val;
277 int channel = cohc->id;
278 void __iomem *virtbase = cohc->base->virtbase;
279
280 disable_powersave(cohc);
281
282 val = readl(virtbase + COH901318_CX_CFG +
283 COH901318_CX_CFG_SPACING * channel);
284
285 /* Enable channel */
286 val |= COH901318_CX_CFG_CH_ENABLE;
287 writel(val, virtbase + COH901318_CX_CFG +
288 COH901318_CX_CFG_SPACING * channel);
289
290 return 0;
291 }
292
293 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
294 struct coh901318_lli *lli)
295 {
296 int channel = cohc->id;
297 void __iomem *virtbase = cohc->base->virtbase;
298
299 BUG_ON(readl(virtbase + COH901318_CX_STAT +
300 COH901318_CX_STAT_SPACING*channel) &
301 COH901318_CX_STAT_ACTIVE);
302
303 writel(lli->src_addr,
304 virtbase + COH901318_CX_SRC_ADDR +
305 COH901318_CX_SRC_ADDR_SPACING * channel);
306
307 writel(lli->dst_addr, virtbase +
308 COH901318_CX_DST_ADDR +
309 COH901318_CX_DST_ADDR_SPACING * channel);
310
311 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
312 COH901318_CX_LNK_ADDR_SPACING * channel);
313
314 writel(lli->control, virtbase + COH901318_CX_CTRL +
315 COH901318_CX_CTRL_SPACING * channel);
316
317 return 0;
318 }
319 static dma_cookie_t
320 coh901318_assign_cookie(struct coh901318_chan *cohc,
321 struct coh901318_desc *cohd)
322 {
323 dma_cookie_t cookie = cohc->chan.cookie;
324
325 if (++cookie < 0)
326 cookie = 1;
327
328 cohc->chan.cookie = cookie;
329 cohd->desc.cookie = cookie;
330
331 return cookie;
332 }
333
334 static struct coh901318_desc *
335 coh901318_desc_get(struct coh901318_chan *cohc)
336 {
337 struct coh901318_desc *desc;
338
339 if (list_empty(&cohc->free)) {
340 /* alloc new desc because we're out of used ones
341 * TODO: alloc a pile of descs instead of just one,
342 * avoid many small allocations.
343 */
344 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
345 if (desc == NULL)
346 goto out;
347 INIT_LIST_HEAD(&desc->node);
348 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
349 } else {
350 /* Reuse an old desc. */
351 desc = list_first_entry(&cohc->free,
352 struct coh901318_desc,
353 node);
354 list_del(&desc->node);
355 /* Initialize it a bit so it's not insane */
356 desc->sg = NULL;
357 desc->sg_len = 0;
358 desc->desc.callback = NULL;
359 desc->desc.callback_param = NULL;
360 }
361
362 out:
363 return desc;
364 }
365
366 static void
367 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
368 {
369 list_add_tail(&cohd->node, &cohc->free);
370 }
371
372 /* call with irq lock held */
373 static void
374 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
375 {
376 list_add_tail(&desc->node, &cohc->active);
377 }
378
379 static struct coh901318_desc *
380 coh901318_first_active_get(struct coh901318_chan *cohc)
381 {
382 struct coh901318_desc *d;
383
384 if (list_empty(&cohc->active))
385 return NULL;
386
387 d = list_first_entry(&cohc->active,
388 struct coh901318_desc,
389 node);
390 return d;
391 }
392
393 static void
394 coh901318_desc_remove(struct coh901318_desc *cohd)
395 {
396 list_del(&cohd->node);
397 }
398
399 static void
400 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
401 {
402 list_add_tail(&desc->node, &cohc->queue);
403 }
404
405 static struct coh901318_desc *
406 coh901318_first_queued(struct coh901318_chan *cohc)
407 {
408 struct coh901318_desc *d;
409
410 if (list_empty(&cohc->queue))
411 return NULL;
412
413 d = list_first_entry(&cohc->queue,
414 struct coh901318_desc,
415 node);
416 return d;
417 }
418
419 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
420 {
421 struct coh901318_lli *lli = in_lli;
422 u32 bytes = 0;
423
424 while (lli) {
425 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
426 lli = lli->virt_link_addr;
427 }
428 return bytes;
429 }
430
431 /*
432 * Get the number of bytes left to transfer on this channel,
433 * it is unwise to call this before stopping the channel for
434 * absolute measures, but for a rough guess you can still call
435 * it.
436 */
437 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
438 {
439 struct coh901318_chan *cohc = to_coh901318_chan(chan);
440 struct coh901318_desc *cohd;
441 struct list_head *pos;
442 unsigned long flags;
443 u32 left = 0;
444 int i = 0;
445
446 spin_lock_irqsave(&cohc->lock, flags);
447
448 /*
449 * If there are many queued jobs, we iterate and add the
450 * size of them all. We take a special look on the first
451 * job though, since it is probably active.
452 */
453 list_for_each(pos, &cohc->active) {
454 /*
455 * The first job in the list will be working on the
456 * hardware. The job can be stopped but still active,
457 * so that the transfer counter is somewhere inside
458 * the buffer.
459 */
460 cohd = list_entry(pos, struct coh901318_desc, node);
461
462 if (i == 0) {
463 struct coh901318_lli *lli;
464 dma_addr_t ladd;
465
466 /* Read current transfer count value */
467 left = readl(cohc->base->virtbase +
468 COH901318_CX_CTRL +
469 COH901318_CX_CTRL_SPACING * cohc->id) &
470 COH901318_CX_CTRL_TC_VALUE_MASK;
471
472 /* See if the transfer is linked... */
473 ladd = readl(cohc->base->virtbase +
474 COH901318_CX_LNK_ADDR +
475 COH901318_CX_LNK_ADDR_SPACING *
476 cohc->id) &
477 ~COH901318_CX_LNK_LINK_IMMEDIATE;
478 /* Single transaction */
479 if (!ladd)
480 continue;
481
482 /*
483 * Linked transaction, follow the lli, find the
484 * currently processing lli, and proceed to the next
485 */
486 lli = cohd->lli;
487 while (lli && lli->link_addr != ladd)
488 lli = lli->virt_link_addr;
489
490 if (lli)
491 lli = lli->virt_link_addr;
492
493 /*
494 * Follow remaining lli links around to count the total
495 * number of bytes left
496 */
497 left += coh901318_get_bytes_in_lli(lli);
498 } else {
499 left += coh901318_get_bytes_in_lli(cohd->lli);
500 }
501 i++;
502 }
503
504 /* Also count bytes in the queued jobs */
505 list_for_each(pos, &cohc->queue) {
506 cohd = list_entry(pos, struct coh901318_desc, node);
507 left += coh901318_get_bytes_in_lli(cohd->lli);
508 }
509
510 spin_unlock_irqrestore(&cohc->lock, flags);
511
512 return left;
513 }
514
515 /*
516 * Pauses a transfer without losing data. Enables power save.
517 * Use this function in conjunction with coh901318_resume.
518 */
519 static void coh901318_pause(struct dma_chan *chan)
520 {
521 u32 val;
522 unsigned long flags;
523 struct coh901318_chan *cohc = to_coh901318_chan(chan);
524 int channel = cohc->id;
525 void __iomem *virtbase = cohc->base->virtbase;
526
527 spin_lock_irqsave(&cohc->lock, flags);
528
529 /* Disable channel in HW */
530 val = readl(virtbase + COH901318_CX_CFG +
531 COH901318_CX_CFG_SPACING * channel);
532
533 /* Stopping infinite transfer */
534 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
535 (val & COH901318_CX_CFG_CH_ENABLE))
536 cohc->stopped = 1;
537
538
539 val &= ~COH901318_CX_CFG_CH_ENABLE;
540 /* Enable twice, HW bug work around */
541 writel(val, virtbase + COH901318_CX_CFG +
542 COH901318_CX_CFG_SPACING * channel);
543 writel(val, virtbase + COH901318_CX_CFG +
544 COH901318_CX_CFG_SPACING * channel);
545
546 /* Spin-wait for it to actually go inactive */
547 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
548 channel) & COH901318_CX_STAT_ACTIVE)
549 cpu_relax();
550
551 /* Check if we stopped an active job */
552 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
553 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
554 cohc->stopped = 1;
555
556 enable_powersave(cohc);
557
558 spin_unlock_irqrestore(&cohc->lock, flags);
559 }
560
561 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
562 Power save is handled.
563 */
564 static void coh901318_resume(struct dma_chan *chan)
565 {
566 u32 val;
567 unsigned long flags;
568 struct coh901318_chan *cohc = to_coh901318_chan(chan);
569 int channel = cohc->id;
570
571 spin_lock_irqsave(&cohc->lock, flags);
572
573 disable_powersave(cohc);
574
575 if (cohc->stopped) {
576 /* Enable channel in HW */
577 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
578 COH901318_CX_CFG_SPACING * channel);
579
580 val |= COH901318_CX_CFG_CH_ENABLE;
581
582 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
583 COH901318_CX_CFG_SPACING*channel);
584
585 cohc->stopped = 0;
586 }
587
588 spin_unlock_irqrestore(&cohc->lock, flags);
589 }
590
591 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
592 {
593 unsigned int ch_nr = (unsigned int) chan_id;
594
595 if (ch_nr == to_coh901318_chan(chan)->id)
596 return true;
597
598 return false;
599 }
600 EXPORT_SYMBOL(coh901318_filter_id);
601
602 /*
603 * DMA channel allocation
604 */
605 static int coh901318_config(struct coh901318_chan *cohc,
606 struct coh901318_params *param)
607 {
608 unsigned long flags;
609 const struct coh901318_params *p;
610 int channel = cohc->id;
611 void __iomem *virtbase = cohc->base->virtbase;
612
613 spin_lock_irqsave(&cohc->lock, flags);
614
615 if (param)
616 p = param;
617 else
618 p = &cohc->base->platform->chan_conf[channel].param;
619
620 /* Clear any pending BE or TC interrupt */
621 if (channel < 32) {
622 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
623 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
624 } else {
625 writel(1 << (channel - 32), virtbase +
626 COH901318_BE_INT_CLEAR2);
627 writel(1 << (channel - 32), virtbase +
628 COH901318_TC_INT_CLEAR2);
629 }
630
631 coh901318_set_conf(cohc, p->config);
632 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
633
634 spin_unlock_irqrestore(&cohc->lock, flags);
635
636 return 0;
637 }
638
639 /* must lock when calling this function
640 * start queued jobs, if any
641 * TODO: start all queued jobs in one go
642 *
643 * Returns descriptor if queued job is started otherwise NULL.
644 * If the queue is empty NULL is returned.
645 */
646 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
647 {
648 struct coh901318_desc *cohd;
649
650 /*
651 * start queued jobs, if any
652 * TODO: transmit all queued jobs in one go
653 */
654 cohd = coh901318_first_queued(cohc);
655
656 if (cohd != NULL) {
657 /* Remove from queue */
658 coh901318_desc_remove(cohd);
659 /* initiate DMA job */
660 cohc->busy = 1;
661
662 coh901318_desc_submit(cohc, cohd);
663
664 coh901318_prep_linked_list(cohc, cohd->lli);
665
666 /* start dma job on this channel */
667 coh901318_start(cohc);
668
669 }
670
671 return cohd;
672 }
673
674 /*
675 * This tasklet is called from the interrupt handler to
676 * handle each descriptor (DMA job) that is sent to a channel.
677 */
678 static void dma_tasklet(unsigned long data)
679 {
680 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
681 struct coh901318_desc *cohd_fin;
682 unsigned long flags;
683 dma_async_tx_callback callback;
684 void *callback_param;
685
686 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
687 " nbr_active_done %ld\n", __func__,
688 cohc->id, cohc->nbr_active_done);
689
690 spin_lock_irqsave(&cohc->lock, flags);
691
692 /* get first active descriptor entry from list */
693 cohd_fin = coh901318_first_active_get(cohc);
694
695 if (cohd_fin == NULL)
696 goto err;
697
698 /* locate callback to client */
699 callback = cohd_fin->desc.callback;
700 callback_param = cohd_fin->desc.callback_param;
701
702 /* sign this job as completed on the channel */
703 cohc->completed = cohd_fin->desc.cookie;
704
705 /* release the lli allocation and remove the descriptor */
706 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
707
708 /* return desc to free-list */
709 coh901318_desc_remove(cohd_fin);
710 coh901318_desc_free(cohc, cohd_fin);
711
712 spin_unlock_irqrestore(&cohc->lock, flags);
713
714 /* Call the callback when we're done */
715 if (callback)
716 callback(callback_param);
717
718 spin_lock_irqsave(&cohc->lock, flags);
719
720 /*
721 * If another interrupt fired while the tasklet was scheduling,
722 * we don't get called twice, so we have this number of active
723 * counter that keep track of the number of IRQs expected to
724 * be handled for this channel. If there happen to be more than
725 * one IRQ to be ack:ed, we simply schedule this tasklet again.
726 */
727 cohc->nbr_active_done--;
728 if (cohc->nbr_active_done) {
729 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
730 "came in while we were scheduling this tasklet\n");
731 if (cohc_chan_conf(cohc)->priority_high)
732 tasklet_hi_schedule(&cohc->tasklet);
733 else
734 tasklet_schedule(&cohc->tasklet);
735 }
736
737 spin_unlock_irqrestore(&cohc->lock, flags);
738
739 return;
740
741 err:
742 spin_unlock_irqrestore(&cohc->lock, flags);
743 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
744 }
745
746
747 /* called from interrupt context */
748 static void dma_tc_handle(struct coh901318_chan *cohc)
749 {
750 /*
751 * If the channel is not allocated, then we shouldn't have
752 * any TC interrupts on it.
753 */
754 if (!cohc->allocated) {
755 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
756 "unallocated channel\n");
757 return;
758 }
759
760 spin_lock(&cohc->lock);
761
762 /*
763 * When we reach this point, at least one queue item
764 * should have been moved over from cohc->queue to
765 * cohc->active and run to completion, that is why we're
766 * getting a terminal count interrupt is it not?
767 * If you get this BUG() the most probable cause is that
768 * the individual nodes in the lli chain have IRQ enabled,
769 * so check your platform config for lli chain ctrl.
770 */
771 BUG_ON(list_empty(&cohc->active));
772
773 cohc->nbr_active_done++;
774
775 /*
776 * This attempt to take a job from cohc->queue, put it
777 * into cohc->active and start it.
778 */
779 if (coh901318_queue_start(cohc) == NULL)
780 cohc->busy = 0;
781
782 spin_unlock(&cohc->lock);
783
784 /*
785 * This tasklet will remove items from cohc->active
786 * and thus terminates them.
787 */
788 if (cohc_chan_conf(cohc)->priority_high)
789 tasklet_hi_schedule(&cohc->tasklet);
790 else
791 tasklet_schedule(&cohc->tasklet);
792 }
793
794
795 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
796 {
797 u32 status1;
798 u32 status2;
799 int i;
800 int ch;
801 struct coh901318_base *base = dev_id;
802 struct coh901318_chan *cohc;
803 void __iomem *virtbase = base->virtbase;
804
805 status1 = readl(virtbase + COH901318_INT_STATUS1);
806 status2 = readl(virtbase + COH901318_INT_STATUS2);
807
808 if (unlikely(status1 == 0 && status2 == 0)) {
809 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
810 return IRQ_HANDLED;
811 }
812
813 /* TODO: consider handle IRQ in tasklet here to
814 * minimize interrupt latency */
815
816 /* Check the first 32 DMA channels for IRQ */
817 while (status1) {
818 /* Find first bit set, return as a number. */
819 i = ffs(status1) - 1;
820 ch = i;
821
822 cohc = &base->chans[ch];
823 spin_lock(&cohc->lock);
824
825 /* Mask off this bit */
826 status1 &= ~(1 << i);
827 /* Check the individual channel bits */
828 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
829 dev_crit(COHC_2_DEV(cohc),
830 "DMA bus error on channel %d!\n", ch);
831 BUG_ON(1);
832 /* Clear BE interrupt */
833 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
834 } else {
835 /* Caused by TC, really? */
836 if (unlikely(!test_bit(i, virtbase +
837 COH901318_TC_INT_STATUS1))) {
838 dev_warn(COHC_2_DEV(cohc),
839 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
840 /* Clear TC interrupt */
841 BUG_ON(1);
842 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
843 } else {
844 /* Enable powersave if transfer has finished */
845 if (!(readl(virtbase + COH901318_CX_STAT +
846 COH901318_CX_STAT_SPACING*ch) &
847 COH901318_CX_STAT_ENABLED)) {
848 enable_powersave(cohc);
849 }
850
851 /* Must clear TC interrupt before calling
852 * dma_tc_handle
853 * in case tc_handle initiate a new dma job
854 */
855 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
856
857 dma_tc_handle(cohc);
858 }
859 }
860 spin_unlock(&cohc->lock);
861 }
862
863 /* Check the remaining 32 DMA channels for IRQ */
864 while (status2) {
865 /* Find first bit set, return as a number. */
866 i = ffs(status2) - 1;
867 ch = i + 32;
868 cohc = &base->chans[ch];
869 spin_lock(&cohc->lock);
870
871 /* Mask off this bit */
872 status2 &= ~(1 << i);
873 /* Check the individual channel bits */
874 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
875 dev_crit(COHC_2_DEV(cohc),
876 "DMA bus error on channel %d!\n", ch);
877 /* Clear BE interrupt */
878 BUG_ON(1);
879 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
880 } else {
881 /* Caused by TC, really? */
882 if (unlikely(!test_bit(i, virtbase +
883 COH901318_TC_INT_STATUS2))) {
884 dev_warn(COHC_2_DEV(cohc),
885 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
886 /* Clear TC interrupt */
887 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
888 BUG_ON(1);
889 } else {
890 /* Enable powersave if transfer has finished */
891 if (!(readl(virtbase + COH901318_CX_STAT +
892 COH901318_CX_STAT_SPACING*ch) &
893 COH901318_CX_STAT_ENABLED)) {
894 enable_powersave(cohc);
895 }
896 /* Must clear TC interrupt before calling
897 * dma_tc_handle
898 * in case tc_handle initiate a new dma job
899 */
900 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
901
902 dma_tc_handle(cohc);
903 }
904 }
905 spin_unlock(&cohc->lock);
906 }
907
908 return IRQ_HANDLED;
909 }
910
911 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
912 {
913 struct coh901318_chan *cohc = to_coh901318_chan(chan);
914 unsigned long flags;
915
916 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
917 __func__, cohc->id);
918
919 if (chan->client_count > 1)
920 return -EBUSY;
921
922 spin_lock_irqsave(&cohc->lock, flags);
923
924 coh901318_config(cohc, NULL);
925
926 cohc->allocated = 1;
927 cohc->completed = chan->cookie = 1;
928
929 spin_unlock_irqrestore(&cohc->lock, flags);
930
931 return 1;
932 }
933
934 static void
935 coh901318_free_chan_resources(struct dma_chan *chan)
936 {
937 struct coh901318_chan *cohc = to_coh901318_chan(chan);
938 int channel = cohc->id;
939 unsigned long flags;
940
941 spin_lock_irqsave(&cohc->lock, flags);
942
943 /* Disable HW */
944 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
945 COH901318_CX_CFG_SPACING*channel);
946 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
947 COH901318_CX_CTRL_SPACING*channel);
948
949 cohc->allocated = 0;
950
951 spin_unlock_irqrestore(&cohc->lock, flags);
952
953 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
954 }
955
956
957 static dma_cookie_t
958 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
959 {
960 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
961 desc);
962 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
963 unsigned long flags;
964
965 spin_lock_irqsave(&cohc->lock, flags);
966
967 tx->cookie = coh901318_assign_cookie(cohc, cohd);
968
969 coh901318_desc_queue(cohc, cohd);
970
971 spin_unlock_irqrestore(&cohc->lock, flags);
972
973 return tx->cookie;
974 }
975
976 static struct dma_async_tx_descriptor *
977 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
978 size_t size, unsigned long flags)
979 {
980 struct coh901318_lli *lli;
981 struct coh901318_desc *cohd;
982 unsigned long flg;
983 struct coh901318_chan *cohc = to_coh901318_chan(chan);
984 int lli_len;
985 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
986 int ret;
987
988 spin_lock_irqsave(&cohc->lock, flg);
989
990 dev_vdbg(COHC_2_DEV(cohc),
991 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
992 __func__, cohc->id, src, dest, size);
993
994 if (flags & DMA_PREP_INTERRUPT)
995 /* Trigger interrupt after last lli */
996 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
997
998 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
999 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1000 lli_len++;
1001
1002 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
1003
1004 if (lli == NULL)
1005 goto err;
1006
1007 ret = coh901318_lli_fill_memcpy(
1008 &cohc->base->pool, lli, src, size, dest,
1009 cohc_chan_param(cohc)->ctrl_lli_chained,
1010 ctrl_last);
1011 if (ret)
1012 goto err;
1013
1014 COH_DBG(coh901318_list_print(cohc, lli));
1015
1016 /* Pick a descriptor to handle this transfer */
1017 cohd = coh901318_desc_get(cohc);
1018 cohd->lli = lli;
1019 cohd->flags = flags;
1020 cohd->desc.tx_submit = coh901318_tx_submit;
1021
1022 spin_unlock_irqrestore(&cohc->lock, flg);
1023
1024 return &cohd->desc;
1025 err:
1026 spin_unlock_irqrestore(&cohc->lock, flg);
1027 return NULL;
1028 }
1029
1030 static struct dma_async_tx_descriptor *
1031 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1032 unsigned int sg_len, enum dma_data_direction direction,
1033 unsigned long flags)
1034 {
1035 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1036 struct coh901318_lli *lli;
1037 struct coh901318_desc *cohd;
1038 const struct coh901318_params *params;
1039 struct scatterlist *sg;
1040 int len = 0;
1041 int size;
1042 int i;
1043 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1044 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1045 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1046 u32 config;
1047 unsigned long flg;
1048 int ret;
1049
1050 if (!sgl)
1051 goto out;
1052 if (sgl->length == 0)
1053 goto out;
1054
1055 spin_lock_irqsave(&cohc->lock, flg);
1056
1057 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1058 __func__, sg_len, direction);
1059
1060 if (flags & DMA_PREP_INTERRUPT)
1061 /* Trigger interrupt after last lli */
1062 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1063
1064 params = cohc_chan_param(cohc);
1065 config = params->config;
1066 /*
1067 * Add runtime-specific control on top, make
1068 * sure the bits you set per peripheral channel are
1069 * cleared in the default config from the platform.
1070 */
1071 ctrl_chained |= cohc->runtime_ctrl;
1072 ctrl_last |= cohc->runtime_ctrl;
1073 ctrl |= cohc->runtime_ctrl;
1074
1075 if (direction == DMA_TO_DEVICE) {
1076 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1077 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1078
1079 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1080 ctrl_chained |= tx_flags;
1081 ctrl_last |= tx_flags;
1082 ctrl |= tx_flags;
1083 } else if (direction == DMA_FROM_DEVICE) {
1084 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1085 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1086
1087 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1088 ctrl_chained |= rx_flags;
1089 ctrl_last |= rx_flags;
1090 ctrl |= rx_flags;
1091 } else
1092 goto err_direction;
1093
1094 coh901318_set_conf(cohc, config);
1095
1096 /* The dma only supports transmitting packages up to
1097 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1098 * dma elemts required to send the entire sg list
1099 */
1100 for_each_sg(sgl, sg, sg_len, i) {
1101 unsigned int factor;
1102 size = sg_dma_len(sg);
1103
1104 if (size <= MAX_DMA_PACKET_SIZE) {
1105 len++;
1106 continue;
1107 }
1108
1109 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1110 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1111 factor++;
1112
1113 len += factor;
1114 }
1115
1116 pr_debug("Allocate %d lli:s for this transfer\n", len);
1117 lli = coh901318_lli_alloc(&cohc->base->pool, len);
1118
1119 if (lli == NULL)
1120 goto err_dma_alloc;
1121
1122 /* initiate allocated lli list */
1123 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1124 cohc_dev_addr(cohc),
1125 ctrl_chained,
1126 ctrl,
1127 ctrl_last,
1128 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1129 if (ret)
1130 goto err_lli_fill;
1131
1132 /*
1133 * Set the default ctrl for the channel to the one from the lli,
1134 * things may have changed due to odd buffer alignment etc.
1135 */
1136 coh901318_set_ctrl(cohc, lli->control);
1137
1138 COH_DBG(coh901318_list_print(cohc, lli));
1139
1140 /* Pick a descriptor to handle this transfer */
1141 cohd = coh901318_desc_get(cohc);
1142 cohd->dir = direction;
1143 cohd->flags = flags;
1144 cohd->desc.tx_submit = coh901318_tx_submit;
1145 cohd->lli = lli;
1146
1147 spin_unlock_irqrestore(&cohc->lock, flg);
1148
1149 return &cohd->desc;
1150 err_lli_fill:
1151 err_dma_alloc:
1152 err_direction:
1153 spin_unlock_irqrestore(&cohc->lock, flg);
1154 out:
1155 return NULL;
1156 }
1157
1158 static enum dma_status
1159 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1160 struct dma_tx_state *txstate)
1161 {
1162 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1163 dma_cookie_t last_used;
1164 dma_cookie_t last_complete;
1165 int ret;
1166
1167 last_complete = cohc->completed;
1168 last_used = chan->cookie;
1169
1170 ret = dma_async_is_complete(cookie, last_complete, last_used);
1171
1172 dma_set_tx_state(txstate, last_complete, last_used,
1173 coh901318_get_bytes_left(chan));
1174 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1175 ret = DMA_PAUSED;
1176
1177 return ret;
1178 }
1179
1180 static void
1181 coh901318_issue_pending(struct dma_chan *chan)
1182 {
1183 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1184 unsigned long flags;
1185
1186 spin_lock_irqsave(&cohc->lock, flags);
1187
1188 /*
1189 * Busy means that pending jobs are already being processed,
1190 * and then there is no point in starting the queue: the
1191 * terminal count interrupt on the channel will take the next
1192 * job on the queue and execute it anyway.
1193 */
1194 if (!cohc->busy)
1195 coh901318_queue_start(cohc);
1196
1197 spin_unlock_irqrestore(&cohc->lock, flags);
1198 }
1199
1200 /*
1201 * Here we wrap in the runtime dma control interface
1202 */
1203 struct burst_table {
1204 int burst_8bit;
1205 int burst_16bit;
1206 int burst_32bit;
1207 u32 reg;
1208 };
1209
1210 static const struct burst_table burst_sizes[] = {
1211 {
1212 .burst_8bit = 64,
1213 .burst_16bit = 32,
1214 .burst_32bit = 16,
1215 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1216 },
1217 {
1218 .burst_8bit = 48,
1219 .burst_16bit = 24,
1220 .burst_32bit = 12,
1221 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1222 },
1223 {
1224 .burst_8bit = 32,
1225 .burst_16bit = 16,
1226 .burst_32bit = 8,
1227 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1228 },
1229 {
1230 .burst_8bit = 16,
1231 .burst_16bit = 8,
1232 .burst_32bit = 4,
1233 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1234 },
1235 {
1236 .burst_8bit = 8,
1237 .burst_16bit = 4,
1238 .burst_32bit = 2,
1239 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1240 },
1241 {
1242 .burst_8bit = 4,
1243 .burst_16bit = 2,
1244 .burst_32bit = 1,
1245 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1246 },
1247 {
1248 .burst_8bit = 2,
1249 .burst_16bit = 1,
1250 .burst_32bit = 0,
1251 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1252 },
1253 {
1254 .burst_8bit = 1,
1255 .burst_16bit = 0,
1256 .burst_32bit = 0,
1257 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1258 },
1259 };
1260
1261 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1262 struct dma_slave_config *config)
1263 {
1264 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1265 dma_addr_t addr;
1266 enum dma_slave_buswidth addr_width;
1267 u32 maxburst;
1268 u32 runtime_ctrl = 0;
1269 int i = 0;
1270
1271 /* We only support mem to per or per to mem transfers */
1272 if (config->direction == DMA_FROM_DEVICE) {
1273 addr = config->src_addr;
1274 addr_width = config->src_addr_width;
1275 maxburst = config->src_maxburst;
1276 } else if (config->direction == DMA_TO_DEVICE) {
1277 addr = config->dst_addr;
1278 addr_width = config->dst_addr_width;
1279 maxburst = config->dst_maxburst;
1280 } else {
1281 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1282 return;
1283 }
1284
1285 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1286 addr_width);
1287 switch (addr_width) {
1288 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1289 runtime_ctrl |=
1290 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1291 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1292
1293 while (i < ARRAY_SIZE(burst_sizes)) {
1294 if (burst_sizes[i].burst_8bit <= maxburst)
1295 break;
1296 i++;
1297 }
1298
1299 break;
1300 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1301 runtime_ctrl |=
1302 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1303 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1304
1305 while (i < ARRAY_SIZE(burst_sizes)) {
1306 if (burst_sizes[i].burst_16bit <= maxburst)
1307 break;
1308 i++;
1309 }
1310
1311 break;
1312 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1313 /* Direction doesn't matter here, it's 32/32 bits */
1314 runtime_ctrl |=
1315 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1316 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1317
1318 while (i < ARRAY_SIZE(burst_sizes)) {
1319 if (burst_sizes[i].burst_32bit <= maxburst)
1320 break;
1321 i++;
1322 }
1323
1324 break;
1325 default:
1326 dev_err(COHC_2_DEV(cohc),
1327 "bad runtimeconfig: alien address width\n");
1328 return;
1329 }
1330
1331 runtime_ctrl |= burst_sizes[i].reg;
1332 dev_dbg(COHC_2_DEV(cohc),
1333 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1334 burst_sizes[i].burst_8bit, addr_width, maxburst);
1335
1336 cohc->runtime_addr = addr;
1337 cohc->runtime_ctrl = runtime_ctrl;
1338 }
1339
1340 static int
1341 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1342 unsigned long arg)
1343 {
1344 unsigned long flags;
1345 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1346 struct coh901318_desc *cohd;
1347 void __iomem *virtbase = cohc->base->virtbase;
1348
1349 if (cmd == DMA_SLAVE_CONFIG) {
1350 struct dma_slave_config *config =
1351 (struct dma_slave_config *) arg;
1352
1353 coh901318_dma_set_runtimeconfig(chan, config);
1354 return 0;
1355 }
1356
1357 if (cmd == DMA_PAUSE) {
1358 coh901318_pause(chan);
1359 return 0;
1360 }
1361
1362 if (cmd == DMA_RESUME) {
1363 coh901318_resume(chan);
1364 return 0;
1365 }
1366
1367 if (cmd != DMA_TERMINATE_ALL)
1368 return -ENXIO;
1369
1370 /* The remainder of this function terminates the transfer */
1371 coh901318_pause(chan);
1372 spin_lock_irqsave(&cohc->lock, flags);
1373
1374 /* Clear any pending BE or TC interrupt */
1375 if (cohc->id < 32) {
1376 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1377 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1378 } else {
1379 writel(1 << (cohc->id - 32), virtbase +
1380 COH901318_BE_INT_CLEAR2);
1381 writel(1 << (cohc->id - 32), virtbase +
1382 COH901318_TC_INT_CLEAR2);
1383 }
1384
1385 enable_powersave(cohc);
1386
1387 while ((cohd = coh901318_first_active_get(cohc))) {
1388 /* release the lli allocation*/
1389 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1390
1391 /* return desc to free-list */
1392 coh901318_desc_remove(cohd);
1393 coh901318_desc_free(cohc, cohd);
1394 }
1395
1396 while ((cohd = coh901318_first_queued(cohc))) {
1397 /* release the lli allocation*/
1398 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1399
1400 /* return desc to free-list */
1401 coh901318_desc_remove(cohd);
1402 coh901318_desc_free(cohc, cohd);
1403 }
1404
1405
1406 cohc->nbr_active_done = 0;
1407 cohc->busy = 0;
1408
1409 spin_unlock_irqrestore(&cohc->lock, flags);
1410
1411 return 0;
1412 }
1413
1414 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1415 struct coh901318_base *base)
1416 {
1417 int chans_i;
1418 int i = 0;
1419 struct coh901318_chan *cohc;
1420
1421 INIT_LIST_HEAD(&dma->channels);
1422
1423 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1424 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1425 cohc = &base->chans[i];
1426
1427 cohc->base = base;
1428 cohc->chan.device = dma;
1429 cohc->id = i;
1430
1431 /* TODO: do we really need this lock if only one
1432 * client is connected to each channel?
1433 */
1434
1435 spin_lock_init(&cohc->lock);
1436
1437 cohc->nbr_active_done = 0;
1438 cohc->busy = 0;
1439 INIT_LIST_HEAD(&cohc->free);
1440 INIT_LIST_HEAD(&cohc->active);
1441 INIT_LIST_HEAD(&cohc->queue);
1442
1443 tasklet_init(&cohc->tasklet, dma_tasklet,
1444 (unsigned long) cohc);
1445
1446 list_add_tail(&cohc->chan.device_node,
1447 &dma->channels);
1448 }
1449 }
1450 }
1451
1452 static int __init coh901318_probe(struct platform_device *pdev)
1453 {
1454 int err = 0;
1455 struct coh901318_platform *pdata;
1456 struct coh901318_base *base;
1457 int irq;
1458 struct resource *io;
1459
1460 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1461 if (!io)
1462 goto err_get_resource;
1463
1464 /* Map DMA controller registers to virtual memory */
1465 if (request_mem_region(io->start,
1466 resource_size(io),
1467 pdev->dev.driver->name) == NULL) {
1468 err = -EBUSY;
1469 goto err_request_mem;
1470 }
1471
1472 pdata = pdev->dev.platform_data;
1473 if (!pdata)
1474 goto err_no_platformdata;
1475
1476 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1477 pdata->max_channels *
1478 sizeof(struct coh901318_chan),
1479 GFP_KERNEL);
1480 if (!base)
1481 goto err_alloc_coh_dma_channels;
1482
1483 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1484
1485 base->virtbase = ioremap(io->start, resource_size(io));
1486 if (!base->virtbase) {
1487 err = -ENOMEM;
1488 goto err_no_ioremap;
1489 }
1490
1491 base->dev = &pdev->dev;
1492 base->platform = pdata;
1493 spin_lock_init(&base->pm.lock);
1494 base->pm.started_channels = 0;
1495
1496 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1497
1498 platform_set_drvdata(pdev, base);
1499
1500 irq = platform_get_irq(pdev, 0);
1501 if (irq < 0)
1502 goto err_no_irq;
1503
1504 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1505 "coh901318", base);
1506 if (err) {
1507 dev_crit(&pdev->dev,
1508 "Cannot allocate IRQ for DMA controller!\n");
1509 goto err_request_irq;
1510 }
1511
1512 err = coh901318_pool_create(&base->pool, &pdev->dev,
1513 sizeof(struct coh901318_lli),
1514 32);
1515 if (err)
1516 goto err_pool_create;
1517
1518 /* init channels for device transfers */
1519 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1520 base);
1521
1522 dma_cap_zero(base->dma_slave.cap_mask);
1523 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1524
1525 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1526 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1527 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1528 base->dma_slave.device_tx_status = coh901318_tx_status;
1529 base->dma_slave.device_issue_pending = coh901318_issue_pending;
1530 base->dma_slave.device_control = coh901318_control;
1531 base->dma_slave.dev = &pdev->dev;
1532
1533 err = dma_async_device_register(&base->dma_slave);
1534
1535 if (err)
1536 goto err_register_slave;
1537
1538 /* init channels for memcpy */
1539 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1540 base);
1541
1542 dma_cap_zero(base->dma_memcpy.cap_mask);
1543 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1544
1545 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1546 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1547 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1548 base->dma_memcpy.device_tx_status = coh901318_tx_status;
1549 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1550 base->dma_memcpy.device_control = coh901318_control;
1551 base->dma_memcpy.dev = &pdev->dev;
1552 /*
1553 * This controller can only access address at even 32bit boundaries,
1554 * i.e. 2^2
1555 */
1556 base->dma_memcpy.copy_align = 2;
1557 err = dma_async_device_register(&base->dma_memcpy);
1558
1559 if (err)
1560 goto err_register_memcpy;
1561
1562 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1563 (u32) base->virtbase);
1564
1565 return err;
1566
1567 err_register_memcpy:
1568 dma_async_device_unregister(&base->dma_slave);
1569 err_register_slave:
1570 coh901318_pool_destroy(&base->pool);
1571 err_pool_create:
1572 free_irq(platform_get_irq(pdev, 0), base);
1573 err_request_irq:
1574 err_no_irq:
1575 iounmap(base->virtbase);
1576 err_no_ioremap:
1577 kfree(base);
1578 err_alloc_coh_dma_channels:
1579 err_no_platformdata:
1580 release_mem_region(pdev->resource->start,
1581 resource_size(pdev->resource));
1582 err_request_mem:
1583 err_get_resource:
1584 return err;
1585 }
1586
1587 static int __exit coh901318_remove(struct platform_device *pdev)
1588 {
1589 struct coh901318_base *base = platform_get_drvdata(pdev);
1590
1591 dma_async_device_unregister(&base->dma_memcpy);
1592 dma_async_device_unregister(&base->dma_slave);
1593 coh901318_pool_destroy(&base->pool);
1594 free_irq(platform_get_irq(pdev, 0), base);
1595 iounmap(base->virtbase);
1596 kfree(base);
1597 release_mem_region(pdev->resource->start,
1598 resource_size(pdev->resource));
1599 return 0;
1600 }
1601
1602
1603 static struct platform_driver coh901318_driver = {
1604 .remove = __exit_p(coh901318_remove),
1605 .driver = {
1606 .name = "coh901318",
1607 },
1608 };
1609
1610 int __init coh901318_init(void)
1611 {
1612 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1613 }
1614 subsys_initcall(coh901318_init);
1615
1616 void __exit coh901318_exit(void)
1617 {
1618 platform_driver_unregister(&coh901318_driver);
1619 }
1620 module_exit(coh901318_exit);
1621
1622 MODULE_LICENSE("GPL");
1623 MODULE_AUTHOR("Per Friden");
Linux with added FPC-III support