arch/mips/powertv/powertv-usb.c

   1 /*
   2  *                              powertv-usb.c
   3  *
   4  * Description:  ASIC-specific USB device setup and shutdown
   5  *
   6  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
   7  * Copyright (C) 2009 Cisco Systems, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  *
  23  * Author:       Ken Eppinett
  24  *               David Schleef <ds@schleef.org>
  25  *
  26  * NOTE: The bootloader allocates persistent memory at an address which is
  27  * 16 MiB below the end of the highest address in KSEG0. All fixed
  28  * address memory reservations must avoid this region.
  29  */
  30
  31 #include <linux/kernel.h>
  32 #include <linux/export.h>
  33 #include <linux/ioport.h>
  34 #include <linux/platform_device.h>
  35 #include <asm/mach-powertv/asic.h>
  36 #include <asm/mach-powertv/interrupts.h>
  37
  38 /* misc_clk_ctl1 values */
  39 #define MCC1_30MHZ_POWERUP_SELECT       (1 << 14)
  40 #define MCC1_DIV9                       (1 << 13)
  41 #define MCC1_ETHMIPS_POWERUP_SELECT     (1 << 11)
  42 #define MCC1_USB_POWERUP_SELECT         (1 << 1)
  43 #define MCC1_CLOCK108_POWERUP_SELECT    (1 << 0)
  44
  45 /* Possible values for clock select */
  46 #define MCC1_USB_CLOCK_HIGH_Z           (0 << 4)
  47 #define MCC1_USB_CLOCK_48MHZ            (1 << 4)
  48 #define MCC1_USB_CLOCK_24MHZ            (2 << 4)
  49 #define MCC1_USB_CLOCK_6MHZ             (3 << 4)
  50
  51 #define MCC1_CONFIG     (MCC1_30MHZ_POWERUP_SELECT |            \
  52                          MCC1_DIV9 |                            \
  53                          MCC1_ETHMIPS_POWERUP_SELECT |          \
  54                          MCC1_USB_POWERUP_SELECT |              \
  55                          MCC1_CLOCK108_POWERUP_SELECT)
  56
  57 /* misc_clk_ctl2 values */
  58 #define MCC2_GMII_GCLK_TO_PAD           (1 << 31)
  59 #define MCC2_ETHER125_0_CLOCK_SELECT    (1 << 29)
  60 #define MCC2_RMII_0_CLOCK_SELECT        (1 << 28)
  61 #define MCC2_GMII_TX0_CLOCK_SELECT      (1 << 27)
  62 #define MCC2_GMII_RX0_CLOCK_SELECT      (1 << 26)
  63 #define MCC2_ETHER125_1_CLOCK_SELECT    (1 << 24)
  64 #define MCC2_RMII_1_CLOCK_SELECT        (1 << 23)
  65 #define MCC2_GMII_TX1_CLOCK_SELECT      (1 << 22)
  66 #define MCC2_GMII_RX1_CLOCK_SELECT      (1 << 21)
  67 #define MCC2_ETHER125_2_CLOCK_SELECT    (1 << 19)
  68 #define MCC2_RMII_2_CLOCK_SELECT        (1 << 18)
  69 #define MCC2_GMII_TX2_CLOCK_SELECT      (1 << 17)
  70 #define MCC2_GMII_RX2_CLOCK_SELECT      (1 << 16)
  71
  72 #define ETHER_CLK_CONFIG        (MCC2_GMII_GCLK_TO_PAD |        \
  73                                  MCC2_ETHER125_0_CLOCK_SELECT | \
  74                                  MCC2_RMII_0_CLOCK_SELECT |     \
  75                                  MCC2_GMII_TX0_CLOCK_SELECT |   \
  76                                  MCC2_GMII_RX0_CLOCK_SELECT |   \
  77                                  MCC2_ETHER125_1_CLOCK_SELECT | \
  78                                  MCC2_RMII_1_CLOCK_SELECT |     \
  79                                  MCC2_GMII_TX1_CLOCK_SELECT |   \
  80                                  MCC2_GMII_RX1_CLOCK_SELECT |   \
  81                                  MCC2_ETHER125_2_CLOCK_SELECT | \
  82                                  MCC2_RMII_2_CLOCK_SELECT |     \
  83                                  MCC2_GMII_TX2_CLOCK_SELECT |   \
  84                                  MCC2_GMII_RX2_CLOCK_SELECT)
  85
  86 /* misc_clk_ctl2 definitions for Gaia */
  87 #define FSX4A_REF_SELECT                (1 << 16)
  88 #define FSX4B_REF_SELECT                (1 << 17)
  89 #define FSX4C_REF_SELECT                (1 << 18)
  90 #define DDR_PLL_REF_SELECT              (1 << 19)
  91 #define MIPS_PLL_REF_SELECT             (1 << 20)
  92
  93 /* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
  94 #define QAM_FS_SDIV_SHIFT               29
  95 #define QAM_FS_MD_SHIFT                 24
  96 #define QAM_FS_MD_MASK                  0x1f    /* Cut down to 5 bits */
  97 #define QAM_FS_PE_SHIFT                 8
  98
  99 #define QAM_FS_DISABLE_DIVIDE_BY_3              (1 << 5)
 100 #define QAM_FS_ENABLE_PROGRAM                   (1 << 4)
 101 #define QAM_FS_ENABLE_OUTPUT                    (1 << 3)
 102 #define QAM_FS_SELECT_TEST_BYPASS               (1 << 2)
 103 #define QAM_FS_DISABLE_DIGITAL_STANDBY          (1 << 1)
 104 #define QAM_FS_CHOOSE_FS                        (1 << 0)
 105
 106 /* Definitions for fs432x4a_ctl register */
 107 #define QAM_FS_NSDIV_54MHZ                      (1 << 2)
 108
 109 /* Definitions for bcm1_usb2_ctl register */
 110 #define BCM1_USB2_CTL_BISTOK                            (1 << 11)
 111 #define BCM1_USB2_CTL_PORT2_SHIFT_JK                    (1 << 7)
 112 #define BCM1_USB2_CTL_PORT1_SHIFT_JK                    (1 << 6)
 113 #define BCM1_USB2_CTL_PORT2_FAST_EDGE                   (1 << 5)
 114 #define BCM1_USB2_CTL_PORT1_FAST_EDGE                   (1 << 4)
 115 #define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH          (1 << 1)
 116 #define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH     (1 << 0)
 117
 118 /* Definitions for crt_spare register */
 119 #define CRT_SPARE_PORT2_SHIFT_JK                        (1 << 21)
 120 #define CRT_SPARE_PORT1_SHIFT_JK                        (1 << 20)
 121 #define CRT_SPARE_PORT2_FAST_EDGE                       (1 << 19)
 122 #define CRT_SPARE_PORT1_FAST_EDGE                       (1 << 18)
 123 #define CRT_SPARE_DIVIDE_BY_9_FROM_432                  (1 << 17)
 124 #define CRT_SPARE_USB_DIVIDE_BY_9                       (1 << 16)
 125
 126 /* Definitions for usb2_stbus_obc register */
 127 #define USB_STBUS_OBC_STORE32_LOAD32                    0x3
 128
 129 /* Definitions for usb2_stbus_mess_size register */
 130 #define USB2_STBUS_MESS_SIZE_2                          0x1     /* 2 packets */
 131
 132 /* Definitions for usb2_stbus_chunk_size register */
 133 #define USB2_STBUS_CHUNK_SIZE_2                         0x1     /* 2 packets */
 134
 135 /* Definitions for usb2_strap register */
 136 #define USB2_STRAP_HFREQ_SELECT                         0x1
 137
 138 /*
 139  * USB Host Resource Definition
 140  */
 141
 142 static struct resource ehci_resources[] = {
 143         {
 144                 .parent = &asic_resource,
 145                 .start  = 0,
 146                 .end    = 0xff,
 147                 .flags  = IORESOURCE_MEM,
 148         },
 149         {
 150                 .start  = irq_usbehci,
 151                 .end    = irq_usbehci,
 152                 .flags  = IORESOURCE_IRQ,
 153         },
 154 };
 155
 156 static u64 ehci_dmamask = 0xffffffffULL;
 157
 158 static struct platform_device ehci_device = {
 159         .name = "powertv-ehci",
 160         .id = 0,
 161         .num_resources = 2,
 162         .resource = ehci_resources,
 163         .dev = {
 164                 .dma_mask = &ehci_dmamask,
 165                 .coherent_dma_mask = 0xffffffff,
 166         },
 167 };
 168
 169 static struct resource ohci_resources[] = {
 170         {
 171                 .parent = &asic_resource,
 172                 .start  = 0,
 173                 .end    = 0xff,
 174                 .flags  = IORESOURCE_MEM,
 175         },
 176         {
 177                 .start  = irq_usbohci,
 178                 .end    = irq_usbohci,
 179                 .flags  = IORESOURCE_IRQ,
 180         },
 181 };
 182
 183 static u64 ohci_dmamask = 0xffffffffULL;
 184
 185 static struct platform_device ohci_device = {
 186         .name = "powertv-ohci",
 187         .id = 0,
 188         .num_resources = 2,
 189         .resource = ohci_resources,
 190         .dev = {
 191                 .dma_mask = &ohci_dmamask,
 192                 .coherent_dma_mask = 0xffffffff,
 193         },
 194 };
 195
 196 static unsigned usb_users;
 197 static DEFINE_SPINLOCK(usb_regs_lock);
 198
 199 /*
 200  *
 201  * fs_update - set frequency synthesizer for USB
 202  * @pe_bits             Phase tap setting
 203  * @md_bits             Coarse selector bus for algorithm of phase tap
 204  * @sdiv_bits           Output divider setting
 205  * @disable_div_by_3    Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
 206  * @standby             Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
 207  *
 208  * QAM frequency selection code, which affects the frequency at which USB
 209  * runs. The frequency is calculated as:
 210  *                             2^15 * ndiv * Fin
 211  * Fout = ------------------------------------------------------------
 212  *        (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
 213  * where:
 214  * Fin          54 MHz
 215  * ndiv         QAM_FS_NSDIV_54MHZ ? 8 : 16
 216  * sdiv         1 << (sdiv_bits + 1)
 217  * ipe          Same as pe_bits
 218  * md           A five-bit, two's-complement integer (range [-16, 15]), which
 219  *              is the lower 5 bits of md_bits.
 220  */
 221 static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
 222         u32 disable_div_by_3, u32 standby)
 223 {
 224         u32 val;
 225
 226         val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
 227                 ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
 228                 (pe_bits << QAM_FS_PE_SHIFT) |
 229                 QAM_FS_ENABLE_OUTPUT |
 230                 standby |
 231                 disable_div_by_3);
 232         asic_write(val, fs432x4b4_usb_ctl);
 233         asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
 234         asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
 235                 fs432x4b4_usb_ctl);
 236 }
 237
 238 /*
 239  * usb_eye_configure - for optimizing the shape USB eye waveform
 240  * @set:        Bits to set in the register
 241  * @clear:      Bits to clear in the register; each bit with a one will
 242  *              be set in the register, zero bits will not be modified
 243  */
 244 static void usb_eye_configure(u32 set, u32 clear)
 245 {
 246         u32 old;
 247
 248         old = asic_read(crt_spare);
 249         old |= set;
 250         old &= ~clear;
 251         asic_write(old, crt_spare);
 252 }
 253
 254 /*
 255  * platform_configure_usb - usb configuration based on platform type.
 256  */
 257 static void platform_configure_usb(void)
 258 {
 259         u32 bcm1_usb2_ctl_value;
 260         enum asic_type asic_type;
 261         unsigned long flags;
 262
 263         spin_lock_irqsave(&usb_regs_lock, flags);
 264         usb_users++;
 265
 266         if (usb_users != 1) {
 267                 spin_unlock_irqrestore(&usb_regs_lock, flags);
 268                 return;
 269         }
 270
 271         asic_type = platform_get_asic();
 272
 273         switch (asic_type) {
 274         case ASIC_ZEUS:
 275                 fs_update(0x0000, -15, 0x02, 0, 0);
 276                 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
 277                         BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
 278                 break;
 279
 280         case ASIC_CRONUS:
 281         case ASIC_CRONUSLITE:
 282                 usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
 283                 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
 284                         QAM_FS_DISABLE_DIGITAL_STANDBY);
 285                 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
 286                         BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
 287                 break;
 288
 289         case ASIC_CALLIOPE:
 290                 fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
 291                         QAM_FS_DISABLE_DIGITAL_STANDBY);
 292
 293                 switch (platform_get_family()) {
 294                 case FAMILY_1500VZE:
 295                         break;
 296
 297                 case FAMILY_1500VZF:
 298                         usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
 299                                 CRT_SPARE_PORT1_SHIFT_JK |
 300                                 CRT_SPARE_PORT2_FAST_EDGE |
 301                                 CRT_SPARE_PORT1_FAST_EDGE, 0);
 302                         break;
 303
 304                 default:
 305                         usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
 306                                 CRT_SPARE_PORT1_SHIFT_JK, 0);
 307                         break;
 308                 }
 309
 310                 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
 311                         BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
 312                         BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
 313                 break;
 314
 315         case ASIC_GAIA:
 316                 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
 317                         QAM_FS_DISABLE_DIGITAL_STANDBY);
 318                 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
 319                         BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
 320                         BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
 321                 break;
 322
 323         default:
 324                 pr_err("Unknown ASIC type: %d\n", asic_type);
 325                 bcm1_usb2_ctl_value = 0;
 326                 break;
 327         }
 328
 329         /* turn on USB power */
 330         asic_write(0, usb2_strap);
 331         /* Enable all OHCI interrupts */
 332         asic_write(bcm1_usb2_ctl_value, usb2_control);
 333         /* usb2_stbus_obc store32/load32 */
 334         asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
 335         /* usb2_stbus_mess_size 2 packets */
 336         asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
 337         /* usb2_stbus_chunk_size 2 packets */
 338         asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
 339         spin_unlock_irqrestore(&usb_regs_lock, flags);
 340 }
 341
 342 static void platform_unconfigure_usb(void)
 343 {
 344         unsigned long flags;
 345
 346         spin_lock_irqsave(&usb_regs_lock, flags);
 347         usb_users--;
 348         if (usb_users == 0)
 349                 asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
 350         spin_unlock_irqrestore(&usb_regs_lock, flags);
 351 }
 352
 353 /*
 354  * Set up the USB EHCI interface
 355  */
 356 void platform_configure_usb_ehci()
 357 {
 358         platform_configure_usb();
 359 }
 360 EXPORT_SYMBOL(platform_configure_usb_ehci);
 361
 362 /*
 363  * Set up the USB OHCI interface
 364  */
 365 void platform_configure_usb_ohci()
 366 {
 367         platform_configure_usb();
 368 }
 369 EXPORT_SYMBOL(platform_configure_usb_ohci);
 370
 371 /*
 372  * Shut the USB EHCI interface down
 373  */
 374 void platform_unconfigure_usb_ehci()
 375 {
 376         platform_unconfigure_usb();
 377 }
 378 EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
 379
 380 /*
 381  * Shut the USB OHCI interface down
 382  */
 383 void platform_unconfigure_usb_ohci()
 384 {
 385         platform_unconfigure_usb();
 386 }
 387 EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
 388
 389 /**
 390  * platform_devices_init - sets up USB device resourse.
 391  */
 392 int __init platform_usb_devices_init(struct platform_device **ehci_dev,
 393         struct platform_device **ohci_dev)
 394 {
 395         *ehci_dev = &ehci_device;
 396         ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
 397         ehci_resources[0].end += ehci_resources[0].start;
 398
 399         *ohci_dev = &ohci_device;
 400         ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
 401         ohci_resources[0].end += ohci_resources[0].start;
 402
 403         return 0;
 404 }