drivers/clk/renesas/rcar-gen2-cpg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R-Car Gen2 Clock Pulse Generator
   4  *
   5  * Copyright (C) 2016 Cogent Embedded Inc.
   6  */
   7
   8 #include <linux/bug.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/sys_soc.h>
  17
  18 #include "renesas-cpg-mssr.h"
  19 #include "rcar-gen2-cpg.h"
  20
  21 #define CPG_FRQCRB              0x0004
  22 #define CPG_FRQCRB_KICK         BIT(31)
  23 #define CPG_SDCKCR              0x0074
  24 #define CPG_PLL0CR              0x00d8
  25 #define CPG_PLL0CR_STC_SHIFT    24
  26 #define CPG_PLL0CR_STC_MASK     (0x7f << CPG_PLL0CR_STC_SHIFT)
  27 #define CPG_FRQCRC              0x00e0
  28 #define CPG_FRQCRC_ZFC_SHIFT    8
  29 #define CPG_FRQCRC_ZFC_MASK     (0x1f << CPG_FRQCRC_ZFC_SHIFT)
  30 #define CPG_ADSPCKCR            0x025c
  31 #define CPG_RCANCKCR            0x0270
  32
  33 static spinlock_t cpg_lock;
  34
  35 /*
  36  * Z Clock
  37  *
  38  * Traits of this clock:
  39  * prepare - clk_prepare only ensures that parents are prepared
  40  * enable - clk_enable only ensures that parents are enabled
  41  * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
  42  * parent - fixed parent.  No clk_set_parent support
  43  */
  44
  45 struct cpg_z_clk {
  46         struct clk_hw hw;
  47         void __iomem *reg;
  48         void __iomem *kick_reg;
  49 };
  50
  51 #define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)
  52
  53 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
  54                                            unsigned long parent_rate)
  55 {
  56         struct cpg_z_clk *zclk = to_z_clk(hw);
  57         unsigned int mult;
  58         unsigned int val;
  59
  60         val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
  61         mult = 32 - val;
  62
  63         return div_u64((u64)parent_rate * mult, 32);
  64 }
  65
  66 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  67                                  unsigned long *parent_rate)
  68 {
  69         unsigned long prate  = *parent_rate;
  70         unsigned int mult;
  71
  72         if (!prate)
  73                 prate = 1;
  74
  75         mult = div_u64((u64)rate * 32, prate);
  76         mult = clamp(mult, 1U, 32U);
  77
  78         return *parent_rate / 32 * mult;
  79 }
  80
  81 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  82                               unsigned long parent_rate)
  83 {
  84         struct cpg_z_clk *zclk = to_z_clk(hw);
  85         unsigned int mult;
  86         u32 val, kick;
  87         unsigned int i;
  88
  89         mult = div_u64((u64)rate * 32, parent_rate);
  90         mult = clamp(mult, 1U, 32U);
  91
  92         if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
  93                 return -EBUSY;
  94
  95         val = readl(zclk->reg);
  96         val &= ~CPG_FRQCRC_ZFC_MASK;
  97         val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
  98         writel(val, zclk->reg);
  99
 100         /*
 101          * Set KICK bit in FRQCRB to update hardware setting and wait for
 102          * clock change completion.
 103          */
 104         kick = readl(zclk->kick_reg);
 105         kick |= CPG_FRQCRB_KICK;
 106         writel(kick, zclk->kick_reg);
 107
 108         /*
 109          * Note: There is no HW information about the worst case latency.
 110          *
 111          * Using experimental measurements, it seems that no more than
 112          * ~10 iterations are needed, independently of the CPU rate.
 113          * Since this value might be dependent on external xtal rate, pll1
 114          * rate or even the other emulation clocks rate, use 1000 as a
 115          * "super" safe value.
 116          */
 117         for (i = 1000; i; i--) {
 118                 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
 119                         return 0;
 120
 121                 cpu_relax();
 122         }
 123
 124         return -ETIMEDOUT;
 125 }
 126
 127 static const struct clk_ops cpg_z_clk_ops = {
 128         .recalc_rate = cpg_z_clk_recalc_rate,
 129         .round_rate = cpg_z_clk_round_rate,
 130         .set_rate = cpg_z_clk_set_rate,
 131 };
 132
 133 static struct clk * __init cpg_z_clk_register(const char *name,
 134                                               const char *parent_name,
 135                                               void __iomem *base)
 136 {
 137         struct clk_init_data init;
 138         struct cpg_z_clk *zclk;
 139         struct clk *clk;
 140
 141         zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
 142         if (!zclk)
 143                 return ERR_PTR(-ENOMEM);
 144
 145         init.name = name;
 146         init.ops = &cpg_z_clk_ops;
 147         init.flags = 0;
 148         init.parent_names = &parent_name;
 149         init.num_parents = 1;
 150
 151         zclk->reg = base + CPG_FRQCRC;
 152         zclk->kick_reg = base + CPG_FRQCRB;
 153         zclk->hw.init = &init;
 154
 155         clk = clk_register(NULL, &zclk->hw);
 156         if (IS_ERR(clk))
 157                 kfree(zclk);
 158
 159         return clk;
 160 }
 161
 162 static struct clk * __init cpg_rcan_clk_register(const char *name,
 163                                                  const char *parent_name,
 164                                                  void __iomem *base)
 165 {
 166         struct clk_fixed_factor *fixed;
 167         struct clk_gate *gate;
 168         struct clk *clk;
 169
 170         fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
 171         if (!fixed)
 172                 return ERR_PTR(-ENOMEM);
 173
 174         fixed->mult = 1;
 175         fixed->div = 6;
 176
 177         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 178         if (!gate) {
 179                 kfree(fixed);
 180                 return ERR_PTR(-ENOMEM);
 181         }
 182
 183         gate->reg = base + CPG_RCANCKCR;
 184         gate->bit_idx = 8;
 185         gate->flags = CLK_GATE_SET_TO_DISABLE;
 186         gate->lock = &cpg_lock;
 187
 188         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 189                                      &fixed->hw, &clk_fixed_factor_ops,
 190                                      &gate->hw, &clk_gate_ops, 0);
 191         if (IS_ERR(clk)) {
 192                 kfree(gate);
 193                 kfree(fixed);
 194         }
 195
 196         return clk;
 197 }
 198
 199 /* ADSP divisors */
 200 static const struct clk_div_table cpg_adsp_div_table[] = {
 201         {  1,  3 }, {  2,  4 }, {  3,  6 }, {  4,  8 },
 202         {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
 203         { 10, 36 }, { 11, 48 }, {  0,  0 },
 204 };
 205
 206 static struct clk * __init cpg_adsp_clk_register(const char *name,
 207                                                  const char *parent_name,
 208                                                  void __iomem *base)
 209 {
 210         struct clk_divider *div;
 211         struct clk_gate *gate;
 212         struct clk *clk;
 213
 214         div = kzalloc(sizeof(*div), GFP_KERNEL);
 215         if (!div)
 216                 return ERR_PTR(-ENOMEM);
 217
 218         div->reg = base + CPG_ADSPCKCR;
 219         div->width = 4;
 220         div->table = cpg_adsp_div_table;
 221         div->lock = &cpg_lock;
 222
 223         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 224         if (!gate) {
 225                 kfree(div);
 226                 return ERR_PTR(-ENOMEM);
 227         }
 228
 229         gate->reg = base + CPG_ADSPCKCR;
 230         gate->bit_idx = 8;
 231         gate->flags = CLK_GATE_SET_TO_DISABLE;
 232         gate->lock = &cpg_lock;
 233
 234         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 235                                      &div->hw, &clk_divider_ops,
 236                                      &gate->hw, &clk_gate_ops, 0);
 237         if (IS_ERR(clk)) {
 238                 kfree(gate);
 239                 kfree(div);
 240         }
 241
 242         return clk;
 243 }
 244
 245 /* SDHI divisors */
 246 static const struct clk_div_table cpg_sdh_div_table[] = {
 247         {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
 248         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
 249         {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
 250 };
 251
 252 static const struct clk_div_table cpg_sd01_div_table[] = {
 253         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
 254         {  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
 255         {  0,  0 },
 256 };
 257
 258 static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
 259 static unsigned int cpg_pll0_div __initdata;
 260 static u32 cpg_mode __initdata;
 261 static u32 cpg_quirks __initdata;
 262
 263 #define SD_SKIP_FIRST   BIT(0)          /* Skip first clock in SD table */
 264
 265 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 266         {
 267                 .soc_id = "r8a77470",
 268                 .data = (void *)SD_SKIP_FIRST,
 269         },
 270         { /* sentinel */ }
 271 };
 272
 273 struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 274         const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
 275         struct clk **clks, void __iomem *base,
 276         struct raw_notifier_head *notifiers)
 277 {
 278         const struct clk_div_table *table = NULL;
 279         const struct clk *parent;
 280         const char *parent_name;
 281         unsigned int mult = 1;
 282         unsigned int div = 1;
 283         unsigned int shift;
 284
 285         parent = clks[core->parent];
 286         if (IS_ERR(parent))
 287                 return ERR_CAST(parent);
 288
 289         parent_name = __clk_get_name(parent);
 290
 291         switch (core->type) {
 292         /* R-Car Gen2 */
 293         case CLK_TYPE_GEN2_MAIN:
 294                 div = cpg_pll_config->extal_div;
 295                 break;
 296
 297         case CLK_TYPE_GEN2_PLL0:
 298                 /*
 299                  * PLL0 is a  configurable multiplier clock except on R-Car
 300                  * V2H/E2. Register the PLL0 clock as a fixed factor clock for
 301                  * now as there's no generic multiplier clock implementation and
 302                  * we  currently  have no need to change  the multiplier value.
 303                  */
 304                 mult = cpg_pll_config->pll0_mult;
 305                 div  = cpg_pll0_div;
 306                 if (!mult) {
 307                         u32 pll0cr = readl(base + CPG_PLL0CR);
 308
 309                         mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
 310                                  CPG_PLL0CR_STC_SHIFT) + 1) * 2;
 311                 }
 312                 break;
 313
 314         case CLK_TYPE_GEN2_PLL1:
 315                 mult = cpg_pll_config->pll1_mult / 2;
 316                 break;
 317
 318         case CLK_TYPE_GEN2_PLL3:
 319                 mult = cpg_pll_config->pll3_mult;
 320                 break;
 321
 322         case CLK_TYPE_GEN2_Z:
 323                 return cpg_z_clk_register(core->name, parent_name, base);
 324
 325         case CLK_TYPE_GEN2_LB:
 326                 div = cpg_mode & BIT(18) ? 36 : 24;
 327                 break;
 328
 329         case CLK_TYPE_GEN2_ADSP:
 330                 return cpg_adsp_clk_register(core->name, parent_name, base);
 331
 332         case CLK_TYPE_GEN2_SDH:
 333                 table = cpg_sdh_div_table;
 334                 shift = 8;
 335                 break;
 336
 337         case CLK_TYPE_GEN2_SD0:
 338                 table = cpg_sd01_div_table;
 339                 if (cpg_quirks & SD_SKIP_FIRST)
 340                         table++;
 341
 342                 shift = 4;
 343                 break;
 344
 345         case CLK_TYPE_GEN2_SD1:
 346                 table = cpg_sd01_div_table;
 347                 if (cpg_quirks & SD_SKIP_FIRST)
 348                         table++;
 349
 350                 shift = 0;
 351                 break;
 352
 353         case CLK_TYPE_GEN2_QSPI:
 354                 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
 355                       8 : 10;
 356                 break;
 357
 358         case CLK_TYPE_GEN2_RCAN:
 359                 return cpg_rcan_clk_register(core->name, parent_name, base);
 360
 361         default:
 362                 return ERR_PTR(-EINVAL);
 363         }
 364
 365         if (!table)
 366                 return clk_register_fixed_factor(NULL, core->name, parent_name,
 367                                                  0, mult, div);
 368         else
 369                 return clk_register_divider_table(NULL, core->name,
 370                                                   parent_name, 0,
 371                                                   base + CPG_SDCKCR, shift, 4,
 372                                                   0, table, &cpg_lock);
 373 }
 374
 375 int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
 376                               unsigned int pll0_div, u32 mode)
 377 {
 378         const struct soc_device_attribute *attr;
 379
 380         cpg_pll_config = config;
 381         cpg_pll0_div = pll0_div;
 382         cpg_mode = mode;
 383         attr = soc_device_match(cpg_quirks_match);
 384         if (attr)
 385                 cpg_quirks = (uintptr_t)attr->data;
 386         pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
 387
 388         spin_lock_init(&cpg_lock);
 389
 390         return 0;
 391 }