drivers/scsi/ipr.h

   1 /*
   2  * ipr.h -- driver for IBM Power Linux RAID adapters
   3  *
   4  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
   5  *
   6  * Copyright (C) 2003, 2004 IBM Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
  23  *                              that broke 64bit platforms.
  24  */
  25
  26 #ifndef _IPR_H
  27 #define _IPR_H
  28
  29 #include <asm/unaligned.h>
  30 #include <linux/types.h>
  31 #include <linux/completion.h>
  32 #include <linux/libata.h>
  33 #include <linux/list.h>
  34 #include <linux/kref.h>
  35 #include <linux/irq_poll.h>
  36 #include <scsi/scsi.h>
  37 #include <scsi/scsi_cmnd.h>
  38
  39 /*
  40  * Literals
  41  */
  42 #define IPR_DRIVER_VERSION "2.6.3"
  43 #define IPR_DRIVER_DATE "(October 17, 2015)"
  44
  45 /*
  46  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  47  *      ops per device for devices not running tagged command queuing.
  48  *      This can be adjusted at runtime through sysfs device attributes.
  49  */
  50 #define IPR_MAX_CMD_PER_LUN                             6
  51 #define IPR_MAX_CMD_PER_ATA_LUN                 1
  52
  53 /*
  54  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  55  *      ops the mid-layer can send to the adapter.
  56  */
  57 #define IPR_NUM_BASE_CMD_BLKS                   (ioa_cfg->max_cmds)
  58
  59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E    0x0339
  60
  61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
  62 #define PCI_DEVICE_ID_IBM_CROCODILE             0x034A
  63
  64 #define IPR_SUBS_DEV_ID_2780    0x0264
  65 #define IPR_SUBS_DEV_ID_5702    0x0266
  66 #define IPR_SUBS_DEV_ID_5703    0x0278
  67 #define IPR_SUBS_DEV_ID_572E    0x028D
  68 #define IPR_SUBS_DEV_ID_573E    0x02D3
  69 #define IPR_SUBS_DEV_ID_573D    0x02D4
  70 #define IPR_SUBS_DEV_ID_571A    0x02C0
  71 #define IPR_SUBS_DEV_ID_571B    0x02BE
  72 #define IPR_SUBS_DEV_ID_571E    0x02BF
  73 #define IPR_SUBS_DEV_ID_571F    0x02D5
  74 #define IPR_SUBS_DEV_ID_572A    0x02C1
  75 #define IPR_SUBS_DEV_ID_572B    0x02C2
  76 #define IPR_SUBS_DEV_ID_572F    0x02C3
  77 #define IPR_SUBS_DEV_ID_574E    0x030A
  78 #define IPR_SUBS_DEV_ID_575B    0x030D
  79 #define IPR_SUBS_DEV_ID_575C    0x0338
  80 #define IPR_SUBS_DEV_ID_57B3    0x033A
  81 #define IPR_SUBS_DEV_ID_57B7    0x0360
  82 #define IPR_SUBS_DEV_ID_57B8    0x02C2
  83
  84 #define IPR_SUBS_DEV_ID_57B4    0x033B
  85 #define IPR_SUBS_DEV_ID_57B2    0x035F
  86 #define IPR_SUBS_DEV_ID_57C0    0x0352
  87 #define IPR_SUBS_DEV_ID_57C3    0x0353
  88 #define IPR_SUBS_DEV_ID_57C4    0x0354
  89 #define IPR_SUBS_DEV_ID_57C6    0x0357
  90 #define IPR_SUBS_DEV_ID_57CC    0x035C
  91
  92 #define IPR_SUBS_DEV_ID_57B5    0x033C
  93 #define IPR_SUBS_DEV_ID_57CE    0x035E
  94 #define IPR_SUBS_DEV_ID_57B1    0x0355
  95
  96 #define IPR_SUBS_DEV_ID_574D    0x0356
  97 #define IPR_SUBS_DEV_ID_57C8    0x035D
  98
  99 #define IPR_SUBS_DEV_ID_57D5    0x03FB
 100 #define IPR_SUBS_DEV_ID_57D6    0x03FC
 101 #define IPR_SUBS_DEV_ID_57D7    0x03FF
 102 #define IPR_SUBS_DEV_ID_57D8    0x03FE
 103 #define IPR_SUBS_DEV_ID_57D9    0x046D
 104 #define IPR_SUBS_DEV_ID_57DA    0x04CA
 105 #define IPR_SUBS_DEV_ID_57EB    0x0474
 106 #define IPR_SUBS_DEV_ID_57EC    0x0475
 107 #define IPR_SUBS_DEV_ID_57ED    0x0499
 108 #define IPR_SUBS_DEV_ID_57EE    0x049A
 109 #define IPR_SUBS_DEV_ID_57EF    0x049B
 110 #define IPR_SUBS_DEV_ID_57F0    0x049C
 111 #define IPR_SUBS_DEV_ID_2CCA    0x04C7
 112 #define IPR_SUBS_DEV_ID_2CD2    0x04C8
 113 #define IPR_SUBS_DEV_ID_2CCD    0x04C9
 114 #define IPR_NAME                                "ipr"
 115
 116 /*
 117  * Return codes
 118  */
 119 #define IPR_RC_JOB_CONTINUE             1
 120 #define IPR_RC_JOB_RETURN               2
 121
 122 /*
 123  * IOASCs
 124  */
 125 #define IPR_IOASC_NR_INIT_CMD_REQUIRED          0x02040200
 126 #define IPR_IOASC_NR_IOA_RESET_REQUIRED         0x02048000
 127 #define IPR_IOASC_SYNC_REQUIRED                 0x023f0000
 128 #define IPR_IOASC_MED_DO_NOT_REALLOC            0x03110C00
 129 #define IPR_IOASC_HW_SEL_TIMEOUT                        0x04050000
 130 #define IPR_IOASC_HW_DEV_BUS_STATUS                     0x04448500
 131 #define IPR_IOASC_IOASC_MASK                    0xFFFFFF00
 132 #define IPR_IOASC_SCSI_STATUS_MASK              0x000000FF
 133 #define IPR_IOASC_HW_CMD_FAILED                 0x046E0000
 134 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT    0x05240000
 135 #define IPR_IOASC_IR_RESOURCE_HANDLE            0x05250000
 136 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA         0x05258100
 137 #define IPR_IOASA_IR_DUAL_IOA_DISABLED          0x052C8000
 138 #define IPR_IOASC_BUS_WAS_RESET                 0x06290000
 139 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER                0x06298000
 140 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST      0x0B5A0000
 141 #define IPR_IOASC_IR_NON_OPTIMIZED              0x05258200
 142
 143 #define IPR_FIRST_DRIVER_IOASC                  0x10000000
 144 #define IPR_IOASC_IOA_WAS_RESET                 0x10000001
 145 #define IPR_IOASC_PCI_ACCESS_ERROR                      0x10000002
 146
 147 /* Driver data flags */
 148 #define IPR_USE_LONG_TRANSOP_TIMEOUT            0x00000001
 149 #define IPR_USE_PCI_WARM_RESET                  0x00000002
 150
 151 #define IPR_DEFAULT_MAX_ERROR_DUMP                      984
 152 #define IPR_NUM_LOG_HCAMS                               2
 153 #define IPR_NUM_CFG_CHG_HCAMS                           2
 154 #define IPR_NUM_HCAMS   (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
 155
 156 #define IPR_MAX_SIS64_TARGETS_PER_BUS                   1024
 157 #define IPR_MAX_SIS64_LUNS_PER_TARGET                   0xffffffff
 158
 159 #define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 160 #define IPR_MAX_NUM_LUNS_PER_TARGET                     256
 161 #define IPR_VSET_BUS                                    0xff
 162 #define IPR_IOA_BUS                                             0xff
 163 #define IPR_IOA_TARGET                                  0xff
 164 #define IPR_IOA_LUN                                             0xff
 165 #define IPR_MAX_NUM_BUSES                               16
 166
 167 #define IPR_NUM_RESET_RELOAD_RETRIES            3
 168
 169 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
 170 #define IPR_NUM_INTERNAL_CMD_BLKS       (IPR_NUM_HCAMS + \
 171                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 172
 173 #define IPR_MAX_COMMANDS                100
 174 #define IPR_NUM_CMD_BLKS                (IPR_NUM_BASE_CMD_BLKS + \
 175                                                 IPR_NUM_INTERNAL_CMD_BLKS)
 176
 177 #define IPR_MAX_PHYSICAL_DEVS                           192
 178 #define IPR_DEFAULT_SIS64_DEVS                          1024
 179 #define IPR_MAX_SIS64_DEVS                              4096
 180
 181 #define IPR_MAX_SGLIST                                  64
 182 #define IPR_IOA_MAX_SECTORS                             32767
 183 #define IPR_VSET_MAX_SECTORS                            512
 184 #define IPR_MAX_CDB_LEN                                 16
 185 #define IPR_MAX_HRRQ_RETRIES                            3
 186
 187 #define IPR_DEFAULT_BUS_WIDTH                           16
 188 #define IPR_80MBs_SCSI_RATE             ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 189 #define IPR_U160_SCSI_RATE      ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 190 #define IPR_U320_SCSI_RATE      ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 191 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
 192
 193 #define IPR_IOA_RES_HANDLE                              0xffffffff
 194 #define IPR_INVALID_RES_HANDLE                  0
 195 #define IPR_IOA_RES_ADDR                                0x00ffffff
 196
 197 /*
 198  * Adapter Commands
 199  */
 200 #define IPR_CANCEL_REQUEST                              0xC0
 201 #define IPR_CANCEL_64BIT_IOARCB                 0x01
 202 #define IPR_QUERY_RSRC_STATE                            0xC2
 203 #define IPR_RESET_DEVICE                                0xC3
 204 #define IPR_RESET_TYPE_SELECT                           0x80
 205 #define IPR_LUN_RESET                                   0x40
 206 #define IPR_TARGET_RESET                                        0x20
 207 #define IPR_BUS_RESET                                   0x10
 208 #define IPR_ATA_PHY_RESET                                       0x80
 209 #define IPR_ID_HOST_RR_Q                                0xC4
 210 #define IPR_QUERY_IOA_CONFIG                            0xC5
 211 #define IPR_CANCEL_ALL_REQUESTS                 0xCE
 212 #define IPR_HOST_CONTROLLED_ASYNC                       0xCF
 213 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE      0x01
 214 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA           0x02
 215 #define IPR_SET_SUPPORTED_DEVICES                       0xFB
 216 #define IPR_SET_ALL_SUPPORTED_DEVICES                   0x80
 217 #define IPR_IOA_SHUTDOWN                                0xF7
 218 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE                    0x05
 219 #define IPR_IOA_SERVICE_ACTION                          0xD2
 220
 221 /* IOA Service Actions */
 222 #define IPR_IOA_SA_CHANGE_CACHE_PARAMS                  0x14
 223
 224 /*
 225  * Timeouts
 226  */
 227 #define IPR_SHUTDOWN_TIMEOUT                    (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
 228 #define IPR_VSET_RW_TIMEOUT                     (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
 229 #define IPR_ABBREV_SHUTDOWN_TIMEOUT             (10 * HZ)
 230 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO   (2 * 60 * HZ)
 231 #define IPR_DEVICE_RESET_TIMEOUT                (ipr_fastfail ? 10 * HZ : 30 * HZ)
 232 #define IPR_CANCEL_TIMEOUT                      (ipr_fastfail ? 10 * HZ : 30 * HZ)
 233 #define IPR_CANCEL_ALL_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 234 #define IPR_ABORT_TASK_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 235 #define IPR_INTERNAL_TIMEOUT                    (ipr_fastfail ? 10 * HZ : 30 * HZ)
 236 #define IPR_WRITE_BUFFER_TIMEOUT                (30 * 60 * HZ)
 237 #define IPR_SET_SUP_DEVICE_TIMEOUT              (2 * 60 * HZ)
 238 #define IPR_REQUEST_SENSE_TIMEOUT               (10 * HZ)
 239 #define IPR_OPERATIONAL_TIMEOUT         (5 * 60)
 240 #define IPR_LONG_OPERATIONAL_TIMEOUT    (12 * 60)
 241 #define IPR_WAIT_FOR_RESET_TIMEOUT              (2 * HZ)
 242 #define IPR_CHECK_FOR_RESET_TIMEOUT             (HZ / 10)
 243 #define IPR_WAIT_FOR_BIST_TIMEOUT               (2 * HZ)
 244 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT  (120 * HZ)
 245 #define IPR_PCI_RESET_TIMEOUT                   (HZ / 2)
 246 #define IPR_SIS32_DUMP_TIMEOUT                  (15 * HZ)
 247 #define IPR_SIS64_DUMP_TIMEOUT                  (40 * HZ)
 248 #define IPR_DUMP_DELAY_SECONDS                  4
 249 #define IPR_DUMP_DELAY_TIMEOUT                  (IPR_DUMP_DELAY_SECONDS * HZ)
 250
 251 /*
 252  * SCSI Literals
 253  */
 254 #define IPR_VENDOR_ID_LEN                       8
 255 #define IPR_PROD_ID_LEN                         16
 256 #define IPR_SERIAL_NUM_LEN                      8
 257
 258 /*
 259  * Hardware literals
 260  */
 261 #define IPR_FMT2_MBX_ADDR_MASK                          0x0fffffff
 262 #define IPR_FMT2_MBX_BAR_SEL_MASK                       0xf0000000
 263 #define IPR_FMT2_MKR_BAR_SEL_SHIFT                      28
 264 #define IPR_GET_FMT2_BAR_SEL(mbx) \
 265 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
 266 #define IPR_SDT_FMT2_BAR0_SEL                           0x0
 267 #define IPR_SDT_FMT2_BAR1_SEL                           0x1
 268 #define IPR_SDT_FMT2_BAR2_SEL                           0x2
 269 #define IPR_SDT_FMT2_BAR3_SEL                           0x3
 270 #define IPR_SDT_FMT2_BAR4_SEL                           0x4
 271 #define IPR_SDT_FMT2_BAR5_SEL                           0x5
 272 #define IPR_SDT_FMT2_EXP_ROM_SEL                        0x8
 273 #define IPR_FMT2_SDT_READY_TO_USE                       0xC4D4E3F2
 274 #define IPR_FMT3_SDT_READY_TO_USE                       0xC4D4E3F3
 275 #define IPR_DOORBELL                                    0x82800000
 276 #define IPR_RUNTIME_RESET                               0x40000000
 277
 278 #define IPR_IPL_INIT_MIN_STAGE_TIME                     5
 279 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 30
 280 #define IPR_IPL_INIT_STAGE_UNKNOWN                      0x0
 281 #define IPR_IPL_INIT_STAGE_TRANSOP                      0xB0000000
 282 #define IPR_IPL_INIT_STAGE_MASK                         0xff000000
 283 #define IPR_IPL_INIT_STAGE_TIME_MASK                    0x0000ffff
 284 #define IPR_PCII_IPL_STAGE_CHANGE                       (0x80000000 >> 0)
 285
 286 #define IPR_PCII_MAILBOX_STABLE                         (0x80000000 >> 4)
 287 #define IPR_WAIT_FOR_MAILBOX                            (2 * HZ)
 288
 289 #define IPR_PCII_IOA_TRANS_TO_OPER                      (0x80000000 >> 0)
 290 #define IPR_PCII_IOARCB_XFER_FAILED                     (0x80000000 >> 3)
 291 #define IPR_PCII_IOA_UNIT_CHECKED                       (0x80000000 >> 4)
 292 #define IPR_PCII_NO_HOST_RRQ                            (0x80000000 >> 5)
 293 #define IPR_PCII_CRITICAL_OPERATION                     (0x80000000 >> 6)
 294 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE           (0x80000000 >> 7)
 295 #define IPR_PCII_IOARRIN_LOST                           (0x80000000 >> 27)
 296 #define IPR_PCII_MMIO_ERROR                             (0x80000000 >> 28)
 297 #define IPR_PCII_PROC_ERR_STATE                 (0x80000000 >> 29)
 298 #define IPR_PCII_HRRQ_UPDATED                           (0x80000000 >> 30)
 299 #define IPR_PCII_CORE_ISSUED_RST_REQ            (0x80000000 >> 31)
 300
 301 #define IPR_PCII_ERROR_INTERRUPTS \
 302 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
 303 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
 304
 305 #define IPR_PCII_OPER_INTERRUPTS \
 306 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
 307
 308 #define IPR_UPROCI_RESET_ALERT                  (0x80000000 >> 7)
 309 #define IPR_UPROCI_IO_DEBUG_ALERT                       (0x80000000 >> 9)
 310 #define IPR_UPROCI_SIS64_START_BIST                     (0x80000000 >> 23)
 311
 312 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC            200000  /* 200 ms */
 313 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC           200000  /* 200 ms */
 314
 315 /*
 316  * Dump literals
 317  */
 318 #define IPR_FMT2_MAX_IOA_DUMP_SIZE                      (4 * 1024 * 1024)
 319 #define IPR_FMT3_MAX_IOA_DUMP_SIZE                      (80 * 1024 * 1024)
 320 #define IPR_FMT2_NUM_SDT_ENTRIES                        511
 321 #define IPR_FMT3_NUM_SDT_ENTRIES                        0xFFF
 322 #define IPR_FMT2_MAX_NUM_DUMP_PAGES     ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 323 #define IPR_FMT3_MAX_NUM_DUMP_PAGES     ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 324
 325 /*
 326  * Misc literals
 327  */
 328 #define IPR_NUM_IOADL_ENTRIES                   IPR_MAX_SGLIST
 329 #define IPR_MAX_MSIX_VECTORS            0x10
 330 #define IPR_MAX_HRRQ_NUM                0x10
 331 #define IPR_INIT_HRRQ                   0x0
 332
 333 /*
 334  * Adapter interface types
 335  */
 336
 337 struct ipr_res_addr {
 338         u8 reserved;
 339         u8 bus;
 340         u8 target;
 341         u8 lun;
 342 #define IPR_GET_PHYS_LOC(res_addr) \
 343         (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
 344 }__attribute__((packed, aligned (4)));
 345
 346 struct ipr_std_inq_vpids {
 347         u8 vendor_id[IPR_VENDOR_ID_LEN];
 348         u8 product_id[IPR_PROD_ID_LEN];
 349 }__attribute__((packed));
 350
 351 struct ipr_vpd {
 352         struct ipr_std_inq_vpids vpids;
 353         u8 sn[IPR_SERIAL_NUM_LEN];
 354 }__attribute__((packed));
 355
 356 struct ipr_ext_vpd {
 357         struct ipr_vpd vpd;
 358         __be32 wwid[2];
 359 }__attribute__((packed));
 360
 361 struct ipr_ext_vpd64 {
 362         struct ipr_vpd vpd;
 363         __be32 wwid[4];
 364 }__attribute__((packed));
 365
 366 struct ipr_std_inq_data {
 367         u8 peri_qual_dev_type;
 368 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
 369 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
 370
 371         u8 removeable_medium_rsvd;
 372 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
 373
 374 #define IPR_IS_DASD_DEVICE(std_inq) \
 375 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
 376 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
 377
 378 #define IPR_IS_SES_DEVICE(std_inq) \
 379 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
 380
 381         u8 version;
 382         u8 aen_naca_fmt;
 383         u8 additional_len;
 384         u8 sccs_rsvd;
 385         u8 bq_enc_multi;
 386         u8 sync_cmdq_flags;
 387
 388         struct ipr_std_inq_vpids vpids;
 389
 390         u8 ros_rsvd_ram_rsvd[4];
 391
 392         u8 serial_num[IPR_SERIAL_NUM_LEN];
 393 }__attribute__ ((packed));
 394
 395 #define IPR_RES_TYPE_AF_DASD            0x00
 396 #define IPR_RES_TYPE_GENERIC_SCSI       0x01
 397 #define IPR_RES_TYPE_VOLUME_SET         0x02
 398 #define IPR_RES_TYPE_REMOTE_AF_DASD     0x03
 399 #define IPR_RES_TYPE_GENERIC_ATA        0x04
 400 #define IPR_RES_TYPE_ARRAY              0x05
 401 #define IPR_RES_TYPE_IOAFP              0xff
 402
 403 struct ipr_config_table_entry {
 404         u8 proto;
 405 #define IPR_PROTO_SATA                  0x02
 406 #define IPR_PROTO_SATA_ATAPI            0x03
 407 #define IPR_PROTO_SAS_STP               0x06
 408 #define IPR_PROTO_SAS_STP_ATAPI         0x07
 409         u8 array_id;
 410         u8 flags;
 411 #define IPR_IS_IOA_RESOURCE             0x80
 412         u8 rsvd_subtype;
 413
 414 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
 415 #define IPR_QUEUE_FROZEN_MODEL          0
 416 #define IPR_QUEUE_NACA_MODEL            1
 417
 418         struct ipr_res_addr res_addr;
 419         __be32 res_handle;
 420         __be32 lun_wwn[2];
 421         struct ipr_std_inq_data std_inq_data;
 422 }__attribute__ ((packed, aligned (4)));
 423
 424 struct ipr_config_table_entry64 {
 425         u8 res_type;
 426         u8 proto;
 427         u8 vset_num;
 428         u8 array_id;
 429         __be16 flags;
 430         __be16 res_flags;
 431 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
 432         __be32 res_handle;
 433         u8 dev_id_type;
 434         u8 reserved[3];
 435         __be64 dev_id;
 436         __be64 lun;
 437         __be64 lun_wwn[2];
 438 #define IPR_MAX_RES_PATH_LENGTH         48
 439         __be64 res_path;
 440         struct ipr_std_inq_data std_inq_data;
 441         u8 reserved2[4];
 442         __be64 reserved3[2];
 443         u8 reserved4[8];
 444 }__attribute__ ((packed, aligned (8)));
 445
 446 struct ipr_config_table_hdr {
 447         u8 num_entries;
 448         u8 flags;
 449 #define IPR_UCODE_DOWNLOAD_REQ  0x10
 450         __be16 reserved;
 451 }__attribute__((packed, aligned (4)));
 452
 453 struct ipr_config_table_hdr64 {
 454         __be16 num_entries;
 455         __be16 reserved;
 456         u8 flags;
 457         u8 reserved2[11];
 458 }__attribute__((packed, aligned (4)));
 459
 460 struct ipr_config_table {
 461         struct ipr_config_table_hdr hdr;
 462         struct ipr_config_table_entry dev[0];
 463 }__attribute__((packed, aligned (4)));
 464
 465 struct ipr_config_table64 {
 466         struct ipr_config_table_hdr64 hdr64;
 467         struct ipr_config_table_entry64 dev[0];
 468 }__attribute__((packed, aligned (8)));
 469
 470 struct ipr_config_table_entry_wrapper {
 471         union {
 472                 struct ipr_config_table_entry *cfgte;
 473                 struct ipr_config_table_entry64 *cfgte64;
 474         } u;
 475 };
 476
 477 struct ipr_hostrcb_cfg_ch_not {
 478         union {
 479                 struct ipr_config_table_entry cfgte;
 480                 struct ipr_config_table_entry64 cfgte64;
 481         } u;
 482         u8 reserved[936];
 483 }__attribute__((packed, aligned (4)));
 484
 485 struct ipr_supported_device {
 486         __be16 data_length;
 487         u8 reserved;
 488         u8 num_records;
 489         struct ipr_std_inq_vpids vpids;
 490         u8 reserved2[16];
 491 }__attribute__((packed, aligned (4)));
 492
 493 struct ipr_hrr_queue {
 494         struct ipr_ioa_cfg *ioa_cfg;
 495         __be32 *host_rrq;
 496         dma_addr_t host_rrq_dma;
 497 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK   0xfffffffc
 498 #define IPR_HRRQ_RESP_BIT_SET           0x00000002
 499 #define IPR_HRRQ_TOGGLE_BIT             0x00000001
 500 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT  2
 501 #define IPR_ID_HRRQ_SELE_ENABLE         0x02
 502         volatile __be32 *hrrq_start;
 503         volatile __be32 *hrrq_end;
 504         volatile __be32 *hrrq_curr;
 505
 506         struct list_head hrrq_free_q;
 507         struct list_head hrrq_pending_q;
 508         spinlock_t _lock;
 509         spinlock_t *lock;
 510
 511         volatile u32 toggle_bit;
 512         u32 size;
 513         u32 min_cmd_id;
 514         u32 max_cmd_id;
 515         u8 allow_interrupts:1;
 516         u8 ioa_is_dead:1;
 517         u8 allow_cmds:1;
 518         u8 removing_ioa:1;
 519
 520         struct irq_poll iopoll;
 521 };
 522
 523 /* Command packet structure */
 524 struct ipr_cmd_pkt {
 525         u8 reserved;            /* Reserved by IOA */
 526         u8 hrrq_id;
 527         u8 request_type;
 528 #define IPR_RQTYPE_SCSICDB              0x00
 529 #define IPR_RQTYPE_IOACMD               0x01
 530 #define IPR_RQTYPE_HCAM                 0x02
 531 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
 532 #define IPR_RQTYPE_PIPE                 0x05
 533
 534         u8 reserved2;
 535
 536         u8 flags_hi;
 537 #define IPR_FLAGS_HI_WRITE_NOT_READ             0x80
 538 #define IPR_FLAGS_HI_NO_ULEN_CHK                0x20
 539 #define IPR_FLAGS_HI_SYNC_OVERRIDE              0x10
 540 #define IPR_FLAGS_HI_SYNC_COMPLETE              0x08
 541 #define IPR_FLAGS_HI_NO_LINK_DESC               0x04
 542
 543         u8 flags_lo;
 544 #define IPR_FLAGS_LO_ALIGNED_BFR                0x20
 545 #define IPR_FLAGS_LO_DELAY_AFTER_RST            0x10
 546 #define IPR_FLAGS_LO_UNTAGGED_TASK              0x00
 547 #define IPR_FLAGS_LO_SIMPLE_TASK                0x02
 548 #define IPR_FLAGS_LO_ORDERED_TASK               0x04
 549 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK             0x06
 550 #define IPR_FLAGS_LO_ACA_TASK                   0x08
 551
 552         u8 cdb[16];
 553         __be16 timeout;
 554 }__attribute__ ((packed, aligned(4)));
 555
 556 struct ipr_ioarcb_ata_regs {    /* 22 bytes */
 557         u8 flags;
 558 #define IPR_ATA_FLAG_PACKET_CMD                 0x80
 559 #define IPR_ATA_FLAG_XFER_TYPE_DMA                      0x40
 560 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION  0x20
 561         u8 reserved[3];
 562
 563         __be16 data;
 564         u8 feature;
 565         u8 nsect;
 566         u8 lbal;
 567         u8 lbam;
 568         u8 lbah;
 569         u8 device;
 570         u8 command;
 571         u8 reserved2[3];
 572         u8 hob_feature;
 573         u8 hob_nsect;
 574         u8 hob_lbal;
 575         u8 hob_lbam;
 576         u8 hob_lbah;
 577         u8 ctl;
 578 }__attribute__ ((packed, aligned(2)));
 579
 580 struct ipr_ioadl_desc {
 581         __be32 flags_and_data_len;
 582 #define IPR_IOADL_FLAGS_MASK            0xff000000
 583 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
 584 #define IPR_IOADL_DATA_LEN_MASK         0x00ffffff
 585 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
 586 #define IPR_IOADL_FLAGS_READ            0x48000000
 587 #define IPR_IOADL_FLAGS_READ_LAST       0x49000000
 588 #define IPR_IOADL_FLAGS_WRITE           0x68000000
 589 #define IPR_IOADL_FLAGS_WRITE_LAST      0x69000000
 590 #define IPR_IOADL_FLAGS_LAST            0x01000000
 591
 592         __be32 address;
 593 }__attribute__((packed, aligned (8)));
 594
 595 struct ipr_ioadl64_desc {
 596         __be32 flags;
 597         __be32 data_len;
 598         __be64 address;
 599 }__attribute__((packed, aligned (16)));
 600
 601 struct ipr_ata64_ioadl {
 602         struct ipr_ioarcb_ata_regs regs;
 603         u16 reserved[5];
 604         struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
 605 }__attribute__((packed, aligned (16)));
 606
 607 struct ipr_ioarcb_add_data {
 608         union {
 609                 struct ipr_ioarcb_ata_regs regs;
 610                 struct ipr_ioadl_desc ioadl[5];
 611                 __be32 add_cmd_parms[10];
 612         } u;
 613 }__attribute__ ((packed, aligned (4)));
 614
 615 struct ipr_ioarcb_sis64_add_addr_ecb {
 616         __be64 ioasa_host_pci_addr;
 617         __be64 data_ioadl_addr;
 618         __be64 reserved;
 619         __be32 ext_control_buf[4];
 620 }__attribute__((packed, aligned (8)));
 621
 622 /* IOA Request Control Block    128 bytes  */
 623 struct ipr_ioarcb {
 624         union {
 625                 __be32 ioarcb_host_pci_addr;
 626                 __be64 ioarcb_host_pci_addr64;
 627         } a;
 628         __be32 res_handle;
 629         __be32 host_response_handle;
 630         __be32 reserved1;
 631         __be32 reserved2;
 632         __be32 reserved3;
 633
 634         __be32 data_transfer_length;
 635         __be32 read_data_transfer_length;
 636         __be32 write_ioadl_addr;
 637         __be32 ioadl_len;
 638         __be32 read_ioadl_addr;
 639         __be32 read_ioadl_len;
 640
 641         __be32 ioasa_host_pci_addr;
 642         __be16 ioasa_len;
 643         __be16 reserved4;
 644
 645         struct ipr_cmd_pkt cmd_pkt;
 646
 647         __be16 add_cmd_parms_offset;
 648         __be16 add_cmd_parms_len;
 649
 650         union {
 651                 struct ipr_ioarcb_add_data add_data;
 652                 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
 653         } u;
 654
 655 }__attribute__((packed, aligned (4)));
 656
 657 struct ipr_ioasa_vset {
 658         __be32 failing_lba_hi;
 659         __be32 failing_lba_lo;
 660         __be32 reserved;
 661 }__attribute__((packed, aligned (4)));
 662
 663 struct ipr_ioasa_af_dasd {
 664         __be32 failing_lba;
 665         __be32 reserved[2];
 666 }__attribute__((packed, aligned (4)));
 667
 668 struct ipr_ioasa_gpdd {
 669         u8 end_state;
 670         u8 bus_phase;
 671         __be16 reserved;
 672         __be32 ioa_data[2];
 673 }__attribute__((packed, aligned (4)));
 674
 675 struct ipr_ioasa_gata {
 676         u8 error;
 677         u8 nsect;               /* Interrupt reason */
 678         u8 lbal;
 679         u8 lbam;
 680         u8 lbah;
 681         u8 device;
 682         u8 status;
 683         u8 alt_status;  /* ATA CTL */
 684         u8 hob_nsect;
 685         u8 hob_lbal;
 686         u8 hob_lbam;
 687         u8 hob_lbah;
 688 }__attribute__((packed, aligned (4)));
 689
 690 struct ipr_auto_sense {
 691         __be16 auto_sense_len;
 692         __be16 ioa_data_len;
 693         __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
 694 };
 695
 696 struct ipr_ioasa_hdr {
 697         __be32 ioasc;
 698 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
 699 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
 700 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
 701 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
 702
 703         __be16 ret_stat_len;    /* Length of the returned IOASA */
 704
 705         __be16 avail_stat_len;  /* Total Length of status available. */
 706
 707         __be32 residual_data_len;       /* number of bytes in the host data */
 708         /* buffers that were not used by the IOARCB command. */
 709
 710         __be32 ilid;
 711 #define IPR_NO_ILID                     0
 712 #define IPR_DRIVER_ILID         0xffffffff
 713
 714         __be32 fd_ioasc;
 715
 716         __be32 fd_phys_locator;
 717
 718         __be32 fd_res_handle;
 719
 720         __be32 ioasc_specific;  /* status code specific field */
 721 #define IPR_ADDITIONAL_STATUS_FMT               0x80000000
 722 #define IPR_AUTOSENSE_VALID                     0x40000000
 723 #define IPR_ATA_DEVICE_WAS_RESET                0x20000000
 724 #define IPR_IOASC_SPECIFIC_MASK         0x00ffffff
 725 #define IPR_FIELD_POINTER_VALID         (0x80000000 >> 8)
 726 #define IPR_FIELD_POINTER_MASK          0x0000ffff
 727
 728 }__attribute__((packed, aligned (4)));
 729
 730 struct ipr_ioasa {
 731         struct ipr_ioasa_hdr hdr;
 732
 733         union {
 734                 struct ipr_ioasa_vset vset;
 735                 struct ipr_ioasa_af_dasd dasd;
 736                 struct ipr_ioasa_gpdd gpdd;
 737                 struct ipr_ioasa_gata gata;
 738         } u;
 739
 740         struct ipr_auto_sense auto_sense;
 741 }__attribute__((packed, aligned (4)));
 742
 743 struct ipr_ioasa64 {
 744         struct ipr_ioasa_hdr hdr;
 745         u8 fd_res_path[8];
 746
 747         union {
 748                 struct ipr_ioasa_vset vset;
 749                 struct ipr_ioasa_af_dasd dasd;
 750                 struct ipr_ioasa_gpdd gpdd;
 751                 struct ipr_ioasa_gata gata;
 752         } u;
 753
 754         struct ipr_auto_sense auto_sense;
 755 }__attribute__((packed, aligned (4)));
 756
 757 struct ipr_mode_parm_hdr {
 758         u8 length;
 759         u8 medium_type;
 760         u8 device_spec_parms;
 761         u8 block_desc_len;
 762 }__attribute__((packed));
 763
 764 struct ipr_mode_pages {
 765         struct ipr_mode_parm_hdr hdr;
 766         u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
 767 }__attribute__((packed));
 768
 769 struct ipr_mode_page_hdr {
 770         u8 ps_page_code;
 771 #define IPR_MODE_PAGE_PS        0x80
 772 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
 773         u8 page_length;
 774 }__attribute__ ((packed));
 775
 776 struct ipr_dev_bus_entry {
 777         struct ipr_res_addr res_addr;
 778         u8 flags;
 779 #define IPR_SCSI_ATTR_ENABLE_QAS                        0x80
 780 #define IPR_SCSI_ATTR_DISABLE_QAS                       0x40
 781 #define IPR_SCSI_ATTR_QAS_MASK                          0xC0
 782 #define IPR_SCSI_ATTR_ENABLE_TM                         0x20
 783 #define IPR_SCSI_ATTR_NO_TERM_PWR                       0x10
 784 #define IPR_SCSI_ATTR_TM_SUPPORTED                      0x08
 785 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED     0x04
 786
 787         u8 scsi_id;
 788         u8 bus_width;
 789         u8 extended_reset_delay;
 790 #define IPR_EXTENDED_RESET_DELAY        7
 791
 792         __be32 max_xfer_rate;
 793
 794         u8 spinup_delay;
 795         u8 reserved3;
 796         __be16 reserved4;
 797 }__attribute__((packed, aligned (4)));
 798
 799 struct ipr_mode_page28 {
 800         struct ipr_mode_page_hdr hdr;
 801         u8 num_entries;
 802         u8 entry_length;
 803         struct ipr_dev_bus_entry bus[0];
 804 }__attribute__((packed));
 805
 806 struct ipr_mode_page24 {
 807         struct ipr_mode_page_hdr hdr;
 808         u8 flags;
 809 #define IPR_ENABLE_DUAL_IOA_AF 0x80
 810 }__attribute__((packed));
 811
 812 struct ipr_ioa_vpd {
 813         struct ipr_std_inq_data std_inq_data;
 814         u8 ascii_part_num[12];
 815         u8 reserved[40];
 816         u8 ascii_plant_code[4];
 817 }__attribute__((packed));
 818
 819 struct ipr_inquiry_page3 {
 820         u8 peri_qual_dev_type;
 821         u8 page_code;
 822         u8 reserved1;
 823         u8 page_length;
 824         u8 ascii_len;
 825         u8 reserved2[3];
 826         u8 load_id[4];
 827         u8 major_release;
 828         u8 card_type;
 829         u8 minor_release[2];
 830         u8 ptf_number[4];
 831         u8 patch_number[4];
 832 }__attribute__((packed));
 833
 834 struct ipr_inquiry_cap {
 835         u8 peri_qual_dev_type;
 836         u8 page_code;
 837         u8 reserved1;
 838         u8 page_length;
 839         u8 ascii_len;
 840         u8 reserved2;
 841         u8 sis_version[2];
 842         u8 cap;
 843 #define IPR_CAP_DUAL_IOA_RAID           0x80
 844         u8 reserved3[15];
 845 }__attribute__((packed));
 846
 847 #define IPR_INQUIRY_PAGE0_ENTRIES 20
 848 struct ipr_inquiry_page0 {
 849         u8 peri_qual_dev_type;
 850         u8 page_code;
 851         u8 reserved1;
 852         u8 len;
 853         u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
 854 }__attribute__((packed));
 855
 856 struct ipr_inquiry_pageC4 {
 857         u8 peri_qual_dev_type;
 858         u8 page_code;
 859         u8 reserved1;
 860         u8 len;
 861         u8 cache_cap[4];
 862 #define IPR_CAP_SYNC_CACHE              0x08
 863         u8 reserved2[20];
 864 } __packed;
 865
 866 struct ipr_hostrcb_device_data_entry {
 867         struct ipr_vpd vpd;
 868         struct ipr_res_addr dev_res_addr;
 869         struct ipr_vpd new_vpd;
 870         struct ipr_vpd ioa_last_with_dev_vpd;
 871         struct ipr_vpd cfc_last_with_dev_vpd;
 872         __be32 ioa_data[5];
 873 }__attribute__((packed, aligned (4)));
 874
 875 struct ipr_hostrcb_device_data_entry_enhanced {
 876         struct ipr_ext_vpd vpd;
 877         u8 ccin[4];
 878         struct ipr_res_addr dev_res_addr;
 879         struct ipr_ext_vpd new_vpd;
 880         u8 new_ccin[4];
 881         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 882         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 883 }__attribute__((packed, aligned (4)));
 884
 885 struct ipr_hostrcb64_device_data_entry_enhanced {
 886         struct ipr_ext_vpd vpd;
 887         u8 ccin[4];
 888         u8 res_path[8];
 889         struct ipr_ext_vpd new_vpd;
 890         u8 new_ccin[4];
 891         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 892         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 893 }__attribute__((packed, aligned (4)));
 894
 895 struct ipr_hostrcb_array_data_entry {
 896         struct ipr_vpd vpd;
 897         struct ipr_res_addr expected_dev_res_addr;
 898         struct ipr_res_addr dev_res_addr;
 899 }__attribute__((packed, aligned (4)));
 900
 901 struct ipr_hostrcb64_array_data_entry {
 902         struct ipr_ext_vpd vpd;
 903         u8 ccin[4];
 904         u8 expected_res_path[8];
 905         u8 res_path[8];
 906 }__attribute__((packed, aligned (4)));
 907
 908 struct ipr_hostrcb_array_data_entry_enhanced {
 909         struct ipr_ext_vpd vpd;
 910         u8 ccin[4];
 911         struct ipr_res_addr expected_dev_res_addr;
 912         struct ipr_res_addr dev_res_addr;
 913 }__attribute__((packed, aligned (4)));
 914
 915 struct ipr_hostrcb_type_ff_error {
 916         __be32 ioa_data[758];
 917 }__attribute__((packed, aligned (4)));
 918
 919 struct ipr_hostrcb_type_01_error {
 920         __be32 seek_counter;
 921         __be32 read_counter;
 922         u8 sense_data[32];
 923         __be32 ioa_data[236];
 924 }__attribute__((packed, aligned (4)));
 925
 926 struct ipr_hostrcb_type_21_error {
 927         __be32 wwn[4];
 928         u8 res_path[8];
 929         u8 primary_problem_desc[32];
 930         u8 second_problem_desc[32];
 931         __be32 sense_data[8];
 932         __be32 cdb[4];
 933         __be32 residual_trans_length;
 934         __be32 length_of_error;
 935         __be32 ioa_data[236];
 936 }__attribute__((packed, aligned (4)));
 937
 938 struct ipr_hostrcb_type_02_error {
 939         struct ipr_vpd ioa_vpd;
 940         struct ipr_vpd cfc_vpd;
 941         struct ipr_vpd ioa_last_attached_to_cfc_vpd;
 942         struct ipr_vpd cfc_last_attached_to_ioa_vpd;
 943         __be32 ioa_data[3];
 944 }__attribute__((packed, aligned (4)));
 945
 946 struct ipr_hostrcb_type_12_error {
 947         struct ipr_ext_vpd ioa_vpd;
 948         struct ipr_ext_vpd cfc_vpd;
 949         struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
 950         struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
 951         __be32 ioa_data[3];
 952 }__attribute__((packed, aligned (4)));
 953
 954 struct ipr_hostrcb_type_03_error {
 955         struct ipr_vpd ioa_vpd;
 956         struct ipr_vpd cfc_vpd;
 957         __be32 errors_detected;
 958         __be32 errors_logged;
 959         u8 ioa_data[12];
 960         struct ipr_hostrcb_device_data_entry dev[3];
 961 }__attribute__((packed, aligned (4)));
 962
 963 struct ipr_hostrcb_type_13_error {
 964         struct ipr_ext_vpd ioa_vpd;
 965         struct ipr_ext_vpd cfc_vpd;
 966         __be32 errors_detected;
 967         __be32 errors_logged;
 968         struct ipr_hostrcb_device_data_entry_enhanced dev[3];
 969 }__attribute__((packed, aligned (4)));
 970
 971 struct ipr_hostrcb_type_23_error {
 972         struct ipr_ext_vpd ioa_vpd;
 973         struct ipr_ext_vpd cfc_vpd;
 974         __be32 errors_detected;
 975         __be32 errors_logged;
 976         struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
 977 }__attribute__((packed, aligned (4)));
 978
 979 struct ipr_hostrcb_type_04_error {
 980         struct ipr_vpd ioa_vpd;
 981         struct ipr_vpd cfc_vpd;
 982         u8 ioa_data[12];
 983         struct ipr_hostrcb_array_data_entry array_member[10];
 984         __be32 exposed_mode_adn;
 985         __be32 array_id;
 986         struct ipr_vpd incomp_dev_vpd;
 987         __be32 ioa_data2;
 988         struct ipr_hostrcb_array_data_entry array_member2[8];
 989         struct ipr_res_addr last_func_vset_res_addr;
 990         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 991         u8 protection_level[8];
 992 }__attribute__((packed, aligned (4)));
 993
 994 struct ipr_hostrcb_type_14_error {
 995         struct ipr_ext_vpd ioa_vpd;
 996         struct ipr_ext_vpd cfc_vpd;
 997         __be32 exposed_mode_adn;
 998         __be32 array_id;
 999         struct ipr_res_addr last_func_vset_res_addr;
1000         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
1001         u8 protection_level[8];
1002         __be32 num_entries;
1003         struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
1004 }__attribute__((packed, aligned (4)));
1005
1006 struct ipr_hostrcb_type_24_error {
1007         struct ipr_ext_vpd ioa_vpd;
1008         struct ipr_ext_vpd cfc_vpd;
1009         u8 reserved[2];
1010         u8 exposed_mode_adn;
1011 #define IPR_INVALID_ARRAY_DEV_NUM               0xff
1012         u8 array_id;
1013         u8 last_res_path[8];
1014         u8 protection_level[8];
1015         struct ipr_ext_vpd64 array_vpd;
1016         u8 description[16];
1017         u8 reserved2[3];
1018         u8 num_entries;
1019         struct ipr_hostrcb64_array_data_entry array_member[32];
1020 }__attribute__((packed, aligned (4)));
1021
1022 struct ipr_hostrcb_type_07_error {
1023         u8 failure_reason[64];
1024         struct ipr_vpd vpd;
1025         __be32 data[222];
1026 }__attribute__((packed, aligned (4)));
1027
1028 struct ipr_hostrcb_type_17_error {
1029         u8 failure_reason[64];
1030         struct ipr_ext_vpd vpd;
1031         __be32 data[476];
1032 }__attribute__((packed, aligned (4)));
1033
1034 struct ipr_hostrcb_config_element {
1035         u8 type_status;
1036 #define IPR_PATH_CFG_TYPE_MASK  0xF0
1037 #define IPR_PATH_CFG_NOT_EXIST  0x00
1038 #define IPR_PATH_CFG_IOA_PORT           0x10
1039 #define IPR_PATH_CFG_EXP_PORT           0x20
1040 #define IPR_PATH_CFG_DEVICE_PORT        0x30
1041 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1042
1043 #define IPR_PATH_CFG_STATUS_MASK        0x0F
1044 #define IPR_PATH_CFG_NO_PROB            0x00
1045 #define IPR_PATH_CFG_DEGRADED           0x01
1046 #define IPR_PATH_CFG_FAILED             0x02
1047 #define IPR_PATH_CFG_SUSPECT            0x03
1048 #define IPR_PATH_NOT_DETECTED           0x04
1049 #define IPR_PATH_INCORRECT_CONN 0x05
1050
1051         u8 cascaded_expander;
1052         u8 phy;
1053         u8 link_rate;
1054 #define IPR_PHY_LINK_RATE_MASK  0x0F
1055
1056         __be32 wwid[2];
1057 }__attribute__((packed, aligned (4)));
1058
1059 struct ipr_hostrcb64_config_element {
1060         __be16 length;
1061         u8 descriptor_id;
1062 #define IPR_DESCRIPTOR_MASK             0xC0
1063 #define IPR_DESCRIPTOR_SIS64            0x00
1064
1065         u8 reserved;
1066         u8 type_status;
1067
1068         u8 reserved2[2];
1069         u8 link_rate;
1070
1071         u8 res_path[8];
1072         __be32 wwid[2];
1073 }__attribute__((packed, aligned (8)));
1074
1075 struct ipr_hostrcb_fabric_desc {
1076         __be16 length;
1077         u8 ioa_port;
1078         u8 cascaded_expander;
1079         u8 phy;
1080         u8 path_state;
1081 #define IPR_PATH_ACTIVE_MASK            0xC0
1082 #define IPR_PATH_NO_INFO                0x00
1083 #define IPR_PATH_ACTIVE                 0x40
1084 #define IPR_PATH_NOT_ACTIVE             0x80
1085
1086 #define IPR_PATH_STATE_MASK             0x0F
1087 #define IPR_PATH_STATE_NO_INFO  0x00
1088 #define IPR_PATH_HEALTHY                0x01
1089 #define IPR_PATH_DEGRADED               0x02
1090 #define IPR_PATH_FAILED                 0x03
1091
1092         __be16 num_entries;
1093         struct ipr_hostrcb_config_element elem[1];
1094 }__attribute__((packed, aligned (4)));
1095
1096 struct ipr_hostrcb64_fabric_desc {
1097         __be16 length;
1098         u8 descriptor_id;
1099
1100         u8 reserved[2];
1101         u8 path_state;
1102
1103         u8 reserved2[2];
1104         u8 res_path[8];
1105         u8 reserved3[6];
1106         __be16 num_entries;
1107         struct ipr_hostrcb64_config_element elem[1];
1108 }__attribute__((packed, aligned (8)));
1109
1110 #define for_each_hrrq(hrrq, ioa_cfg) \
1111                 for (hrrq = (ioa_cfg)->hrrq; \
1112                         hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1113
1114 #define for_each_fabric_cfg(fabric, cfg) \
1115                 for (cfg = (fabric)->elem; \
1116                         cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1117                         cfg++)
1118
1119 struct ipr_hostrcb_type_20_error {
1120         u8 failure_reason[64];
1121         u8 reserved[3];
1122         u8 num_entries;
1123         struct ipr_hostrcb_fabric_desc desc[1];
1124 }__attribute__((packed, aligned (4)));
1125
1126 struct ipr_hostrcb_type_30_error {
1127         u8 failure_reason[64];
1128         u8 reserved[3];
1129         u8 num_entries;
1130         struct ipr_hostrcb64_fabric_desc desc[1];
1131 }__attribute__((packed, aligned (4)));
1132
1133 struct ipr_hostrcb_error {
1134         __be32 fd_ioasc;
1135         struct ipr_res_addr fd_res_addr;
1136         __be32 fd_res_handle;
1137         __be32 prc;
1138         union {
1139                 struct ipr_hostrcb_type_ff_error type_ff_error;
1140                 struct ipr_hostrcb_type_01_error type_01_error;
1141                 struct ipr_hostrcb_type_02_error type_02_error;
1142                 struct ipr_hostrcb_type_03_error type_03_error;
1143                 struct ipr_hostrcb_type_04_error type_04_error;
1144                 struct ipr_hostrcb_type_07_error type_07_error;
1145                 struct ipr_hostrcb_type_12_error type_12_error;
1146                 struct ipr_hostrcb_type_13_error type_13_error;
1147                 struct ipr_hostrcb_type_14_error type_14_error;
1148                 struct ipr_hostrcb_type_17_error type_17_error;
1149                 struct ipr_hostrcb_type_20_error type_20_error;
1150         } u;
1151 }__attribute__((packed, aligned (4)));
1152
1153 struct ipr_hostrcb64_error {
1154         __be32 fd_ioasc;
1155         __be32 ioa_fw_level;
1156         __be32 fd_res_handle;
1157         __be32 prc;
1158         __be64 fd_dev_id;
1159         __be64 fd_lun;
1160         u8 fd_res_path[8];
1161         __be64 time_stamp;
1162         u8 reserved[16];
1163         union {
1164                 struct ipr_hostrcb_type_ff_error type_ff_error;
1165                 struct ipr_hostrcb_type_12_error type_12_error;
1166                 struct ipr_hostrcb_type_17_error type_17_error;
1167                 struct ipr_hostrcb_type_21_error type_21_error;
1168                 struct ipr_hostrcb_type_23_error type_23_error;
1169                 struct ipr_hostrcb_type_24_error type_24_error;
1170                 struct ipr_hostrcb_type_30_error type_30_error;
1171         } u;
1172 }__attribute__((packed, aligned (8)));
1173
1174 struct ipr_hostrcb_raw {
1175         __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1176 }__attribute__((packed, aligned (4)));
1177
1178 struct ipr_hcam {
1179         u8 op_code;
1180 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE                      0xE1
1181 #define IPR_HOST_RCB_OP_CODE_LOG_DATA                           0xE2
1182
1183         u8 notify_type;
1184 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED        0x00
1185 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY                       0x01
1186 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY                       0x02
1187 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY         0x10
1188 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY       0x11
1189
1190         u8 notifications_lost;
1191 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST                      0
1192 #define IPR_HOST_RCB_NOTIFICATIONS_LOST                         0x80
1193
1194         u8 flags;
1195 #define IPR_HOSTRCB_INTERNAL_OPER       0x80
1196 #define IPR_HOSTRCB_ERR_RESP_SENT       0x40
1197
1198         u8 overlay_id;
1199 #define IPR_HOST_RCB_OVERLAY_ID_1                               0x01
1200 #define IPR_HOST_RCB_OVERLAY_ID_2                               0x02
1201 #define IPR_HOST_RCB_OVERLAY_ID_3                               0x03
1202 #define IPR_HOST_RCB_OVERLAY_ID_4                               0x04
1203 #define IPR_HOST_RCB_OVERLAY_ID_6                               0x06
1204 #define IPR_HOST_RCB_OVERLAY_ID_7                               0x07
1205 #define IPR_HOST_RCB_OVERLAY_ID_12                              0x12
1206 #define IPR_HOST_RCB_OVERLAY_ID_13                              0x13
1207 #define IPR_HOST_RCB_OVERLAY_ID_14                              0x14
1208 #define IPR_HOST_RCB_OVERLAY_ID_16                              0x16
1209 #define IPR_HOST_RCB_OVERLAY_ID_17                              0x17
1210 #define IPR_HOST_RCB_OVERLAY_ID_20                              0x20
1211 #define IPR_HOST_RCB_OVERLAY_ID_21                              0x21
1212 #define IPR_HOST_RCB_OVERLAY_ID_23                              0x23
1213 #define IPR_HOST_RCB_OVERLAY_ID_24                              0x24
1214 #define IPR_HOST_RCB_OVERLAY_ID_26                              0x26
1215 #define IPR_HOST_RCB_OVERLAY_ID_30                              0x30
1216 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT                         0xFF
1217
1218         u8 reserved1[3];
1219         __be32 ilid;
1220         __be32 time_since_last_ioa_reset;
1221         __be32 reserved2;
1222         __be32 length;
1223
1224         union {
1225                 struct ipr_hostrcb_error error;
1226                 struct ipr_hostrcb64_error error64;
1227                 struct ipr_hostrcb_cfg_ch_not ccn;
1228                 struct ipr_hostrcb_raw raw;
1229         } u;
1230 }__attribute__((packed, aligned (4)));
1231
1232 struct ipr_hostrcb {
1233         struct ipr_hcam hcam;
1234         dma_addr_t hostrcb_dma;
1235         struct list_head queue;
1236         struct ipr_ioa_cfg *ioa_cfg;
1237         char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1238 };
1239
1240 /* IPR smart dump table structures */
1241 struct ipr_sdt_entry {
1242         __be32 start_token;
1243         __be32 end_token;
1244         u8 reserved[4];
1245
1246         u8 flags;
1247 #define IPR_SDT_ENDIAN          0x80
1248 #define IPR_SDT_VALID_ENTRY     0x20
1249
1250         u8 resv;
1251         __be16 priority;
1252 }__attribute__((packed, aligned (4)));
1253
1254 struct ipr_sdt_header {
1255         __be32 state;
1256         __be32 num_entries;
1257         __be32 num_entries_used;
1258         __be32 dump_size;
1259 }__attribute__((packed, aligned (4)));
1260
1261 struct ipr_sdt {
1262         struct ipr_sdt_header hdr;
1263         struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1264 }__attribute__((packed, aligned (4)));
1265
1266 struct ipr_uc_sdt {
1267         struct ipr_sdt_header hdr;
1268         struct ipr_sdt_entry entry[1];
1269 }__attribute__((packed, aligned (4)));
1270
1271 /*
1272  * Driver types
1273  */
1274 struct ipr_bus_attributes {
1275         u8 bus;
1276         u8 qas_enabled;
1277         u8 bus_width;
1278         u8 reserved;
1279         u32 max_xfer_rate;
1280 };
1281
1282 struct ipr_sata_port {
1283         struct ipr_ioa_cfg *ioa_cfg;
1284         struct ata_port *ap;
1285         struct ipr_resource_entry *res;
1286         struct ipr_ioasa_gata ioasa;
1287 };
1288
1289 struct ipr_resource_entry {
1290         u8 needs_sync_complete:1;
1291         u8 in_erp:1;
1292         u8 add_to_ml:1;
1293         u8 del_from_ml:1;
1294         u8 resetting_device:1;
1295         u8 reset_occurred:1;
1296         u8 raw_mode:1;
1297
1298         u32 bus;                /* AKA channel */
1299         u32 target;             /* AKA id */
1300         u32 lun;
1301 #define IPR_ARRAY_VIRTUAL_BUS                   0x1
1302 #define IPR_VSET_VIRTUAL_BUS                    0x2
1303 #define IPR_IOAFP_VIRTUAL_BUS                   0x3
1304
1305 #define IPR_GET_RES_PHYS_LOC(res) \
1306         (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1307
1308         u8 ata_class;
1309         u8 type;
1310
1311         u16 flags;
1312         u16 res_flags;
1313
1314         u8 qmodel;
1315         struct ipr_std_inq_data std_inq_data;
1316
1317         __be32 res_handle;
1318         __be64 dev_id;
1319         u64 lun_wwn;
1320         struct scsi_lun dev_lun;
1321         u8 res_path[8];
1322
1323         struct ipr_ioa_cfg *ioa_cfg;
1324         struct scsi_device *sdev;
1325         struct ipr_sata_port *sata_port;
1326         struct list_head queue;
1327 }; /* struct ipr_resource_entry */
1328
1329 struct ipr_resource_hdr {
1330         u16 num_entries;
1331         u16 reserved;
1332 };
1333
1334 struct ipr_misc_cbs {
1335         struct ipr_ioa_vpd ioa_vpd;
1336         struct ipr_inquiry_page0 page0_data;
1337         struct ipr_inquiry_page3 page3_data;
1338         struct ipr_inquiry_cap cap;
1339         struct ipr_inquiry_pageC4 pageC4_data;
1340         struct ipr_mode_pages mode_pages;
1341         struct ipr_supported_device supp_dev;
1342 };
1343
1344 struct ipr_interrupt_offsets {
1345         unsigned long set_interrupt_mask_reg;
1346         unsigned long clr_interrupt_mask_reg;
1347         unsigned long clr_interrupt_mask_reg32;
1348         unsigned long sense_interrupt_mask_reg;
1349         unsigned long sense_interrupt_mask_reg32;
1350         unsigned long clr_interrupt_reg;
1351         unsigned long clr_interrupt_reg32;
1352
1353         unsigned long sense_interrupt_reg;
1354         unsigned long sense_interrupt_reg32;
1355         unsigned long ioarrin_reg;
1356         unsigned long sense_uproc_interrupt_reg;
1357         unsigned long sense_uproc_interrupt_reg32;
1358         unsigned long set_uproc_interrupt_reg;
1359         unsigned long set_uproc_interrupt_reg32;
1360         unsigned long clr_uproc_interrupt_reg;
1361         unsigned long clr_uproc_interrupt_reg32;
1362
1363         unsigned long init_feedback_reg;
1364
1365         unsigned long dump_addr_reg;
1366         unsigned long dump_data_reg;
1367
1368 #define IPR_ENDIAN_SWAP_KEY             0x00080800
1369         unsigned long endian_swap_reg;
1370 };
1371
1372 struct ipr_interrupts {
1373         void __iomem *set_interrupt_mask_reg;
1374         void __iomem *clr_interrupt_mask_reg;
1375         void __iomem *clr_interrupt_mask_reg32;
1376         void __iomem *sense_interrupt_mask_reg;
1377         void __iomem *sense_interrupt_mask_reg32;
1378         void __iomem *clr_interrupt_reg;
1379         void __iomem *clr_interrupt_reg32;
1380
1381         void __iomem *sense_interrupt_reg;
1382         void __iomem *sense_interrupt_reg32;
1383         void __iomem *ioarrin_reg;
1384         void __iomem *sense_uproc_interrupt_reg;
1385         void __iomem *sense_uproc_interrupt_reg32;
1386         void __iomem *set_uproc_interrupt_reg;
1387         void __iomem *set_uproc_interrupt_reg32;
1388         void __iomem *clr_uproc_interrupt_reg;
1389         void __iomem *clr_uproc_interrupt_reg32;
1390
1391         void __iomem *init_feedback_reg;
1392
1393         void __iomem *dump_addr_reg;
1394         void __iomem *dump_data_reg;
1395
1396         void __iomem *endian_swap_reg;
1397 };
1398
1399 struct ipr_chip_cfg_t {
1400         u32 mailbox;
1401         u16 max_cmds;
1402         u8 cache_line_size;
1403         u8 clear_isr;
1404         u32 iopoll_weight;
1405         struct ipr_interrupt_offsets regs;
1406 };
1407
1408 struct ipr_chip_t {
1409         u16 vendor;
1410         u16 device;
1411         u16 intr_type;
1412 #define IPR_USE_LSI                     0x00
1413 #define IPR_USE_MSI                     0x01
1414 #define IPR_USE_MSIX                    0x02
1415         u16 sis_type;
1416 #define IPR_SIS32                       0x00
1417 #define IPR_SIS64                       0x01
1418         u16 bist_method;
1419 #define IPR_PCI_CFG                     0x00
1420 #define IPR_MMIO                        0x01
1421         const struct ipr_chip_cfg_t *cfg;
1422 };
1423
1424 enum ipr_shutdown_type {
1425         IPR_SHUTDOWN_NORMAL = 0x00,
1426         IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1427         IPR_SHUTDOWN_ABBREV = 0x80,
1428         IPR_SHUTDOWN_NONE = 0x100,
1429         IPR_SHUTDOWN_QUIESCE = 0x101,
1430 };
1431
1432 struct ipr_trace_entry {
1433         u32 time;
1434
1435         u8 op_code;
1436         u8 ata_op_code;
1437         u8 type;
1438 #define IPR_TRACE_START                 0x00
1439 #define IPR_TRACE_FINISH                0xff
1440         u8 cmd_index;
1441
1442         __be32 res_handle;
1443         union {
1444                 u32 ioasc;
1445                 u32 add_data;
1446                 u32 res_addr;
1447         } u;
1448 };
1449
1450 struct ipr_sglist {
1451         u32 order;
1452         u32 num_sg;
1453         u32 num_dma_sg;
1454         u32 buffer_len;
1455         struct scatterlist scatterlist[1];
1456 };
1457
1458 enum ipr_sdt_state {
1459         INACTIVE,
1460         WAIT_FOR_DUMP,
1461         GET_DUMP,
1462         READ_DUMP,
1463         ABORT_DUMP,
1464         DUMP_OBTAINED
1465 };
1466
1467 /* Per-controller data */
1468 struct ipr_ioa_cfg {
1469         char eye_catcher[8];
1470 #define IPR_EYECATCHER                  "iprcfg"
1471
1472         struct list_head queue;
1473
1474         u8 in_reset_reload:1;
1475         u8 in_ioa_bringdown:1;
1476         u8 ioa_unit_checked:1;
1477         u8 dump_taken:1;
1478         u8 scan_done:1;
1479         u8 needs_hard_reset:1;
1480         u8 dual_raid:1;
1481         u8 needs_warm_reset:1;
1482         u8 msi_received:1;
1483         u8 sis64:1;
1484         u8 dump_timeout:1;
1485         u8 cfg_locked:1;
1486         u8 clear_isr:1;
1487         u8 probe_done:1;
1488
1489         u8 revid;
1490
1491         /*
1492          * Bitmaps for SIS64 generated target values
1493          */
1494         unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1495         unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1496         unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1497
1498         u16 type; /* CCIN of the card */
1499
1500         u8 log_level;
1501 #define IPR_MAX_LOG_LEVEL                       4
1502 #define IPR_DEFAULT_LOG_LEVEL           2
1503
1504 #define IPR_NUM_TRACE_INDEX_BITS        8
1505 #define IPR_NUM_TRACE_ENTRIES           (1 << IPR_NUM_TRACE_INDEX_BITS)
1506 #define IPR_TRACE_INDEX_MASK            (IPR_NUM_TRACE_ENTRIES - 1)
1507 #define IPR_TRACE_SIZE  (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1508         char trace_start[8];
1509 #define IPR_TRACE_START_LABEL                   "trace"
1510         struct ipr_trace_entry *trace;
1511         atomic_t trace_index;
1512
1513         char cfg_table_start[8];
1514 #define IPR_CFG_TBL_START               "cfg"
1515         union {
1516                 struct ipr_config_table *cfg_table;
1517                 struct ipr_config_table64 *cfg_table64;
1518         } u;
1519         dma_addr_t cfg_table_dma;
1520         u32 cfg_table_size;
1521         u32 max_devs_supported;
1522
1523         char resource_table_label[8];
1524 #define IPR_RES_TABLE_LABEL             "res_tbl"
1525         struct ipr_resource_entry *res_entries;
1526         struct list_head free_res_q;
1527         struct list_head used_res_q;
1528
1529         char ipr_hcam_label[8];
1530 #define IPR_HCAM_LABEL                  "hcams"
1531         struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1532         dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1533         struct list_head hostrcb_free_q;
1534         struct list_head hostrcb_pending_q;
1535
1536         struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1537         u32 hrrq_num;
1538         atomic_t  hrrq_index;
1539         u16 identify_hrrq_index;
1540
1541         struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1542
1543         unsigned int transop_timeout;
1544         const struct ipr_chip_cfg_t *chip_cfg;
1545         const struct ipr_chip_t *ipr_chip;
1546
1547         void __iomem *hdw_dma_regs;     /* iomapped PCI memory space */
1548         unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1549         void __iomem *ioa_mailbox;
1550         struct ipr_interrupts regs;
1551
1552         u16 saved_pcix_cmd_reg;
1553         u16 reset_retries;
1554
1555         u32 errors_logged;
1556         u32 doorbell;
1557
1558         struct Scsi_Host *host;
1559         struct pci_dev *pdev;
1560         struct ipr_sglist *ucode_sglist;
1561         u8 saved_mode_page_len;
1562
1563         struct work_struct work_q;
1564         struct workqueue_struct *reset_work_q;
1565
1566         wait_queue_head_t reset_wait_q;
1567         wait_queue_head_t msi_wait_q;
1568         wait_queue_head_t eeh_wait_q;
1569
1570         struct ipr_dump *dump;
1571         enum ipr_sdt_state sdt_state;
1572
1573         struct ipr_misc_cbs *vpd_cbs;
1574         dma_addr_t vpd_cbs_dma;
1575
1576         struct dma_pool *ipr_cmd_pool;
1577
1578         struct ipr_cmnd *reset_cmd;
1579         int (*reset) (struct ipr_cmnd *);
1580
1581         struct ata_host ata_host;
1582         char ipr_cmd_label[8];
1583 #define IPR_CMD_LABEL           "ipr_cmd"
1584         u32 max_cmds;
1585         struct ipr_cmnd **ipr_cmnd_list;
1586         dma_addr_t *ipr_cmnd_list_dma;
1587
1588         u16 intr_flag;
1589         unsigned int nvectors;
1590
1591         struct {
1592                 unsigned short vec;
1593                 char desc[22];
1594         } vectors_info[IPR_MAX_MSIX_VECTORS];
1595
1596         u32 iopoll_weight;
1597
1598 }; /* struct ipr_ioa_cfg */
1599
1600 struct ipr_cmnd {
1601         struct ipr_ioarcb ioarcb;
1602         union {
1603                 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1604                 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1605                 struct ipr_ata64_ioadl ata_ioadl;
1606         } i;
1607         union {
1608                 struct ipr_ioasa ioasa;
1609                 struct ipr_ioasa64 ioasa64;
1610         } s;
1611         struct list_head queue;
1612         struct scsi_cmnd *scsi_cmd;
1613         struct ata_queued_cmd *qc;
1614         struct completion completion;
1615         struct timer_list timer;
1616         struct work_struct work;
1617         void (*fast_done) (struct ipr_cmnd *);
1618         void (*done) (struct ipr_cmnd *);
1619         int (*job_step) (struct ipr_cmnd *);
1620         int (*job_step_failed) (struct ipr_cmnd *);
1621         u16 cmd_index;
1622         u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1623         dma_addr_t sense_buffer_dma;
1624         unsigned short dma_use_sg;
1625         dma_addr_t dma_addr;
1626         struct ipr_cmnd *sibling;
1627         union {
1628                 enum ipr_shutdown_type shutdown_type;
1629                 struct ipr_hostrcb *hostrcb;
1630                 unsigned long time_left;
1631                 unsigned long scratch;
1632                 struct ipr_resource_entry *res;
1633                 struct scsi_device *sdev;
1634         } u;
1635
1636         struct completion *eh_comp;
1637         struct ipr_hrr_queue *hrrq;
1638         struct ipr_ioa_cfg *ioa_cfg;
1639 };
1640
1641 struct ipr_ses_table_entry {
1642         char product_id[17];
1643         char compare_product_id_byte[17];
1644         u32 max_bus_speed_limit;        /* MB/sec limit for this backplane */
1645 };
1646
1647 struct ipr_dump_header {
1648         u32 eye_catcher;
1649 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1650         u32 len;
1651         u32 num_entries;
1652         u32 first_entry_offset;
1653         u32 status;
1654 #define IPR_DUMP_STATUS_SUCCESS                 0
1655 #define IPR_DUMP_STATUS_QUAL_SUCCESS            2
1656 #define IPR_DUMP_STATUS_FAILED                  0xffffffff
1657         u32 os;
1658 #define IPR_DUMP_OS_LINUX       0x4C4E5558
1659         u32 driver_name;
1660 #define IPR_DUMP_DRIVER_NAME    0x49505232
1661 }__attribute__((packed, aligned (4)));
1662
1663 struct ipr_dump_entry_header {
1664         u32 eye_catcher;
1665 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1666         u32 len;
1667         u32 num_elems;
1668         u32 offset;
1669         u32 data_type;
1670 #define IPR_DUMP_DATA_TYPE_ASCII        0x41534349
1671 #define IPR_DUMP_DATA_TYPE_BINARY       0x42494E41
1672         u32 id;
1673 #define IPR_DUMP_IOA_DUMP_ID            0x494F4131
1674 #define IPR_DUMP_LOCATION_ID            0x4C4F4341
1675 #define IPR_DUMP_TRACE_ID               0x54524143
1676 #define IPR_DUMP_DRIVER_VERSION_ID      0x44525652
1677 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1678 #define IPR_DUMP_IOA_CTRL_BLK           0x494F4342
1679 #define IPR_DUMP_PEND_OPS               0x414F5053
1680         u32 status;
1681 }__attribute__((packed, aligned (4)));
1682
1683 struct ipr_dump_location_entry {
1684         struct ipr_dump_entry_header hdr;
1685         u8 location[20];
1686 }__attribute__((packed));
1687
1688 struct ipr_dump_trace_entry {
1689         struct ipr_dump_entry_header hdr;
1690         u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1691 }__attribute__((packed, aligned (4)));
1692
1693 struct ipr_dump_version_entry {
1694         struct ipr_dump_entry_header hdr;
1695         u8 version[sizeof(IPR_DRIVER_VERSION)];
1696 };
1697
1698 struct ipr_dump_ioa_type_entry {
1699         struct ipr_dump_entry_header hdr;
1700         u32 type;
1701         u32 fw_version;
1702 };
1703
1704 struct ipr_driver_dump {
1705         struct ipr_dump_header hdr;
1706         struct ipr_dump_version_entry version_entry;
1707         struct ipr_dump_location_entry location_entry;
1708         struct ipr_dump_ioa_type_entry ioa_type_entry;
1709         struct ipr_dump_trace_entry trace_entry;
1710 }__attribute__((packed));
1711
1712 struct ipr_ioa_dump {
1713         struct ipr_dump_entry_header hdr;
1714         struct ipr_sdt sdt;
1715         __be32 **ioa_data;
1716         u32 reserved;
1717         u32 next_page_index;
1718         u32 page_offset;
1719         u32 format;
1720 }__attribute__((packed, aligned (4)));
1721
1722 struct ipr_dump {
1723         struct kref kref;
1724         struct ipr_ioa_cfg *ioa_cfg;
1725         struct ipr_driver_dump driver_dump;
1726         struct ipr_ioa_dump ioa_dump;
1727 };
1728
1729 struct ipr_error_table_t {
1730         u32 ioasc;
1731         int log_ioasa;
1732         int log_hcam;
1733         char *error;
1734 };
1735
1736 struct ipr_software_inq_lid_info {
1737         __be32 load_id;
1738         __be32 timestamp[3];
1739 }__attribute__((packed, aligned (4)));
1740
1741 struct ipr_ucode_image_header {
1742         __be32 header_length;
1743         __be32 lid_table_offset;
1744         u8 major_release;
1745         u8 card_type;
1746         u8 minor_release[2];
1747         u8 reserved[20];
1748         char eyecatcher[16];
1749         __be32 num_lids;
1750         struct ipr_software_inq_lid_info lid[1];
1751 }__attribute__((packed, aligned (4)));
1752
1753 /*
1754  * Macros
1755  */
1756 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1757
1758 #ifdef CONFIG_SCSI_IPR_TRACE
1759 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1760 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1761 #else
1762 #define ipr_create_trace_file(kobj, attr) 0
1763 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1764 #endif
1765
1766 #ifdef CONFIG_SCSI_IPR_DUMP
1767 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1768 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1769 #else
1770 #define ipr_create_dump_file(kobj, attr) 0
1771 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1772 #endif
1773
1774 /*
1775  * Error logging macros
1776  */
1777 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1778 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1779 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1780
1781 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1782         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1783                 bus, target, lun, ##__VA_ARGS__)
1784
1785 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1786         ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1787
1788 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1789         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1790                 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1791
1792 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1793         ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1794
1795 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)                        \
1796 {                                                                       \
1797         if ((res).bus >= IPR_MAX_NUM_BUSES) {                           \
1798                 ipr_err(fmt": unknown\n", ##__VA_ARGS__);               \
1799         } else {                                                        \
1800                 ipr_err(fmt": %d:%d:%d:%d\n",                           \
1801                         ##__VA_ARGS__, (ioa_cfg)->host->host_no,        \
1802                         (res).bus, (res).target, (res).lun);            \
1803         }                                                               \
1804 }
1805
1806 #define ipr_hcam_err(hostrcb, fmt, ...)                                 \
1807 {                                                                       \
1808         if (ipr_is_device(hostrcb)) {                                   \
1809                 if ((hostrcb)->ioa_cfg->sis64) {                        \
1810                         printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
1811                                 ipr_format_res_path(hostrcb->ioa_cfg,   \
1812                                         hostrcb->hcam.u.error64.fd_res_path, \
1813                                         hostrcb->rp_buffer,             \
1814                                         sizeof(hostrcb->rp_buffer)),    \
1815                                 __VA_ARGS__);                           \
1816                 } else {                                                \
1817                         ipr_ra_err((hostrcb)->ioa_cfg,                  \
1818                                 (hostrcb)->hcam.u.error.fd_res_addr,    \
1819                                 fmt, __VA_ARGS__);                      \
1820                 }                                                       \
1821         } else {                                                        \
1822                 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1823         }                                                               \
1824 }
1825
1826 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1827         __FILE__, __func__, __LINE__)
1828
1829 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1830 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1831
1832 #define ipr_err_separator \
1833 ipr_err("----------------------------------------------------------\n")
1834
1835
1836 /*
1837  * Inlines
1838  */
1839
1840 /**
1841  * ipr_is_ioa_resource - Determine if a resource is the IOA
1842  * @res:        resource entry struct
1843  *
1844  * Return value:
1845  *      1 if IOA / 0 if not IOA
1846  **/
1847 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1848 {
1849         return res->type == IPR_RES_TYPE_IOAFP;
1850 }
1851
1852 /**
1853  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1854  * @res:        resource entry struct
1855  *
1856  * Return value:
1857  *      1 if AF DASD / 0 if not AF DASD
1858  **/
1859 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1860 {
1861         return res->type == IPR_RES_TYPE_AF_DASD ||
1862                 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1863 }
1864
1865 /**
1866  * ipr_is_vset_device - Determine if a resource is a VSET
1867  * @res:        resource entry struct
1868  *
1869  * Return value:
1870  *      1 if VSET / 0 if not VSET
1871  **/
1872 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1873 {
1874         return res->type == IPR_RES_TYPE_VOLUME_SET;
1875 }
1876
1877 /**
1878  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1879  * @res:        resource entry struct
1880  *
1881  * Return value:
1882  *      1 if GSCSI / 0 if not GSCSI
1883  **/
1884 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1885 {
1886         return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1887 }
1888
1889 /**
1890  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1891  * @res:        resource entry struct
1892  *
1893  * Return value:
1894  *      1 if SCSI disk / 0 if not SCSI disk
1895  **/
1896 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1897 {
1898         if (ipr_is_af_dasd_device(res) ||
1899             (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1900                 return 1;
1901         else
1902                 return 0;
1903 }
1904
1905 /**
1906  * ipr_is_gata - Determine if a resource is a generic ATA resource
1907  * @res:        resource entry struct
1908  *
1909  * Return value:
1910  *      1 if GATA / 0 if not GATA
1911  **/
1912 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1913 {
1914         return res->type == IPR_RES_TYPE_GENERIC_ATA;
1915 }
1916
1917 /**
1918  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1919  * @res:        resource entry struct
1920  *
1921  * Return value:
1922  *      1 if NACA queueing model / 0 if not NACA queueing model
1923  **/
1924 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1925 {
1926         if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1927                 return 1;
1928         return 0;
1929 }
1930
1931 /**
1932  * ipr_is_device - Determine if the hostrcb structure is related to a device
1933  * @hostrcb:    host resource control blocks struct
1934  *
1935  * Return value:
1936  *      1 if AF / 0 if not AF
1937  **/
1938 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1939 {
1940         struct ipr_res_addr *res_addr;
1941         u8 *res_path;
1942
1943         if (hostrcb->ioa_cfg->sis64) {
1944                 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1945                 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1946                     res_path[0] == 0x81) && res_path[2] != 0xFF)
1947                         return 1;
1948         } else {
1949                 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1950
1951                 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1952                     (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1953                         return 1;
1954         }
1955         return 0;
1956 }
1957
1958 /**
1959  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1960  * @sdt_word:   SDT address
1961  *
1962  * Return value:
1963  *      1 if format 2 / 0 if not
1964  **/
1965 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1966 {
1967         u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1968
1969         switch (bar_sel) {
1970         case IPR_SDT_FMT2_BAR0_SEL:
1971         case IPR_SDT_FMT2_BAR1_SEL:
1972         case IPR_SDT_FMT2_BAR2_SEL:
1973         case IPR_SDT_FMT2_BAR3_SEL:
1974         case IPR_SDT_FMT2_BAR4_SEL:
1975         case IPR_SDT_FMT2_BAR5_SEL:
1976         case IPR_SDT_FMT2_EXP_ROM_SEL:
1977                 return 1;
1978         };
1979
1980         return 0;
1981 }
1982
1983 #ifndef writeq
1984 static inline void writeq(u64 val, void __iomem *addr)
1985 {
1986         writel(((u32) (val >> 32)), addr);
1987         writel(((u32) (val)), (addr + 4));
1988 }
1989 #endif
1990
1991 #endif /* _IPR_H */