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ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE build
[linux/fpc-iii.git] / drivers / spi / spi-pl022.c
blob5e5fd77e27119d6ceb8d64f657884ab4ef9f3759
1 /*
2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
3 *
4 * Copyright (C) 2008-2012 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 *
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/delay.h>
33 #include <linux/clk.h>
34 #include <linux/err.h>
35 #include <linux/amba/bus.h>
36 #include <linux/amba/pl022.h>
37 #include <linux/io.h>
38 #include <linux/slab.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/pinctrl/consumer.h>
46
47 /*
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
51 */
52 #define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54
55 /*
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
59 */
60 #define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
62
63 #define DRIVE_TX 0
64 #define DO_NOT_DRIVE_TX 1
65
66 #define DO_NOT_QUEUE_DMA 0
67 #define QUEUE_DMA 1
68
69 #define RX_TRANSFER 1
70 #define TX_TRANSFER 2
71
72 /*
73 * Macros to access SSP Registers with their offsets
74 */
75 #define SSP_CR0(r) (r + 0x000)
76 #define SSP_CR1(r) (r + 0x004)
77 #define SSP_DR(r) (r + 0x008)
78 #define SSP_SR(r) (r + 0x00C)
79 #define SSP_CPSR(r) (r + 0x010)
80 #define SSP_IMSC(r) (r + 0x014)
81 #define SSP_RIS(r) (r + 0x018)
82 #define SSP_MIS(r) (r + 0x01C)
83 #define SSP_ICR(r) (r + 0x020)
84 #define SSP_DMACR(r) (r + 0x024)
85 #define SSP_CSR(r) (r + 0x030) /* vendor extension */
86 #define SSP_ITCR(r) (r + 0x080)
87 #define SSP_ITIP(r) (r + 0x084)
88 #define SSP_ITOP(r) (r + 0x088)
89 #define SSP_TDR(r) (r + 0x08C)
90
91 #define SSP_PID0(r) (r + 0xFE0)
92 #define SSP_PID1(r) (r + 0xFE4)
93 #define SSP_PID2(r) (r + 0xFE8)
94 #define SSP_PID3(r) (r + 0xFEC)
95
96 #define SSP_CID0(r) (r + 0xFF0)
97 #define SSP_CID1(r) (r + 0xFF4)
98 #define SSP_CID2(r) (r + 0xFF8)
99 #define SSP_CID3(r) (r + 0xFFC)
100
101 /*
102 * SSP Control Register 0 - SSP_CR0
103 */
104 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
105 #define SSP_CR0_MASK_FRF (0x3UL << 4)
106 #define SSP_CR0_MASK_SPO (0x1UL << 6)
107 #define SSP_CR0_MASK_SPH (0x1UL << 7)
108 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
109
110 /*
111 * The ST version of this block moves som bits
112 * in SSP_CR0 and extends it to 32 bits
113 */
114 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
115 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
116 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
117 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
118
119 /*
120 * SSP Control Register 0 - SSP_CR1
121 */
122 #define SSP_CR1_MASK_LBM (0x1UL << 0)
123 #define SSP_CR1_MASK_SSE (0x1UL << 1)
124 #define SSP_CR1_MASK_MS (0x1UL << 2)
125 #define SSP_CR1_MASK_SOD (0x1UL << 3)
126
127 /*
128 * The ST version of this block adds some bits
129 * in SSP_CR1
130 */
131 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
132 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
133 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
134 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
135 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
136 /* This one is only in the PL023 variant */
137 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
138
139 /*
140 * SSP Status Register - SSP_SR
141 */
142 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
143 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
144 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
145 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
146 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
147
148 /*
149 * SSP Clock Prescale Register - SSP_CPSR
150 */
151 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
152
153 /*
154 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
155 */
156 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
157 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
158 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
159 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
160
161 /*
162 * SSP Raw Interrupt Status Register - SSP_RIS
163 */
164 /* Receive Overrun Raw Interrupt status */
165 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
166 /* Receive Timeout Raw Interrupt status */
167 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
168 /* Receive FIFO Raw Interrupt status */
169 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
170 /* Transmit FIFO Raw Interrupt status */
171 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
172
173 /*
174 * SSP Masked Interrupt Status Register - SSP_MIS
175 */
176 /* Receive Overrun Masked Interrupt status */
177 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
178 /* Receive Timeout Masked Interrupt status */
179 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
180 /* Receive FIFO Masked Interrupt status */
181 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
182 /* Transmit FIFO Masked Interrupt status */
183 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
184
185 /*
186 * SSP Interrupt Clear Register - SSP_ICR
187 */
188 /* Receive Overrun Raw Clear Interrupt bit */
189 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
190 /* Receive Timeout Clear Interrupt bit */
191 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
192
193 /*
194 * SSP DMA Control Register - SSP_DMACR
195 */
196 /* Receive DMA Enable bit */
197 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
198 /* Transmit DMA Enable bit */
199 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
200
201 /*
202 * SSP Chip Select Control Register - SSP_CSR
203 * (vendor extension)
204 */
205 #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0)
206
207 /*
208 * SSP Integration Test control Register - SSP_ITCR
209 */
210 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
211 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
212
213 /*
214 * SSP Integration Test Input Register - SSP_ITIP
215 */
216 #define ITIP_MASK_SSPRXD (0x1UL << 0)
217 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
218 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
219 #define ITIP_MASK_RXDMAC (0x1UL << 3)
220 #define ITIP_MASK_TXDMAC (0x1UL << 4)
221 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
222
223 /*
224 * SSP Integration Test output Register - SSP_ITOP
225 */
226 #define ITOP_MASK_SSPTXD (0x1UL << 0)
227 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
228 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
229 #define ITOP_MASK_SSPOEn (0x1UL << 3)
230 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
231 #define ITOP_MASK_RORINTR (0x1UL << 5)
232 #define ITOP_MASK_RTINTR (0x1UL << 6)
233 #define ITOP_MASK_RXINTR (0x1UL << 7)
234 #define ITOP_MASK_TXINTR (0x1UL << 8)
235 #define ITOP_MASK_INTR (0x1UL << 9)
236 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
237 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
238 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
239 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
240
241 /*
242 * SSP Test Data Register - SSP_TDR
243 */
244 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
245
246 /*
247 * Message State
248 * we use the spi_message.state (void *) pointer to
249 * hold a single state value, that's why all this
250 * (void *) casting is done here.
251 */
252 #define STATE_START ((void *) 0)
253 #define STATE_RUNNING ((void *) 1)
254 #define STATE_DONE ((void *) 2)
255 #define STATE_ERROR ((void *) -1)
256
257 /*
258 * SSP State - Whether Enabled or Disabled
259 */
260 #define SSP_DISABLED (0)
261 #define SSP_ENABLED (1)
262
263 /*
264 * SSP DMA State - Whether DMA Enabled or Disabled
265 */
266 #define SSP_DMA_DISABLED (0)
267 #define SSP_DMA_ENABLED (1)
268
269 /*
270 * SSP Clock Defaults
271 */
272 #define SSP_DEFAULT_CLKRATE 0x2
273 #define SSP_DEFAULT_PRESCALE 0x40
274
275 /*
276 * SSP Clock Parameter ranges
277 */
278 #define CPSDVR_MIN 0x02
279 #define CPSDVR_MAX 0xFE
280 #define SCR_MIN 0x00
281 #define SCR_MAX 0xFF
282
283 /*
284 * SSP Interrupt related Macros
285 */
286 #define DEFAULT_SSP_REG_IMSC 0x0UL
287 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
288 #define ENABLE_ALL_INTERRUPTS ( \
289 SSP_IMSC_MASK_RORIM | \
290 SSP_IMSC_MASK_RTIM | \
291 SSP_IMSC_MASK_RXIM | \
292 SSP_IMSC_MASK_TXIM \
293 )
294
295 #define CLEAR_ALL_INTERRUPTS 0x3
296
297 #define SPI_POLLING_TIMEOUT 1000
298
299 /*
300 * The type of reading going on on this chip
301 */
302 enum ssp_reading {
303 READING_NULL,
304 READING_U8,
305 READING_U16,
306 READING_U32
307 };
308
309 /**
310 * The type of writing going on on this chip
311 */
312 enum ssp_writing {
313 WRITING_NULL,
314 WRITING_U8,
315 WRITING_U16,
316 WRITING_U32
317 };
318
319 /**
320 * struct vendor_data - vendor-specific config parameters
321 * for PL022 derivates
322 * @fifodepth: depth of FIFOs (both)
323 * @max_bpw: maximum number of bits per word
324 * @unidir: supports unidirection transfers
325 * @extended_cr: 32 bit wide control register 0 with extra
326 * features and extra features in CR1 as found in the ST variants
327 * @pl023: supports a subset of the ST extensions called "PL023"
328 * @internal_cs_ctrl: supports chip select control register
329 */
330 struct vendor_data {
331 int fifodepth;
332 int max_bpw;
333 bool unidir;
334 bool extended_cr;
335 bool pl023;
336 bool loopback;
337 bool internal_cs_ctrl;
338 };
339
340 /**
341 * struct pl022 - This is the private SSP driver data structure
342 * @adev: AMBA device model hookup
343 * @vendor: vendor data for the IP block
344 * @phybase: the physical memory where the SSP device resides
345 * @virtbase: the virtual memory where the SSP is mapped
346 * @clk: outgoing clock "SPICLK" for the SPI bus
347 * @master: SPI framework hookup
348 * @master_info: controller-specific data from machine setup
349 * @kworker: thread struct for message pump
350 * @kworker_task: pointer to task for message pump kworker thread
351 * @pump_messages: work struct for scheduling work to the message pump
352 * @queue_lock: spinlock to syncronise access to message queue
353 * @queue: message queue
354 * @busy: message pump is busy
355 * @running: message pump is running
356 * @pump_transfers: Tasklet used in Interrupt Transfer mode
357 * @cur_msg: Pointer to current spi_message being processed
358 * @cur_transfer: Pointer to current spi_transfer
359 * @cur_chip: pointer to current clients chip(assigned from controller_state)
360 * @next_msg_cs_active: the next message in the queue has been examined
361 * and it was found that it uses the same chip select as the previous
362 * message, so we left it active after the previous transfer, and it's
363 * active already.
364 * @tx: current position in TX buffer to be read
365 * @tx_end: end position in TX buffer to be read
366 * @rx: current position in RX buffer to be written
367 * @rx_end: end position in RX buffer to be written
368 * @read: the type of read currently going on
369 * @write: the type of write currently going on
370 * @exp_fifo_level: expected FIFO level
371 * @dma_rx_channel: optional channel for RX DMA
372 * @dma_tx_channel: optional channel for TX DMA
373 * @sgt_rx: scattertable for the RX transfer
374 * @sgt_tx: scattertable for the TX transfer
375 * @dummypage: a dummy page used for driving data on the bus with DMA
376 * @cur_cs: current chip select (gpio)
377 * @chipselects: list of chipselects (gpios)
378 */
379 struct pl022 {
380 struct amba_device *adev;
381 struct vendor_data *vendor;
382 resource_size_t phybase;
383 void __iomem *virtbase;
384 struct clk *clk;
385 struct spi_master *master;
386 struct pl022_ssp_controller *master_info;
387 /* Message per-transfer pump */
388 struct tasklet_struct pump_transfers;
389 struct spi_message *cur_msg;
390 struct spi_transfer *cur_transfer;
391 struct chip_data *cur_chip;
392 bool next_msg_cs_active;
393 void *tx;
394 void *tx_end;
395 void *rx;
396 void *rx_end;
397 enum ssp_reading read;
398 enum ssp_writing write;
399 u32 exp_fifo_level;
400 enum ssp_rx_level_trig rx_lev_trig;
401 enum ssp_tx_level_trig tx_lev_trig;
402 /* DMA settings */
403 #ifdef CONFIG_DMA_ENGINE
404 struct dma_chan *dma_rx_channel;
405 struct dma_chan *dma_tx_channel;
406 struct sg_table sgt_rx;
407 struct sg_table sgt_tx;
408 char *dummypage;
409 bool dma_running;
410 #endif
411 int cur_cs;
412 int *chipselects;
413 };
414
415 /**
416 * struct chip_data - To maintain runtime state of SSP for each client chip
417 * @cr0: Value of control register CR0 of SSP - on later ST variants this
418 * register is 32 bits wide rather than just 16
419 * @cr1: Value of control register CR1 of SSP
420 * @dmacr: Value of DMA control Register of SSP
421 * @cpsr: Value of Clock prescale register
422 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
423 * @enable_dma: Whether to enable DMA or not
424 * @read: function ptr to be used to read when doing xfer for this chip
425 * @write: function ptr to be used to write when doing xfer for this chip
426 * @cs_control: chip select callback provided by chip
427 * @xfer_type: polling/interrupt/DMA
428 *
429 * Runtime state of the SSP controller, maintained per chip,
430 * This would be set according to the current message that would be served
431 */
432 struct chip_data {
433 u32 cr0;
434 u16 cr1;
435 u16 dmacr;
436 u16 cpsr;
437 u8 n_bytes;
438 bool enable_dma;
439 enum ssp_reading read;
440 enum ssp_writing write;
441 void (*cs_control) (u32 command);
442 int xfer_type;
443 };
444
445 /**
446 * null_cs_control - Dummy chip select function
447 * @command: select/delect the chip
448 *
449 * If no chip select function is provided by client this is used as dummy
450 * chip select
451 */
452 static void null_cs_control(u32 command)
453 {
454 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
455 }
456
457 /**
458 * internal_cs_control - Control chip select signals via SSP_CSR.
459 * @pl022: SSP driver private data structure
460 * @command: select/delect the chip
461 *
462 * Used on controller with internal chip select control via SSP_CSR register
463 * (vendor extension). Each of the 5 LSB in the register controls one chip
464 * select signal.
465 */
466 static void internal_cs_control(struct pl022 *pl022, u32 command)
467 {
468 u32 tmp;
469
470 tmp = readw(SSP_CSR(pl022->virtbase));
471 if (command == SSP_CHIP_SELECT)
472 tmp &= ~BIT(pl022->cur_cs);
473 else
474 tmp |= BIT(pl022->cur_cs);
475 writew(tmp, SSP_CSR(pl022->virtbase));
476 }
477
478 static void pl022_cs_control(struct pl022 *pl022, u32 command)
479 {
480 if (pl022->vendor->internal_cs_ctrl)
481 internal_cs_control(pl022, command);
482 else if (gpio_is_valid(pl022->cur_cs))
483 gpio_set_value(pl022->cur_cs, command);
484 else
485 pl022->cur_chip->cs_control(command);
486 }
487
488 /**
489 * giveback - current spi_message is over, schedule next message and call
490 * callback of this message. Assumes that caller already
491 * set message->status; dma and pio irqs are blocked
492 * @pl022: SSP driver private data structure
493 */
494 static void giveback(struct pl022 *pl022)
495 {
496 struct spi_transfer *last_transfer;
497 pl022->next_msg_cs_active = false;
498
499 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
500 struct spi_transfer, transfer_list);
501
502 /* Delay if requested before any change in chip select */
503 if (last_transfer->delay_usecs)
504 /*
505 * FIXME: This runs in interrupt context.
506 * Is this really smart?
507 */
508 udelay(last_transfer->delay_usecs);
509
510 if (!last_transfer->cs_change) {
511 struct spi_message *next_msg;
512
513 /*
514 * cs_change was not set. We can keep the chip select
515 * enabled if there is message in the queue and it is
516 * for the same spi device.
517 *
518 * We cannot postpone this until pump_messages, because
519 * after calling msg->complete (below) the driver that
520 * sent the current message could be unloaded, which
521 * could invalidate the cs_control() callback...
522 */
523 /* get a pointer to the next message, if any */
524 next_msg = spi_get_next_queued_message(pl022->master);
525
526 /*
527 * see if the next and current messages point
528 * to the same spi device.
529 */
530 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
531 next_msg = NULL;
532 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
533 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
534 else
535 pl022->next_msg_cs_active = true;
536
537 }
538
539 pl022->cur_msg = NULL;
540 pl022->cur_transfer = NULL;
541 pl022->cur_chip = NULL;
542
543 /* disable the SPI/SSP operation */
544 writew((readw(SSP_CR1(pl022->virtbase)) &
545 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
546
547 spi_finalize_current_message(pl022->master);
548 }
549
550 /**
551 * flush - flush the FIFO to reach a clean state
552 * @pl022: SSP driver private data structure
553 */
554 static int flush(struct pl022 *pl022)
555 {
556 unsigned long limit = loops_per_jiffy << 1;
557
558 dev_dbg(&pl022->adev->dev, "flush\n");
559 do {
560 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
561 readw(SSP_DR(pl022->virtbase));
562 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
563
564 pl022->exp_fifo_level = 0;
565
566 return limit;
567 }
568
569 /**
570 * restore_state - Load configuration of current chip
571 * @pl022: SSP driver private data structure
572 */
573 static void restore_state(struct pl022 *pl022)
574 {
575 struct chip_data *chip = pl022->cur_chip;
576
577 if (pl022->vendor->extended_cr)
578 writel(chip->cr0, SSP_CR0(pl022->virtbase));
579 else
580 writew(chip->cr0, SSP_CR0(pl022->virtbase));
581 writew(chip->cr1, SSP_CR1(pl022->virtbase));
582 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
583 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
584 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
585 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
586 }
587
588 /*
589 * Default SSP Register Values
590 */
591 #define DEFAULT_SSP_REG_CR0 ( \
592 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
593 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
594 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
595 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
596 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
597 )
598
599 /* ST versions have slightly different bit layout */
600 #define DEFAULT_SSP_REG_CR0_ST ( \
601 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
602 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
603 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
604 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
605 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
606 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
607 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
608 )
609
610 /* The PL023 version is slightly different again */
611 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
612 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
613 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
614 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
615 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
616 )
617
618 #define DEFAULT_SSP_REG_CR1 ( \
619 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
620 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
621 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
622 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
623 )
624
625 /* ST versions extend this register to use all 16 bits */
626 #define DEFAULT_SSP_REG_CR1_ST ( \
627 DEFAULT_SSP_REG_CR1 | \
628 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
629 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
630 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
631 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
632 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
633 )
634
635 /*
636 * The PL023 variant has further differences: no loopback mode, no microwire
637 * support, and a new clock feedback delay setting.
638 */
639 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
640 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
641 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
642 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
643 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
644 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
645 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
646 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
647 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
648 )
649
650 #define DEFAULT_SSP_REG_CPSR ( \
651 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
652 )
653
654 #define DEFAULT_SSP_REG_DMACR (\
655 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
656 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
657 )
658
659 /**
660 * load_ssp_default_config - Load default configuration for SSP
661 * @pl022: SSP driver private data structure
662 */
663 static void load_ssp_default_config(struct pl022 *pl022)
664 {
665 if (pl022->vendor->pl023) {
666 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
667 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
668 } else if (pl022->vendor->extended_cr) {
669 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
670 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
671 } else {
672 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
673 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
674 }
675 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
676 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
677 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
678 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
679 }
680
681 /**
682 * This will write to TX and read from RX according to the parameters
683 * set in pl022.
684 */
685 static void readwriter(struct pl022 *pl022)
686 {
687
688 /*
689 * The FIFO depth is different between primecell variants.
690 * I believe filling in too much in the FIFO might cause
691 * errons in 8bit wide transfers on ARM variants (just 8 words
692 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
693 *
694 * To prevent this issue, the TX FIFO is only filled to the
695 * unused RX FIFO fill length, regardless of what the TX
696 * FIFO status flag indicates.
697 */
698 dev_dbg(&pl022->adev->dev,
699 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
700 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
701
702 /* Read as much as you can */
703 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
704 && (pl022->rx < pl022->rx_end)) {
705 switch (pl022->read) {
706 case READING_NULL:
707 readw(SSP_DR(pl022->virtbase));
708 break;
709 case READING_U8:
710 *(u8 *) (pl022->rx) =
711 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
712 break;
713 case READING_U16:
714 *(u16 *) (pl022->rx) =
715 (u16) readw(SSP_DR(pl022->virtbase));
716 break;
717 case READING_U32:
718 *(u32 *) (pl022->rx) =
719 readl(SSP_DR(pl022->virtbase));
720 break;
721 }
722 pl022->rx += (pl022->cur_chip->n_bytes);
723 pl022->exp_fifo_level--;
724 }
725 /*
726 * Write as much as possible up to the RX FIFO size
727 */
728 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
729 && (pl022->tx < pl022->tx_end)) {
730 switch (pl022->write) {
731 case WRITING_NULL:
732 writew(0x0, SSP_DR(pl022->virtbase));
733 break;
734 case WRITING_U8:
735 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
736 break;
737 case WRITING_U16:
738 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
739 break;
740 case WRITING_U32:
741 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
742 break;
743 }
744 pl022->tx += (pl022->cur_chip->n_bytes);
745 pl022->exp_fifo_level++;
746 /*
747 * This inner reader takes care of things appearing in the RX
748 * FIFO as we're transmitting. This will happen a lot since the
749 * clock starts running when you put things into the TX FIFO,
750 * and then things are continuously clocked into the RX FIFO.
751 */
752 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
753 && (pl022->rx < pl022->rx_end)) {
754 switch (pl022->read) {
755 case READING_NULL:
756 readw(SSP_DR(pl022->virtbase));
757 break;
758 case READING_U8:
759 *(u8 *) (pl022->rx) =
760 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
761 break;
762 case READING_U16:
763 *(u16 *) (pl022->rx) =
764 (u16) readw(SSP_DR(pl022->virtbase));
765 break;
766 case READING_U32:
767 *(u32 *) (pl022->rx) =
768 readl(SSP_DR(pl022->virtbase));
769 break;
770 }
771 pl022->rx += (pl022->cur_chip->n_bytes);
772 pl022->exp_fifo_level--;
773 }
774 }
775 /*
776 * When we exit here the TX FIFO should be full and the RX FIFO
777 * should be empty
778 */
779 }
780
781 /**
782 * next_transfer - Move to the Next transfer in the current spi message
783 * @pl022: SSP driver private data structure
784 *
785 * This function moves though the linked list of spi transfers in the
786 * current spi message and returns with the state of current spi
787 * message i.e whether its last transfer is done(STATE_DONE) or
788 * Next transfer is ready(STATE_RUNNING)
789 */
790 static void *next_transfer(struct pl022 *pl022)
791 {
792 struct spi_message *msg = pl022->cur_msg;
793 struct spi_transfer *trans = pl022->cur_transfer;
794
795 /* Move to next transfer */
796 if (trans->transfer_list.next != &msg->transfers) {
797 pl022->cur_transfer =
798 list_entry(trans->transfer_list.next,
799 struct spi_transfer, transfer_list);
800 return STATE_RUNNING;
801 }
802 return STATE_DONE;
803 }
804
805 /*
806 * This DMA functionality is only compiled in if we have
807 * access to the generic DMA devices/DMA engine.
808 */
809 #ifdef CONFIG_DMA_ENGINE
810 static void unmap_free_dma_scatter(struct pl022 *pl022)
811 {
812 /* Unmap and free the SG tables */
813 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
814 pl022->sgt_tx.nents, DMA_TO_DEVICE);
815 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
816 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
817 sg_free_table(&pl022->sgt_rx);
818 sg_free_table(&pl022->sgt_tx);
819 }
820
821 static void dma_callback(void *data)
822 {
823 struct pl022 *pl022 = data;
824 struct spi_message *msg = pl022->cur_msg;
825
826 BUG_ON(!pl022->sgt_rx.sgl);
827
828 #ifdef VERBOSE_DEBUG
829 /*
830 * Optionally dump out buffers to inspect contents, this is
831 * good if you want to convince yourself that the loopback
832 * read/write contents are the same, when adopting to a new
833 * DMA engine.
834 */
835 {
836 struct scatterlist *sg;
837 unsigned int i;
838
839 dma_sync_sg_for_cpu(&pl022->adev->dev,
840 pl022->sgt_rx.sgl,
841 pl022->sgt_rx.nents,
842 DMA_FROM_DEVICE);
843
844 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
845 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
846 print_hex_dump(KERN_ERR, "SPI RX: ",
847 DUMP_PREFIX_OFFSET,
848 16,
849 1,
850 sg_virt(sg),
851 sg_dma_len(sg),
852 1);
853 }
854 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
855 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
856 print_hex_dump(KERN_ERR, "SPI TX: ",
857 DUMP_PREFIX_OFFSET,
858 16,
859 1,
860 sg_virt(sg),
861 sg_dma_len(sg),
862 1);
863 }
864 }
865 #endif
866
867 unmap_free_dma_scatter(pl022);
868
869 /* Update total bytes transferred */
870 msg->actual_length += pl022->cur_transfer->len;
871 if (pl022->cur_transfer->cs_change)
872 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
873
874 /* Move to next transfer */
875 msg->state = next_transfer(pl022);
876 tasklet_schedule(&pl022->pump_transfers);
877 }
878
879 static void setup_dma_scatter(struct pl022 *pl022,
880 void *buffer,
881 unsigned int length,
882 struct sg_table *sgtab)
883 {
884 struct scatterlist *sg;
885 int bytesleft = length;
886 void *bufp = buffer;
887 int mapbytes;
888 int i;
889
890 if (buffer) {
891 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
892 /*
893 * If there are less bytes left than what fits
894 * in the current page (plus page alignment offset)
895 * we just feed in this, else we stuff in as much
896 * as we can.
897 */
898 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
899 mapbytes = bytesleft;
900 else
901 mapbytes = PAGE_SIZE - offset_in_page(bufp);
902 sg_set_page(sg, virt_to_page(bufp),
903 mapbytes, offset_in_page(bufp));
904 bufp += mapbytes;
905 bytesleft -= mapbytes;
906 dev_dbg(&pl022->adev->dev,
907 "set RX/TX target page @ %p, %d bytes, %d left\n",
908 bufp, mapbytes, bytesleft);
909 }
910 } else {
911 /* Map the dummy buffer on every page */
912 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
913 if (bytesleft < PAGE_SIZE)
914 mapbytes = bytesleft;
915 else
916 mapbytes = PAGE_SIZE;
917 sg_set_page(sg, virt_to_page(pl022->dummypage),
918 mapbytes, 0);
919 bytesleft -= mapbytes;
920 dev_dbg(&pl022->adev->dev,
921 "set RX/TX to dummy page %d bytes, %d left\n",
922 mapbytes, bytesleft);
923
924 }
925 }
926 BUG_ON(bytesleft);
927 }
928
929 /**
930 * configure_dma - configures the channels for the next transfer
931 * @pl022: SSP driver's private data structure
932 */
933 static int configure_dma(struct pl022 *pl022)
934 {
935 struct dma_slave_config rx_conf = {
936 .src_addr = SSP_DR(pl022->phybase),
937 .direction = DMA_DEV_TO_MEM,
938 .device_fc = false,
939 };
940 struct dma_slave_config tx_conf = {
941 .dst_addr = SSP_DR(pl022->phybase),
942 .direction = DMA_MEM_TO_DEV,
943 .device_fc = false,
944 };
945 unsigned int pages;
946 int ret;
947 int rx_sglen, tx_sglen;
948 struct dma_chan *rxchan = pl022->dma_rx_channel;
949 struct dma_chan *txchan = pl022->dma_tx_channel;
950 struct dma_async_tx_descriptor *rxdesc;
951 struct dma_async_tx_descriptor *txdesc;
952
953 /* Check that the channels are available */
954 if (!rxchan || !txchan)
955 return -ENODEV;
956
957 /*
958 * If supplied, the DMA burstsize should equal the FIFO trigger level.
959 * Notice that the DMA engine uses one-to-one mapping. Since we can
960 * not trigger on 2 elements this needs explicit mapping rather than
961 * calculation.
962 */
963 switch (pl022->rx_lev_trig) {
964 case SSP_RX_1_OR_MORE_ELEM:
965 rx_conf.src_maxburst = 1;
966 break;
967 case SSP_RX_4_OR_MORE_ELEM:
968 rx_conf.src_maxburst = 4;
969 break;
970 case SSP_RX_8_OR_MORE_ELEM:
971 rx_conf.src_maxburst = 8;
972 break;
973 case SSP_RX_16_OR_MORE_ELEM:
974 rx_conf.src_maxburst = 16;
975 break;
976 case SSP_RX_32_OR_MORE_ELEM:
977 rx_conf.src_maxburst = 32;
978 break;
979 default:
980 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
981 break;
982 }
983
984 switch (pl022->tx_lev_trig) {
985 case SSP_TX_1_OR_MORE_EMPTY_LOC:
986 tx_conf.dst_maxburst = 1;
987 break;
988 case SSP_TX_4_OR_MORE_EMPTY_LOC:
989 tx_conf.dst_maxburst = 4;
990 break;
991 case SSP_TX_8_OR_MORE_EMPTY_LOC:
992 tx_conf.dst_maxburst = 8;
993 break;
994 case SSP_TX_16_OR_MORE_EMPTY_LOC:
995 tx_conf.dst_maxburst = 16;
996 break;
997 case SSP_TX_32_OR_MORE_EMPTY_LOC:
998 tx_conf.dst_maxburst = 32;
999 break;
1000 default:
1001 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
1002 break;
1003 }
1004
1005 switch (pl022->read) {
1006 case READING_NULL:
1007 /* Use the same as for writing */
1008 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1009 break;
1010 case READING_U8:
1011 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1012 break;
1013 case READING_U16:
1014 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1015 break;
1016 case READING_U32:
1017 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1018 break;
1019 }
1020
1021 switch (pl022->write) {
1022 case WRITING_NULL:
1023 /* Use the same as for reading */
1024 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1025 break;
1026 case WRITING_U8:
1027 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1028 break;
1029 case WRITING_U16:
1030 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1031 break;
1032 case WRITING_U32:
1033 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1034 break;
1035 }
1036
1037 /* SPI pecularity: we need to read and write the same width */
1038 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1039 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1040 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1041 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1042 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1043
1044 dmaengine_slave_config(rxchan, &rx_conf);
1045 dmaengine_slave_config(txchan, &tx_conf);
1046
1047 /* Create sglists for the transfers */
1048 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1049 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1050
1051 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1052 if (ret)
1053 goto err_alloc_rx_sg;
1054
1055 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1056 if (ret)
1057 goto err_alloc_tx_sg;
1058
1059 /* Fill in the scatterlists for the RX+TX buffers */
1060 setup_dma_scatter(pl022, pl022->rx,
1061 pl022->cur_transfer->len, &pl022->sgt_rx);
1062 setup_dma_scatter(pl022, pl022->tx,
1063 pl022->cur_transfer->len, &pl022->sgt_tx);
1064
1065 /* Map DMA buffers */
1066 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1067 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1068 if (!rx_sglen)
1069 goto err_rx_sgmap;
1070
1071 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1072 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1073 if (!tx_sglen)
1074 goto err_tx_sgmap;
1075
1076 /* Send both scatterlists */
1077 rxdesc = dmaengine_prep_slave_sg(rxchan,
1078 pl022->sgt_rx.sgl,
1079 rx_sglen,
1080 DMA_DEV_TO_MEM,
1081 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1082 if (!rxdesc)
1083 goto err_rxdesc;
1084
1085 txdesc = dmaengine_prep_slave_sg(txchan,
1086 pl022->sgt_tx.sgl,
1087 tx_sglen,
1088 DMA_MEM_TO_DEV,
1089 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1090 if (!txdesc)
1091 goto err_txdesc;
1092
1093 /* Put the callback on the RX transfer only, that should finish last */
1094 rxdesc->callback = dma_callback;
1095 rxdesc->callback_param = pl022;
1096
1097 /* Submit and fire RX and TX with TX last so we're ready to read! */
1098 dmaengine_submit(rxdesc);
1099 dmaengine_submit(txdesc);
1100 dma_async_issue_pending(rxchan);
1101 dma_async_issue_pending(txchan);
1102 pl022->dma_running = true;
1103
1104 return 0;
1105
1106 err_txdesc:
1107 dmaengine_terminate_all(txchan);
1108 err_rxdesc:
1109 dmaengine_terminate_all(rxchan);
1110 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1111 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1112 err_tx_sgmap:
1113 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1114 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1115 err_rx_sgmap:
1116 sg_free_table(&pl022->sgt_tx);
1117 err_alloc_tx_sg:
1118 sg_free_table(&pl022->sgt_rx);
1119 err_alloc_rx_sg:
1120 return -ENOMEM;
1121 }
1122
1123 static int pl022_dma_probe(struct pl022 *pl022)
1124 {
1125 dma_cap_mask_t mask;
1126
1127 /* Try to acquire a generic DMA engine slave channel */
1128 dma_cap_zero(mask);
1129 dma_cap_set(DMA_SLAVE, mask);
1130 /*
1131 * We need both RX and TX channels to do DMA, else do none
1132 * of them.
1133 */
1134 pl022->dma_rx_channel = dma_request_channel(mask,
1135 pl022->master_info->dma_filter,
1136 pl022->master_info->dma_rx_param);
1137 if (!pl022->dma_rx_channel) {
1138 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1139 goto err_no_rxchan;
1140 }
1141
1142 pl022->dma_tx_channel = dma_request_channel(mask,
1143 pl022->master_info->dma_filter,
1144 pl022->master_info->dma_tx_param);
1145 if (!pl022->dma_tx_channel) {
1146 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1147 goto err_no_txchan;
1148 }
1149
1150 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1151 if (!pl022->dummypage)
1152 goto err_no_dummypage;
1153
1154 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1155 dma_chan_name(pl022->dma_rx_channel),
1156 dma_chan_name(pl022->dma_tx_channel));
1157
1158 return 0;
1159
1160 err_no_dummypage:
1161 dma_release_channel(pl022->dma_tx_channel);
1162 err_no_txchan:
1163 dma_release_channel(pl022->dma_rx_channel);
1164 pl022->dma_rx_channel = NULL;
1165 err_no_rxchan:
1166 dev_err(&pl022->adev->dev,
1167 "Failed to work in dma mode, work without dma!\n");
1168 return -ENODEV;
1169 }
1170
1171 static int pl022_dma_autoprobe(struct pl022 *pl022)
1172 {
1173 struct device *dev = &pl022->adev->dev;
1174 struct dma_chan *chan;
1175 int err;
1176
1177 /* automatically configure DMA channels from platform, normally using DT */
1178 chan = dma_request_slave_channel_reason(dev, "rx");
1179 if (IS_ERR(chan)) {
1180 err = PTR_ERR(chan);
1181 goto err_no_rxchan;
1182 }
1183
1184 pl022->dma_rx_channel = chan;
1185
1186 chan = dma_request_slave_channel_reason(dev, "tx");
1187 if (IS_ERR(chan)) {
1188 err = PTR_ERR(chan);
1189 goto err_no_txchan;
1190 }
1191
1192 pl022->dma_tx_channel = chan;
1193
1194 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1195 if (!pl022->dummypage) {
1196 err = -ENOMEM;
1197 goto err_no_dummypage;
1198 }
1199
1200 return 0;
1201
1202 err_no_dummypage:
1203 dma_release_channel(pl022->dma_tx_channel);
1204 pl022->dma_tx_channel = NULL;
1205 err_no_txchan:
1206 dma_release_channel(pl022->dma_rx_channel);
1207 pl022->dma_rx_channel = NULL;
1208 err_no_rxchan:
1209 return err;
1210 }
1211
1212 static void terminate_dma(struct pl022 *pl022)
1213 {
1214 struct dma_chan *rxchan = pl022->dma_rx_channel;
1215 struct dma_chan *txchan = pl022->dma_tx_channel;
1216
1217 dmaengine_terminate_all(rxchan);
1218 dmaengine_terminate_all(txchan);
1219 unmap_free_dma_scatter(pl022);
1220 pl022->dma_running = false;
1221 }
1222
1223 static void pl022_dma_remove(struct pl022 *pl022)
1224 {
1225 if (pl022->dma_running)
1226 terminate_dma(pl022);
1227 if (pl022->dma_tx_channel)
1228 dma_release_channel(pl022->dma_tx_channel);
1229 if (pl022->dma_rx_channel)
1230 dma_release_channel(pl022->dma_rx_channel);
1231 kfree(pl022->dummypage);
1232 }
1233
1234 #else
1235 static inline int configure_dma(struct pl022 *pl022)
1236 {
1237 return -ENODEV;
1238 }
1239
1240 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1241 {
1242 return 0;
1243 }
1244
1245 static inline int pl022_dma_probe(struct pl022 *pl022)
1246 {
1247 return 0;
1248 }
1249
1250 static inline void pl022_dma_remove(struct pl022 *pl022)
1251 {
1252 }
1253 #endif
1254
1255 /**
1256 * pl022_interrupt_handler - Interrupt handler for SSP controller
1257 *
1258 * This function handles interrupts generated for an interrupt based transfer.
1259 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1260 * current message's state as STATE_ERROR and schedule the tasklet
1261 * pump_transfers which will do the postprocessing of the current message by
1262 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1263 * more data, and writes data in TX FIFO till it is not full. If we complete
1264 * the transfer we move to the next transfer and schedule the tasklet.
1265 */
1266 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1267 {
1268 struct pl022 *pl022 = dev_id;
1269 struct spi_message *msg = pl022->cur_msg;
1270 u16 irq_status = 0;
1271
1272 if (unlikely(!msg)) {
1273 dev_err(&pl022->adev->dev,
1274 "bad message state in interrupt handler");
1275 /* Never fail */
1276 return IRQ_HANDLED;
1277 }
1278
1279 /* Read the Interrupt Status Register */
1280 irq_status = readw(SSP_MIS(pl022->virtbase));
1281
1282 if (unlikely(!irq_status))
1283 return IRQ_NONE;
1284
1285 /*
1286 * This handles the FIFO interrupts, the timeout
1287 * interrupts are flatly ignored, they cannot be
1288 * trusted.
1289 */
1290 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1291 /*
1292 * Overrun interrupt - bail out since our Data has been
1293 * corrupted
1294 */
1295 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1296 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1297 dev_err(&pl022->adev->dev,
1298 "RXFIFO is full\n");
1299
1300 /*
1301 * Disable and clear interrupts, disable SSP,
1302 * mark message with bad status so it can be
1303 * retried.
1304 */
1305 writew(DISABLE_ALL_INTERRUPTS,
1306 SSP_IMSC(pl022->virtbase));
1307 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1308 writew((readw(SSP_CR1(pl022->virtbase)) &
1309 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1310 msg->state = STATE_ERROR;
1311
1312 /* Schedule message queue handler */
1313 tasklet_schedule(&pl022->pump_transfers);
1314 return IRQ_HANDLED;
1315 }
1316
1317 readwriter(pl022);
1318
1319 if (pl022->tx == pl022->tx_end) {
1320 /* Disable Transmit interrupt, enable receive interrupt */
1321 writew((readw(SSP_IMSC(pl022->virtbase)) &
1322 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1323 SSP_IMSC(pl022->virtbase));
1324 }
1325
1326 /*
1327 * Since all transactions must write as much as shall be read,
1328 * we can conclude the entire transaction once RX is complete.
1329 * At this point, all TX will always be finished.
1330 */
1331 if (pl022->rx >= pl022->rx_end) {
1332 writew(DISABLE_ALL_INTERRUPTS,
1333 SSP_IMSC(pl022->virtbase));
1334 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1335 if (unlikely(pl022->rx > pl022->rx_end)) {
1336 dev_warn(&pl022->adev->dev, "read %u surplus "
1337 "bytes (did you request an odd "
1338 "number of bytes on a 16bit bus?)\n",
1339 (u32) (pl022->rx - pl022->rx_end));
1340 }
1341 /* Update total bytes transferred */
1342 msg->actual_length += pl022->cur_transfer->len;
1343 if (pl022->cur_transfer->cs_change)
1344 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1345 /* Move to next transfer */
1346 msg->state = next_transfer(pl022);
1347 tasklet_schedule(&pl022->pump_transfers);
1348 return IRQ_HANDLED;
1349 }
1350
1351 return IRQ_HANDLED;
1352 }
1353
1354 /**
1355 * This sets up the pointers to memory for the next message to
1356 * send out on the SPI bus.
1357 */
1358 static int set_up_next_transfer(struct pl022 *pl022,
1359 struct spi_transfer *transfer)
1360 {
1361 int residue;
1362
1363 /* Sanity check the message for this bus width */
1364 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1365 if (unlikely(residue != 0)) {
1366 dev_err(&pl022->adev->dev,
1367 "message of %u bytes to transmit but the current "
1368 "chip bus has a data width of %u bytes!\n",
1369 pl022->cur_transfer->len,
1370 pl022->cur_chip->n_bytes);
1371 dev_err(&pl022->adev->dev, "skipping this message\n");
1372 return -EIO;
1373 }
1374 pl022->tx = (void *)transfer->tx_buf;
1375 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1376 pl022->rx = (void *)transfer->rx_buf;
1377 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1378 pl022->write =
1379 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1380 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1381 return 0;
1382 }
1383
1384 /**
1385 * pump_transfers - Tasklet function which schedules next transfer
1386 * when running in interrupt or DMA transfer mode.
1387 * @data: SSP driver private data structure
1388 *
1389 */
1390 static void pump_transfers(unsigned long data)
1391 {
1392 struct pl022 *pl022 = (struct pl022 *) data;
1393 struct spi_message *message = NULL;
1394 struct spi_transfer *transfer = NULL;
1395 struct spi_transfer *previous = NULL;
1396
1397 /* Get current state information */
1398 message = pl022->cur_msg;
1399 transfer = pl022->cur_transfer;
1400
1401 /* Handle for abort */
1402 if (message->state == STATE_ERROR) {
1403 message->status = -EIO;
1404 giveback(pl022);
1405 return;
1406 }
1407
1408 /* Handle end of message */
1409 if (message->state == STATE_DONE) {
1410 message->status = 0;
1411 giveback(pl022);
1412 return;
1413 }
1414
1415 /* Delay if requested at end of transfer before CS change */
1416 if (message->state == STATE_RUNNING) {
1417 previous = list_entry(transfer->transfer_list.prev,
1418 struct spi_transfer,
1419 transfer_list);
1420 if (previous->delay_usecs)
1421 /*
1422 * FIXME: This runs in interrupt context.
1423 * Is this really smart?
1424 */
1425 udelay(previous->delay_usecs);
1426
1427 /* Reselect chip select only if cs_change was requested */
1428 if (previous->cs_change)
1429 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1430 } else {
1431 /* STATE_START */
1432 message->state = STATE_RUNNING;
1433 }
1434
1435 if (set_up_next_transfer(pl022, transfer)) {
1436 message->state = STATE_ERROR;
1437 message->status = -EIO;
1438 giveback(pl022);
1439 return;
1440 }
1441 /* Flush the FIFOs and let's go! */
1442 flush(pl022);
1443
1444 if (pl022->cur_chip->enable_dma) {
1445 if (configure_dma(pl022)) {
1446 dev_dbg(&pl022->adev->dev,
1447 "configuration of DMA failed, fall back to interrupt mode\n");
1448 goto err_config_dma;
1449 }
1450 return;
1451 }
1452
1453 err_config_dma:
1454 /* enable all interrupts except RX */
1455 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1456 }
1457
1458 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1459 {
1460 /*
1461 * Default is to enable all interrupts except RX -
1462 * this will be enabled once TX is complete
1463 */
1464 u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
1465
1466 /* Enable target chip, if not already active */
1467 if (!pl022->next_msg_cs_active)
1468 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1469
1470 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1471 /* Error path */
1472 pl022->cur_msg->state = STATE_ERROR;
1473 pl022->cur_msg->status = -EIO;
1474 giveback(pl022);
1475 return;
1476 }
1477 /* If we're using DMA, set up DMA here */
1478 if (pl022->cur_chip->enable_dma) {
1479 /* Configure DMA transfer */
1480 if (configure_dma(pl022)) {
1481 dev_dbg(&pl022->adev->dev,
1482 "configuration of DMA failed, fall back to interrupt mode\n");
1483 goto err_config_dma;
1484 }
1485 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1486 irqflags = DISABLE_ALL_INTERRUPTS;
1487 }
1488 err_config_dma:
1489 /* Enable SSP, turn on interrupts */
1490 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1491 SSP_CR1(pl022->virtbase));
1492 writew(irqflags, SSP_IMSC(pl022->virtbase));
1493 }
1494
1495 static void do_polling_transfer(struct pl022 *pl022)
1496 {
1497 struct spi_message *message = NULL;
1498 struct spi_transfer *transfer = NULL;
1499 struct spi_transfer *previous = NULL;
1500 struct chip_data *chip;
1501 unsigned long time, timeout;
1502
1503 chip = pl022->cur_chip;
1504 message = pl022->cur_msg;
1505
1506 while (message->state != STATE_DONE) {
1507 /* Handle for abort */
1508 if (message->state == STATE_ERROR)
1509 break;
1510 transfer = pl022->cur_transfer;
1511
1512 /* Delay if requested at end of transfer */
1513 if (message->state == STATE_RUNNING) {
1514 previous =
1515 list_entry(transfer->transfer_list.prev,
1516 struct spi_transfer, transfer_list);
1517 if (previous->delay_usecs)
1518 udelay(previous->delay_usecs);
1519 if (previous->cs_change)
1520 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1521 } else {
1522 /* STATE_START */
1523 message->state = STATE_RUNNING;
1524 if (!pl022->next_msg_cs_active)
1525 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1526 }
1527
1528 /* Configuration Changing Per Transfer */
1529 if (set_up_next_transfer(pl022, transfer)) {
1530 /* Error path */
1531 message->state = STATE_ERROR;
1532 break;
1533 }
1534 /* Flush FIFOs and enable SSP */
1535 flush(pl022);
1536 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1537 SSP_CR1(pl022->virtbase));
1538
1539 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1540
1541 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1542 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1543 time = jiffies;
1544 readwriter(pl022);
1545 if (time_after(time, timeout)) {
1546 dev_warn(&pl022->adev->dev,
1547 "%s: timeout!\n", __func__);
1548 message->state = STATE_ERROR;
1549 goto out;
1550 }
1551 cpu_relax();
1552 }
1553
1554 /* Update total byte transferred */
1555 message->actual_length += pl022->cur_transfer->len;
1556 if (pl022->cur_transfer->cs_change)
1557 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1558 /* Move to next transfer */
1559 message->state = next_transfer(pl022);
1560 }
1561 out:
1562 /* Handle end of message */
1563 if (message->state == STATE_DONE)
1564 message->status = 0;
1565 else
1566 message->status = -EIO;
1567
1568 giveback(pl022);
1569 return;
1570 }
1571
1572 static int pl022_transfer_one_message(struct spi_master *master,
1573 struct spi_message *msg)
1574 {
1575 struct pl022 *pl022 = spi_master_get_devdata(master);
1576
1577 /* Initial message state */
1578 pl022->cur_msg = msg;
1579 msg->state = STATE_START;
1580
1581 pl022->cur_transfer = list_entry(msg->transfers.next,
1582 struct spi_transfer, transfer_list);
1583
1584 /* Setup the SPI using the per chip configuration */
1585 pl022->cur_chip = spi_get_ctldata(msg->spi);
1586 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1587
1588 restore_state(pl022);
1589 flush(pl022);
1590
1591 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1592 do_polling_transfer(pl022);
1593 else
1594 do_interrupt_dma_transfer(pl022);
1595
1596 return 0;
1597 }
1598
1599 static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1600 {
1601 struct pl022 *pl022 = spi_master_get_devdata(master);
1602
1603 /* nothing more to do - disable spi/ssp and power off */
1604 writew((readw(SSP_CR1(pl022->virtbase)) &
1605 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1606
1607 return 0;
1608 }
1609
1610 static int verify_controller_parameters(struct pl022 *pl022,
1611 struct pl022_config_chip const *chip_info)
1612 {
1613 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1614 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1615 dev_err(&pl022->adev->dev,
1616 "interface is configured incorrectly\n");
1617 return -EINVAL;
1618 }
1619 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1620 (!pl022->vendor->unidir)) {
1621 dev_err(&pl022->adev->dev,
1622 "unidirectional mode not supported in this "
1623 "hardware version\n");
1624 return -EINVAL;
1625 }
1626 if ((chip_info->hierarchy != SSP_MASTER)
1627 && (chip_info->hierarchy != SSP_SLAVE)) {
1628 dev_err(&pl022->adev->dev,
1629 "hierarchy is configured incorrectly\n");
1630 return -EINVAL;
1631 }
1632 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1633 && (chip_info->com_mode != DMA_TRANSFER)
1634 && (chip_info->com_mode != POLLING_TRANSFER)) {
1635 dev_err(&pl022->adev->dev,
1636 "Communication mode is configured incorrectly\n");
1637 return -EINVAL;
1638 }
1639 switch (chip_info->rx_lev_trig) {
1640 case SSP_RX_1_OR_MORE_ELEM:
1641 case SSP_RX_4_OR_MORE_ELEM:
1642 case SSP_RX_8_OR_MORE_ELEM:
1643 /* These are always OK, all variants can handle this */
1644 break;
1645 case SSP_RX_16_OR_MORE_ELEM:
1646 if (pl022->vendor->fifodepth < 16) {
1647 dev_err(&pl022->adev->dev,
1648 "RX FIFO Trigger Level is configured incorrectly\n");
1649 return -EINVAL;
1650 }
1651 break;
1652 case SSP_RX_32_OR_MORE_ELEM:
1653 if (pl022->vendor->fifodepth < 32) {
1654 dev_err(&pl022->adev->dev,
1655 "RX FIFO Trigger Level is configured incorrectly\n");
1656 return -EINVAL;
1657 }
1658 break;
1659 default:
1660 dev_err(&pl022->adev->dev,
1661 "RX FIFO Trigger Level is configured incorrectly\n");
1662 return -EINVAL;
1663 }
1664 switch (chip_info->tx_lev_trig) {
1665 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1666 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1667 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1668 /* These are always OK, all variants can handle this */
1669 break;
1670 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1671 if (pl022->vendor->fifodepth < 16) {
1672 dev_err(&pl022->adev->dev,
1673 "TX FIFO Trigger Level is configured incorrectly\n");
1674 return -EINVAL;
1675 }
1676 break;
1677 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1678 if (pl022->vendor->fifodepth < 32) {
1679 dev_err(&pl022->adev->dev,
1680 "TX FIFO Trigger Level is configured incorrectly\n");
1681 return -EINVAL;
1682 }
1683 break;
1684 default:
1685 dev_err(&pl022->adev->dev,
1686 "TX FIFO Trigger Level is configured incorrectly\n");
1687 return -EINVAL;
1688 }
1689 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1690 if ((chip_info->ctrl_len < SSP_BITS_4)
1691 || (chip_info->ctrl_len > SSP_BITS_32)) {
1692 dev_err(&pl022->adev->dev,
1693 "CTRL LEN is configured incorrectly\n");
1694 return -EINVAL;
1695 }
1696 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1697 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1698 dev_err(&pl022->adev->dev,
1699 "Wait State is configured incorrectly\n");
1700 return -EINVAL;
1701 }
1702 /* Half duplex is only available in the ST Micro version */
1703 if (pl022->vendor->extended_cr) {
1704 if ((chip_info->duplex !=
1705 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1706 && (chip_info->duplex !=
1707 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1708 dev_err(&pl022->adev->dev,
1709 "Microwire duplex mode is configured incorrectly\n");
1710 return -EINVAL;
1711 }
1712 } else {
1713 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1714 dev_err(&pl022->adev->dev,
1715 "Microwire half duplex mode requested,"
1716 " but this is only available in the"
1717 " ST version of PL022\n");
1718 return -EINVAL;
1719 }
1720 }
1721 return 0;
1722 }
1723
1724 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1725 {
1726 return rate / (cpsdvsr * (1 + scr));
1727 }
1728
1729 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1730 ssp_clock_params * clk_freq)
1731 {
1732 /* Lets calculate the frequency parameters */
1733 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1734 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1735 best_scr = 0, tmp, found = 0;
1736
1737 rate = clk_get_rate(pl022->clk);
1738 /* cpsdvscr = 2 & scr 0 */
1739 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1740 /* cpsdvsr = 254 & scr = 255 */
1741 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1742
1743 if (freq > max_tclk)
1744 dev_warn(&pl022->adev->dev,
1745 "Max speed that can be programmed is %d Hz, you requested %d\n",
1746 max_tclk, freq);
1747
1748 if (freq < min_tclk) {
1749 dev_err(&pl022->adev->dev,
1750 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1751 freq, min_tclk);
1752 return -EINVAL;
1753 }
1754
1755 /*
1756 * best_freq will give closest possible available rate (<= requested
1757 * freq) for all values of scr & cpsdvsr.
1758 */
1759 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1760 while (scr <= SCR_MAX) {
1761 tmp = spi_rate(rate, cpsdvsr, scr);
1762
1763 if (tmp > freq) {
1764 /* we need lower freq */
1765 scr++;
1766 continue;
1767 }
1768
1769 /*
1770 * If found exact value, mark found and break.
1771 * If found more closer value, update and break.
1772 */
1773 if (tmp > best_freq) {
1774 best_freq = tmp;
1775 best_cpsdvsr = cpsdvsr;
1776 best_scr = scr;
1777
1778 if (tmp == freq)
1779 found = 1;
1780 }
1781 /*
1782 * increased scr will give lower rates, which are not
1783 * required
1784 */
1785 break;
1786 }
1787 cpsdvsr += 2;
1788 scr = SCR_MIN;
1789 }
1790
1791 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1792 freq);
1793
1794 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1795 clk_freq->scr = (u8) (best_scr & 0xFF);
1796 dev_dbg(&pl022->adev->dev,
1797 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1798 freq, best_freq);
1799 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1800 clk_freq->cpsdvsr, clk_freq->scr);
1801
1802 return 0;
1803 }
1804
1805 /*
1806 * A piece of default chip info unless the platform
1807 * supplies it.
1808 */
1809 static const struct pl022_config_chip pl022_default_chip_info = {
1810 .com_mode = POLLING_TRANSFER,
1811 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1812 .hierarchy = SSP_SLAVE,
1813 .slave_tx_disable = DO_NOT_DRIVE_TX,
1814 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1815 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1816 .ctrl_len = SSP_BITS_8,
1817 .wait_state = SSP_MWIRE_WAIT_ZERO,
1818 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1819 .cs_control = null_cs_control,
1820 };
1821
1822 /**
1823 * pl022_setup - setup function registered to SPI master framework
1824 * @spi: spi device which is requesting setup
1825 *
1826 * This function is registered to the SPI framework for this SPI master
1827 * controller. If it is the first time when setup is called by this device,
1828 * this function will initialize the runtime state for this chip and save
1829 * the same in the device structure. Else it will update the runtime info
1830 * with the updated chip info. Nothing is really being written to the
1831 * controller hardware here, that is not done until the actual transfer
1832 * commence.
1833 */
1834 static int pl022_setup(struct spi_device *spi)
1835 {
1836 struct pl022_config_chip const *chip_info;
1837 struct pl022_config_chip chip_info_dt;
1838 struct chip_data *chip;
1839 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1840 int status = 0;
1841 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1842 unsigned int bits = spi->bits_per_word;
1843 u32 tmp;
1844 struct device_node *np = spi->dev.of_node;
1845
1846 if (!spi->max_speed_hz)
1847 return -EINVAL;
1848
1849 /* Get controller_state if one is supplied */
1850 chip = spi_get_ctldata(spi);
1851
1852 if (chip == NULL) {
1853 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1854 if (!chip)
1855 return -ENOMEM;
1856 dev_dbg(&spi->dev,
1857 "allocated memory for controller's runtime state\n");
1858 }
1859
1860 /* Get controller data if one is supplied */
1861 chip_info = spi->controller_data;
1862
1863 if (chip_info == NULL) {
1864 if (np) {
1865 chip_info_dt = pl022_default_chip_info;
1866
1867 chip_info_dt.hierarchy = SSP_MASTER;
1868 of_property_read_u32(np, "pl022,interface",
1869 &chip_info_dt.iface);
1870 of_property_read_u32(np, "pl022,com-mode",
1871 &chip_info_dt.com_mode);
1872 of_property_read_u32(np, "pl022,rx-level-trig",
1873 &chip_info_dt.rx_lev_trig);
1874 of_property_read_u32(np, "pl022,tx-level-trig",
1875 &chip_info_dt.tx_lev_trig);
1876 of_property_read_u32(np, "pl022,ctrl-len",
1877 &chip_info_dt.ctrl_len);
1878 of_property_read_u32(np, "pl022,wait-state",
1879 &chip_info_dt.wait_state);
1880 of_property_read_u32(np, "pl022,duplex",
1881 &chip_info_dt.duplex);
1882
1883 chip_info = &chip_info_dt;
1884 } else {
1885 chip_info = &pl022_default_chip_info;
1886 /* spi_board_info.controller_data not is supplied */
1887 dev_dbg(&spi->dev,
1888 "using default controller_data settings\n");
1889 }
1890 } else
1891 dev_dbg(&spi->dev,
1892 "using user supplied controller_data settings\n");
1893
1894 /*
1895 * We can override with custom divisors, else we use the board
1896 * frequency setting
1897 */
1898 if ((0 == chip_info->clk_freq.cpsdvsr)
1899 && (0 == chip_info->clk_freq.scr)) {
1900 status = calculate_effective_freq(pl022,
1901 spi->max_speed_hz,
1902 &clk_freq);
1903 if (status < 0)
1904 goto err_config_params;
1905 } else {
1906 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1907 if ((clk_freq.cpsdvsr % 2) != 0)
1908 clk_freq.cpsdvsr =
1909 clk_freq.cpsdvsr - 1;
1910 }
1911 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1912 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1913 status = -EINVAL;
1914 dev_err(&spi->dev,
1915 "cpsdvsr is configured incorrectly\n");
1916 goto err_config_params;
1917 }
1918
1919 status = verify_controller_parameters(pl022, chip_info);
1920 if (status) {
1921 dev_err(&spi->dev, "controller data is incorrect");
1922 goto err_config_params;
1923 }
1924
1925 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1926 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1927
1928 /* Now set controller state based on controller data */
1929 chip->xfer_type = chip_info->com_mode;
1930 if (!chip_info->cs_control) {
1931 chip->cs_control = null_cs_control;
1932 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1933 dev_warn(&spi->dev,
1934 "invalid chip select\n");
1935 } else
1936 chip->cs_control = chip_info->cs_control;
1937
1938 /* Check bits per word with vendor specific range */
1939 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1940 status = -ENOTSUPP;
1941 dev_err(&spi->dev, "illegal data size for this controller!\n");
1942 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1943 pl022->vendor->max_bpw);
1944 goto err_config_params;
1945 } else if (bits <= 8) {
1946 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1947 chip->n_bytes = 1;
1948 chip->read = READING_U8;
1949 chip->write = WRITING_U8;
1950 } else if (bits <= 16) {
1951 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1952 chip->n_bytes = 2;
1953 chip->read = READING_U16;
1954 chip->write = WRITING_U16;
1955 } else {
1956 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1957 chip->n_bytes = 4;
1958 chip->read = READING_U32;
1959 chip->write = WRITING_U32;
1960 }
1961
1962 /* Now Initialize all register settings required for this chip */
1963 chip->cr0 = 0;
1964 chip->cr1 = 0;
1965 chip->dmacr = 0;
1966 chip->cpsr = 0;
1967 if ((chip_info->com_mode == DMA_TRANSFER)
1968 && ((pl022->master_info)->enable_dma)) {
1969 chip->enable_dma = true;
1970 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1971 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1972 SSP_DMACR_MASK_RXDMAE, 0);
1973 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1974 SSP_DMACR_MASK_TXDMAE, 1);
1975 } else {
1976 chip->enable_dma = false;
1977 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1978 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1979 SSP_DMACR_MASK_RXDMAE, 0);
1980 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1981 SSP_DMACR_MASK_TXDMAE, 1);
1982 }
1983
1984 chip->cpsr = clk_freq.cpsdvsr;
1985
1986 /* Special setup for the ST micro extended control registers */
1987 if (pl022->vendor->extended_cr) {
1988 u32 etx;
1989
1990 if (pl022->vendor->pl023) {
1991 /* These bits are only in the PL023 */
1992 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1993 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1994 } else {
1995 /* These bits are in the PL022 but not PL023 */
1996 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1997 SSP_CR0_MASK_HALFDUP_ST, 5);
1998 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1999 SSP_CR0_MASK_CSS_ST, 16);
2000 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2001 SSP_CR0_MASK_FRF_ST, 21);
2002 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2003 SSP_CR1_MASK_MWAIT_ST, 6);
2004 }
2005 SSP_WRITE_BITS(chip->cr0, bits - 1,
2006 SSP_CR0_MASK_DSS_ST, 0);
2007
2008 if (spi->mode & SPI_LSB_FIRST) {
2009 tmp = SSP_RX_LSB;
2010 etx = SSP_TX_LSB;
2011 } else {
2012 tmp = SSP_RX_MSB;
2013 etx = SSP_TX_MSB;
2014 }
2015 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2016 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2017 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2018 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2019 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2020 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2021 } else {
2022 SSP_WRITE_BITS(chip->cr0, bits - 1,
2023 SSP_CR0_MASK_DSS, 0);
2024 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2025 SSP_CR0_MASK_FRF, 4);
2026 }
2027
2028 /* Stuff that is common for all versions */
2029 if (spi->mode & SPI_CPOL)
2030 tmp = SSP_CLK_POL_IDLE_HIGH;
2031 else
2032 tmp = SSP_CLK_POL_IDLE_LOW;
2033 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2034
2035 if (spi->mode & SPI_CPHA)
2036 tmp = SSP_CLK_SECOND_EDGE;
2037 else
2038 tmp = SSP_CLK_FIRST_EDGE;
2039 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2040
2041 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2042 /* Loopback is available on all versions except PL023 */
2043 if (pl022->vendor->loopback) {
2044 if (spi->mode & SPI_LOOP)
2045 tmp = LOOPBACK_ENABLED;
2046 else
2047 tmp = LOOPBACK_DISABLED;
2048 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2049 }
2050 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2051 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2052 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2053 3);
2054
2055 /* Save controller_state */
2056 spi_set_ctldata(spi, chip);
2057 return status;
2058 err_config_params:
2059 spi_set_ctldata(spi, NULL);
2060 kfree(chip);
2061 return status;
2062 }
2063
2064 /**
2065 * pl022_cleanup - cleanup function registered to SPI master framework
2066 * @spi: spi device which is requesting cleanup
2067 *
2068 * This function is registered to the SPI framework for this SPI master
2069 * controller. It will free the runtime state of chip.
2070 */
2071 static void pl022_cleanup(struct spi_device *spi)
2072 {
2073 struct chip_data *chip = spi_get_ctldata(spi);
2074
2075 spi_set_ctldata(spi, NULL);
2076 kfree(chip);
2077 }
2078
2079 static struct pl022_ssp_controller *
2080 pl022_platform_data_dt_get(struct device *dev)
2081 {
2082 struct device_node *np = dev->of_node;
2083 struct pl022_ssp_controller *pd;
2084 u32 tmp;
2085
2086 if (!np) {
2087 dev_err(dev, "no dt node defined\n");
2088 return NULL;
2089 }
2090
2091 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2092 if (!pd)
2093 return NULL;
2094
2095 pd->bus_id = -1;
2096 pd->enable_dma = 1;
2097 of_property_read_u32(np, "num-cs", &tmp);
2098 pd->num_chipselect = tmp;
2099 of_property_read_u32(np, "pl022,autosuspend-delay",
2100 &pd->autosuspend_delay);
2101 pd->rt = of_property_read_bool(np, "pl022,rt");
2102
2103 return pd;
2104 }
2105
2106 static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2107 {
2108 struct device *dev = &adev->dev;
2109 struct pl022_ssp_controller *platform_info =
2110 dev_get_platdata(&adev->dev);
2111 struct spi_master *master;
2112 struct pl022 *pl022 = NULL; /*Data for this driver */
2113 struct device_node *np = adev->dev.of_node;
2114 int status = 0, i, num_cs;
2115
2116 dev_info(&adev->dev,
2117 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2118 if (!platform_info && IS_ENABLED(CONFIG_OF))
2119 platform_info = pl022_platform_data_dt_get(dev);
2120
2121 if (!platform_info) {
2122 dev_err(dev, "probe: no platform data defined\n");
2123 return -ENODEV;
2124 }
2125
2126 if (platform_info->num_chipselect) {
2127 num_cs = platform_info->num_chipselect;
2128 } else {
2129 dev_err(dev, "probe: no chip select defined\n");
2130 return -ENODEV;
2131 }
2132
2133 /* Allocate master with space for data */
2134 master = spi_alloc_master(dev, sizeof(struct pl022));
2135 if (master == NULL) {
2136 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2137 return -ENOMEM;
2138 }
2139
2140 pl022 = spi_master_get_devdata(master);
2141 pl022->master = master;
2142 pl022->master_info = platform_info;
2143 pl022->adev = adev;
2144 pl022->vendor = id->data;
2145 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2146 GFP_KERNEL);
2147 if (!pl022->chipselects) {
2148 status = -ENOMEM;
2149 goto err_no_mem;
2150 }
2151
2152 /*
2153 * Bus Number Which has been Assigned to this SSP controller
2154 * on this board
2155 */
2156 master->bus_num = platform_info->bus_id;
2157 master->num_chipselect = num_cs;
2158 master->cleanup = pl022_cleanup;
2159 master->setup = pl022_setup;
2160 master->auto_runtime_pm = true;
2161 master->transfer_one_message = pl022_transfer_one_message;
2162 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2163 master->rt = platform_info->rt;
2164 master->dev.of_node = dev->of_node;
2165
2166 if (platform_info->num_chipselect && platform_info->chipselects) {
2167 for (i = 0; i < num_cs; i++)
2168 pl022->chipselects[i] = platform_info->chipselects[i];
2169 } else if (pl022->vendor->internal_cs_ctrl) {
2170 for (i = 0; i < num_cs; i++)
2171 pl022->chipselects[i] = i;
2172 } else if (IS_ENABLED(CONFIG_OF)) {
2173 for (i = 0; i < num_cs; i++) {
2174 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2175
2176 if (cs_gpio == -EPROBE_DEFER) {
2177 status = -EPROBE_DEFER;
2178 goto err_no_gpio;
2179 }
2180
2181 pl022->chipselects[i] = cs_gpio;
2182
2183 if (gpio_is_valid(cs_gpio)) {
2184 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2185 dev_err(&adev->dev,
2186 "could not request %d gpio\n",
2187 cs_gpio);
2188 else if (gpio_direction_output(cs_gpio, 1))
2189 dev_err(&adev->dev,
2190 "could not set gpio %d as output\n",
2191 cs_gpio);
2192 }
2193 }
2194 }
2195
2196 /*
2197 * Supports mode 0-3, loopback, and active low CS. Transfers are
2198 * always MS bit first on the original pl022.
2199 */
2200 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2201 if (pl022->vendor->extended_cr)
2202 master->mode_bits |= SPI_LSB_FIRST;
2203
2204 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2205
2206 status = amba_request_regions(adev, NULL);
2207 if (status)
2208 goto err_no_ioregion;
2209
2210 pl022->phybase = adev->res.start;
2211 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2212 resource_size(&adev->res));
2213 if (pl022->virtbase == NULL) {
2214 status = -ENOMEM;
2215 goto err_no_ioremap;
2216 }
2217 dev_info(&adev->dev, "mapped registers from %pa to %p\n",
2218 &adev->res.start, pl022->virtbase);
2219
2220 pl022->clk = devm_clk_get(&adev->dev, NULL);
2221 if (IS_ERR(pl022->clk)) {
2222 status = PTR_ERR(pl022->clk);
2223 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2224 goto err_no_clk;
2225 }
2226
2227 status = clk_prepare_enable(pl022->clk);
2228 if (status) {
2229 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2230 goto err_no_clk_en;
2231 }
2232
2233 /* Initialize transfer pump */
2234 tasklet_init(&pl022->pump_transfers, pump_transfers,
2235 (unsigned long)pl022);
2236
2237 /* Disable SSP */
2238 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2239 SSP_CR1(pl022->virtbase));
2240 load_ssp_default_config(pl022);
2241
2242 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2243 0, "pl022", pl022);
2244 if (status < 0) {
2245 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2246 goto err_no_irq;
2247 }
2248
2249 /* Get DMA channels, try autoconfiguration first */
2250 status = pl022_dma_autoprobe(pl022);
2251 if (status == -EPROBE_DEFER) {
2252 dev_dbg(dev, "deferring probe to get DMA channel\n");
2253 goto err_no_irq;
2254 }
2255
2256 /* If that failed, use channels from platform_info */
2257 if (status == 0)
2258 platform_info->enable_dma = 1;
2259 else if (platform_info->enable_dma) {
2260 status = pl022_dma_probe(pl022);
2261 if (status != 0)
2262 platform_info->enable_dma = 0;
2263 }
2264
2265 /* Register with the SPI framework */
2266 amba_set_drvdata(adev, pl022);
2267 status = devm_spi_register_master(&adev->dev, master);
2268 if (status != 0) {
2269 dev_err(&adev->dev,
2270 "probe - problem registering spi master\n");
2271 goto err_spi_register;
2272 }
2273 dev_dbg(dev, "probe succeeded\n");
2274
2275 /* let runtime pm put suspend */
2276 if (platform_info->autosuspend_delay > 0) {
2277 dev_info(&adev->dev,
2278 "will use autosuspend for runtime pm, delay %dms\n",
2279 platform_info->autosuspend_delay);
2280 pm_runtime_set_autosuspend_delay(dev,
2281 platform_info->autosuspend_delay);
2282 pm_runtime_use_autosuspend(dev);
2283 }
2284 pm_runtime_put(dev);
2285
2286 return 0;
2287
2288 err_spi_register:
2289 if (platform_info->enable_dma)
2290 pl022_dma_remove(pl022);
2291 err_no_irq:
2292 clk_disable_unprepare(pl022->clk);
2293 err_no_clk_en:
2294 err_no_clk:
2295 err_no_ioremap:
2296 amba_release_regions(adev);
2297 err_no_ioregion:
2298 err_no_gpio:
2299 err_no_mem:
2300 spi_master_put(master);
2301 return status;
2302 }
2303
2304 static int
2305 pl022_remove(struct amba_device *adev)
2306 {
2307 struct pl022 *pl022 = amba_get_drvdata(adev);
2308
2309 if (!pl022)
2310 return 0;
2311
2312 /*
2313 * undo pm_runtime_put() in probe. I assume that we're not
2314 * accessing the primecell here.
2315 */
2316 pm_runtime_get_noresume(&adev->dev);
2317
2318 load_ssp_default_config(pl022);
2319 if (pl022->master_info->enable_dma)
2320 pl022_dma_remove(pl022);
2321
2322 clk_disable_unprepare(pl022->clk);
2323 amba_release_regions(adev);
2324 tasklet_disable(&pl022->pump_transfers);
2325 return 0;
2326 }
2327
2328 #ifdef CONFIG_PM_SLEEP
2329 static int pl022_suspend(struct device *dev)
2330 {
2331 struct pl022 *pl022 = dev_get_drvdata(dev);
2332 int ret;
2333
2334 ret = spi_master_suspend(pl022->master);
2335 if (ret) {
2336 dev_warn(dev, "cannot suspend master\n");
2337 return ret;
2338 }
2339
2340 ret = pm_runtime_force_suspend(dev);
2341 if (ret) {
2342 spi_master_resume(pl022->master);
2343 return ret;
2344 }
2345
2346 pinctrl_pm_select_sleep_state(dev);
2347
2348 dev_dbg(dev, "suspended\n");
2349 return 0;
2350 }
2351
2352 static int pl022_resume(struct device *dev)
2353 {
2354 struct pl022 *pl022 = dev_get_drvdata(dev);
2355 int ret;
2356
2357 ret = pm_runtime_force_resume(dev);
2358 if (ret)
2359 dev_err(dev, "problem resuming\n");
2360
2361 /* Start the queue running */
2362 ret = spi_master_resume(pl022->master);
2363 if (ret)
2364 dev_err(dev, "problem starting queue (%d)\n", ret);
2365 else
2366 dev_dbg(dev, "resumed\n");
2367
2368 return ret;
2369 }
2370 #endif
2371
2372 #ifdef CONFIG_PM
2373 static int pl022_runtime_suspend(struct device *dev)
2374 {
2375 struct pl022 *pl022 = dev_get_drvdata(dev);
2376
2377 clk_disable_unprepare(pl022->clk);
2378 pinctrl_pm_select_idle_state(dev);
2379
2380 return 0;
2381 }
2382
2383 static int pl022_runtime_resume(struct device *dev)
2384 {
2385 struct pl022 *pl022 = dev_get_drvdata(dev);
2386
2387 pinctrl_pm_select_default_state(dev);
2388 clk_prepare_enable(pl022->clk);
2389
2390 return 0;
2391 }
2392 #endif
2393
2394 static const struct dev_pm_ops pl022_dev_pm_ops = {
2395 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2396 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2397 };
2398
2399 static struct vendor_data vendor_arm = {
2400 .fifodepth = 8,
2401 .max_bpw = 16,
2402 .unidir = false,
2403 .extended_cr = false,
2404 .pl023 = false,
2405 .loopback = true,
2406 .internal_cs_ctrl = false,
2407 };
2408
2409 static struct vendor_data vendor_st = {
2410 .fifodepth = 32,
2411 .max_bpw = 32,
2412 .unidir = false,
2413 .extended_cr = true,
2414 .pl023 = false,
2415 .loopback = true,
2416 .internal_cs_ctrl = false,
2417 };
2418
2419 static struct vendor_data vendor_st_pl023 = {
2420 .fifodepth = 32,
2421 .max_bpw = 32,
2422 .unidir = false,
2423 .extended_cr = true,
2424 .pl023 = true,
2425 .loopback = false,
2426 .internal_cs_ctrl = false,
2427 };
2428
2429 static struct vendor_data vendor_lsi = {
2430 .fifodepth = 8,
2431 .max_bpw = 16,
2432 .unidir = false,
2433 .extended_cr = false,
2434 .pl023 = false,
2435 .loopback = true,
2436 .internal_cs_ctrl = true,
2437 };
2438
2439 static struct amba_id pl022_ids[] = {
2440 {
2441 /*
2442 * ARM PL022 variant, this has a 16bit wide
2443 * and 8 locations deep TX/RX FIFO
2444 */
2445 .id = 0x00041022,
2446 .mask = 0x000fffff,
2447 .data = &vendor_arm,
2448 },
2449 {
2450 /*
2451 * ST Micro derivative, this has 32bit wide
2452 * and 32 locations deep TX/RX FIFO
2453 */
2454 .id = 0x01080022,
2455 .mask = 0xffffffff,
2456 .data = &vendor_st,
2457 },
2458 {
2459 /*
2460 * ST-Ericsson derivative "PL023" (this is not
2461 * an official ARM number), this is a PL022 SSP block
2462 * stripped to SPI mode only, it has 32bit wide
2463 * and 32 locations deep TX/RX FIFO but no extended
2464 * CR0/CR1 register
2465 */
2466 .id = 0x00080023,
2467 .mask = 0xffffffff,
2468 .data = &vendor_st_pl023,
2469 },
2470 {
2471 /*
2472 * PL022 variant that has a chip select control register whih
2473 * allows control of 5 output signals nCS[0:4].
2474 */
2475 .id = 0x000b6022,
2476 .mask = 0x000fffff,
2477 .data = &vendor_lsi,
2478 },
2479 { 0, 0 },
2480 };
2481
2482 MODULE_DEVICE_TABLE(amba, pl022_ids);
2483
2484 static struct amba_driver pl022_driver = {
2485 .drv = {
2486 .name = "ssp-pl022",
2487 .pm = &pl022_dev_pm_ops,
2488 },
2489 .id_table = pl022_ids,
2490 .probe = pl022_probe,
2491 .remove = pl022_remove,
2492 };
2493
2494 static int __init pl022_init(void)
2495 {
2496 return amba_driver_register(&pl022_driver);
2497 }
2498 subsys_initcall(pl022_init);
2499
2500 static void __exit pl022_exit(void)
2501 {
2502 amba_driver_unregister(&pl022_driver);
2503 }
2504 module_exit(pl022_exit);
2505
2506 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2507 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2508 MODULE_LICENSE("GPL");
Linux with added FPC-III support