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ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE build
[linux/fpc-iii.git] / drivers / spi / spi-pxa2xx.c
blobab9914ad8365a6b1fb31f107dab21dac4ef94b17
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
35
36 #include "spi-pxa2xx.h"
37
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
42
43 #define TIMOUT_DFLT 1000
44
45 /*
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
51 */
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
69 #define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
70 #define LPSS_CAPS_CS_EN_SHIFT 9
71 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73 struct lpss_config {
74 /* LPSS offset from drv_data->ioaddr */
75 unsigned offset;
76 /* Register offsets from drv_data->lpss_base or -1 */
77 int reg_general;
78 int reg_ssp;
79 int reg_cs_ctrl;
80 int reg_capabilities;
81 /* FIFO thresholds */
82 u32 rx_threshold;
83 u32 tx_threshold_lo;
84 u32 tx_threshold_hi;
85 };
86
87 /* Keep these sorted with enum pxa_ssp_type */
88 static const struct lpss_config lpss_platforms[] = {
89 { /* LPSS_LPT_SSP */
90 .offset = 0x800,
91 .reg_general = 0x08,
92 .reg_ssp = 0x0c,
93 .reg_cs_ctrl = 0x18,
94 .reg_capabilities = -1,
95 .rx_threshold = 64,
96 .tx_threshold_lo = 160,
97 .tx_threshold_hi = 224,
98 },
99 { /* LPSS_BYT_SSP */
100 .offset = 0x400,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_SPT_SSP */
110 .offset = 0x200,
111 .reg_general = -1,
112 .reg_ssp = 0x20,
113 .reg_cs_ctrl = 0x24,
114 .reg_capabilities = 0xfc,
115 .rx_threshold = 1,
116 .tx_threshold_lo = 32,
117 .tx_threshold_hi = 56,
118 },
119 { /* LPSS_BXT_SSP */
120 .offset = 0x200,
121 .reg_general = -1,
122 .reg_ssp = 0x20,
123 .reg_cs_ctrl = 0x24,
124 .reg_capabilities = 0xfc,
125 .rx_threshold = 1,
126 .tx_threshold_lo = 16,
127 .tx_threshold_hi = 48,
128 },
129 };
130
131 static inline const struct lpss_config
132 *lpss_get_config(const struct driver_data *drv_data)
133 {
134 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
135 }
136
137 static bool is_lpss_ssp(const struct driver_data *drv_data)
138 {
139 switch (drv_data->ssp_type) {
140 case LPSS_LPT_SSP:
141 case LPSS_BYT_SSP:
142 case LPSS_SPT_SSP:
143 case LPSS_BXT_SSP:
144 return true;
145 default:
146 return false;
147 }
148 }
149
150 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
151 {
152 return drv_data->ssp_type == QUARK_X1000_SSP;
153 }
154
155 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
156 {
157 switch (drv_data->ssp_type) {
158 case QUARK_X1000_SSP:
159 return QUARK_X1000_SSCR1_CHANGE_MASK;
160 default:
161 return SSCR1_CHANGE_MASK;
162 }
163 }
164
165 static u32
166 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
167 {
168 switch (drv_data->ssp_type) {
169 case QUARK_X1000_SSP:
170 return RX_THRESH_QUARK_X1000_DFLT;
171 default:
172 return RX_THRESH_DFLT;
173 }
174 }
175
176 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
177 {
178 u32 mask;
179
180 switch (drv_data->ssp_type) {
181 case QUARK_X1000_SSP:
182 mask = QUARK_X1000_SSSR_TFL_MASK;
183 break;
184 default:
185 mask = SSSR_TFL_MASK;
186 break;
187 }
188
189 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
190 }
191
192 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
193 u32 *sccr1_reg)
194 {
195 u32 mask;
196
197 switch (drv_data->ssp_type) {
198 case QUARK_X1000_SSP:
199 mask = QUARK_X1000_SSCR1_RFT;
200 break;
201 default:
202 mask = SSCR1_RFT;
203 break;
204 }
205 *sccr1_reg &= ~mask;
206 }
207
208 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
209 u32 *sccr1_reg, u32 threshold)
210 {
211 switch (drv_data->ssp_type) {
212 case QUARK_X1000_SSP:
213 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
214 break;
215 default:
216 *sccr1_reg |= SSCR1_RxTresh(threshold);
217 break;
218 }
219 }
220
221 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
222 u32 clk_div, u8 bits)
223 {
224 switch (drv_data->ssp_type) {
225 case QUARK_X1000_SSP:
226 return clk_div
227 | QUARK_X1000_SSCR0_Motorola
228 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
229 | SSCR0_SSE;
230 default:
231 return clk_div
232 | SSCR0_Motorola
233 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
234 | SSCR0_SSE
235 | (bits > 16 ? SSCR0_EDSS : 0);
236 }
237 }
238
239 /*
240 * Read and write LPSS SSP private registers. Caller must first check that
241 * is_lpss_ssp() returns true before these can be called.
242 */
243 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
244 {
245 WARN_ON(!drv_data->lpss_base);
246 return readl(drv_data->lpss_base + offset);
247 }
248
249 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
250 unsigned offset, u32 value)
251 {
252 WARN_ON(!drv_data->lpss_base);
253 writel(value, drv_data->lpss_base + offset);
254 }
255
256 /*
257 * lpss_ssp_setup - perform LPSS SSP specific setup
258 * @drv_data: pointer to the driver private data
259 *
260 * Perform LPSS SSP specific setup. This function must be called first if
261 * one is going to use LPSS SSP private registers.
262 */
263 static void lpss_ssp_setup(struct driver_data *drv_data)
264 {
265 const struct lpss_config *config;
266 u32 value;
267
268 config = lpss_get_config(drv_data);
269 drv_data->lpss_base = drv_data->ioaddr + config->offset;
270
271 /* Enable software chip select control */
272 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
273 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
274 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
275 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
276
277 /* Enable multiblock DMA transfers */
278 if (drv_data->master_info->enable_dma) {
279 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
280
281 if (config->reg_general >= 0) {
282 value = __lpss_ssp_read_priv(drv_data,
283 config->reg_general);
284 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
285 __lpss_ssp_write_priv(drv_data,
286 config->reg_general, value);
287 }
288 }
289 }
290
291 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
292 {
293 const struct lpss_config *config;
294 u32 value, cs;
295
296 config = lpss_get_config(drv_data);
297
298 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
299 if (enable) {
300 cs = drv_data->cur_msg->spi->chip_select;
301 cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT;
302 if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) {
303 /*
304 * When switching another chip select output active
305 * the output must be selected first and wait 2 ssp_clk
306 * cycles before changing state to active. Otherwise
307 * a short glitch will occur on the previous chip
308 * select since output select is latched but state
309 * control is not.
310 */
311 value &= ~LPSS_CS_CONTROL_CS_SEL_MASK;
312 value |= cs;
313 __lpss_ssp_write_priv(drv_data,
314 config->reg_cs_ctrl, value);
315 ndelay(1000000000 /
316 (drv_data->master->max_speed_hz / 2));
317 }
318 value &= ~LPSS_CS_CONTROL_CS_HIGH;
319 } else {
320 value |= LPSS_CS_CONTROL_CS_HIGH;
321 }
322 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
323 }
324
325 static void cs_assert(struct driver_data *drv_data)
326 {
327 struct chip_data *chip = drv_data->cur_chip;
328
329 if (drv_data->ssp_type == CE4100_SSP) {
330 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
331 return;
332 }
333
334 if (chip->cs_control) {
335 chip->cs_control(PXA2XX_CS_ASSERT);
336 return;
337 }
338
339 if (gpio_is_valid(chip->gpio_cs)) {
340 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
341 return;
342 }
343
344 if (is_lpss_ssp(drv_data))
345 lpss_ssp_cs_control(drv_data, true);
346 }
347
348 static void cs_deassert(struct driver_data *drv_data)
349 {
350 struct chip_data *chip = drv_data->cur_chip;
351
352 if (drv_data->ssp_type == CE4100_SSP)
353 return;
354
355 if (chip->cs_control) {
356 chip->cs_control(PXA2XX_CS_DEASSERT);
357 return;
358 }
359
360 if (gpio_is_valid(chip->gpio_cs)) {
361 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
362 return;
363 }
364
365 if (is_lpss_ssp(drv_data))
366 lpss_ssp_cs_control(drv_data, false);
367 }
368
369 int pxa2xx_spi_flush(struct driver_data *drv_data)
370 {
371 unsigned long limit = loops_per_jiffy << 1;
372
373 do {
374 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
375 pxa2xx_spi_read(drv_data, SSDR);
376 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
377 write_SSSR_CS(drv_data, SSSR_ROR);
378
379 return limit;
380 }
381
382 static int null_writer(struct driver_data *drv_data)
383 {
384 u8 n_bytes = drv_data->n_bytes;
385
386 if (pxa2xx_spi_txfifo_full(drv_data)
387 || (drv_data->tx == drv_data->tx_end))
388 return 0;
389
390 pxa2xx_spi_write(drv_data, SSDR, 0);
391 drv_data->tx += n_bytes;
392
393 return 1;
394 }
395
396 static int null_reader(struct driver_data *drv_data)
397 {
398 u8 n_bytes = drv_data->n_bytes;
399
400 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
401 && (drv_data->rx < drv_data->rx_end)) {
402 pxa2xx_spi_read(drv_data, SSDR);
403 drv_data->rx += n_bytes;
404 }
405
406 return drv_data->rx == drv_data->rx_end;
407 }
408
409 static int u8_writer(struct driver_data *drv_data)
410 {
411 if (pxa2xx_spi_txfifo_full(drv_data)
412 || (drv_data->tx == drv_data->tx_end))
413 return 0;
414
415 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
416 ++drv_data->tx;
417
418 return 1;
419 }
420
421 static int u8_reader(struct driver_data *drv_data)
422 {
423 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
424 && (drv_data->rx < drv_data->rx_end)) {
425 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
426 ++drv_data->rx;
427 }
428
429 return drv_data->rx == drv_data->rx_end;
430 }
431
432 static int u16_writer(struct driver_data *drv_data)
433 {
434 if (pxa2xx_spi_txfifo_full(drv_data)
435 || (drv_data->tx == drv_data->tx_end))
436 return 0;
437
438 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
439 drv_data->tx += 2;
440
441 return 1;
442 }
443
444 static int u16_reader(struct driver_data *drv_data)
445 {
446 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
447 && (drv_data->rx < drv_data->rx_end)) {
448 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
449 drv_data->rx += 2;
450 }
451
452 return drv_data->rx == drv_data->rx_end;
453 }
454
455 static int u32_writer(struct driver_data *drv_data)
456 {
457 if (pxa2xx_spi_txfifo_full(drv_data)
458 || (drv_data->tx == drv_data->tx_end))
459 return 0;
460
461 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
462 drv_data->tx += 4;
463
464 return 1;
465 }
466
467 static int u32_reader(struct driver_data *drv_data)
468 {
469 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
470 && (drv_data->rx < drv_data->rx_end)) {
471 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
472 drv_data->rx += 4;
473 }
474
475 return drv_data->rx == drv_data->rx_end;
476 }
477
478 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
479 {
480 struct spi_message *msg = drv_data->cur_msg;
481 struct spi_transfer *trans = drv_data->cur_transfer;
482
483 /* Move to next transfer */
484 if (trans->transfer_list.next != &msg->transfers) {
485 drv_data->cur_transfer =
486 list_entry(trans->transfer_list.next,
487 struct spi_transfer,
488 transfer_list);
489 return RUNNING_STATE;
490 } else
491 return DONE_STATE;
492 }
493
494 /* caller already set message->status; dma and pio irqs are blocked */
495 static void giveback(struct driver_data *drv_data)
496 {
497 struct spi_transfer* last_transfer;
498 struct spi_message *msg;
499
500 msg = drv_data->cur_msg;
501 drv_data->cur_msg = NULL;
502 drv_data->cur_transfer = NULL;
503
504 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
505 transfer_list);
506
507 /* Delay if requested before any change in chip select */
508 if (last_transfer->delay_usecs)
509 udelay(last_transfer->delay_usecs);
510
511 /* Drop chip select UNLESS cs_change is true or we are returning
512 * a message with an error, or next message is for another chip
513 */
514 if (!last_transfer->cs_change)
515 cs_deassert(drv_data);
516 else {
517 struct spi_message *next_msg;
518
519 /* Holding of cs was hinted, but we need to make sure
520 * the next message is for the same chip. Don't waste
521 * time with the following tests unless this was hinted.
522 *
523 * We cannot postpone this until pump_messages, because
524 * after calling msg->complete (below) the driver that
525 * sent the current message could be unloaded, which
526 * could invalidate the cs_control() callback...
527 */
528
529 /* get a pointer to the next message, if any */
530 next_msg = spi_get_next_queued_message(drv_data->master);
531
532 /* see if the next and current messages point
533 * to the same chip
534 */
535 if (next_msg && next_msg->spi != msg->spi)
536 next_msg = NULL;
537 if (!next_msg || msg->state == ERROR_STATE)
538 cs_deassert(drv_data);
539 }
540
541 drv_data->cur_chip = NULL;
542 spi_finalize_current_message(drv_data->master);
543 }
544
545 static void reset_sccr1(struct driver_data *drv_data)
546 {
547 struct chip_data *chip = drv_data->cur_chip;
548 u32 sccr1_reg;
549
550 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
551 sccr1_reg &= ~SSCR1_RFT;
552 sccr1_reg |= chip->threshold;
553 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
554 }
555
556 static void int_error_stop(struct driver_data *drv_data, const char* msg)
557 {
558 /* Stop and reset SSP */
559 write_SSSR_CS(drv_data, drv_data->clear_sr);
560 reset_sccr1(drv_data);
561 if (!pxa25x_ssp_comp(drv_data))
562 pxa2xx_spi_write(drv_data, SSTO, 0);
563 pxa2xx_spi_flush(drv_data);
564 pxa2xx_spi_write(drv_data, SSCR0,
565 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
566
567 dev_err(&drv_data->pdev->dev, "%s\n", msg);
568
569 drv_data->cur_msg->state = ERROR_STATE;
570 tasklet_schedule(&drv_data->pump_transfers);
571 }
572
573 static void int_transfer_complete(struct driver_data *drv_data)
574 {
575 /* Stop SSP */
576 write_SSSR_CS(drv_data, drv_data->clear_sr);
577 reset_sccr1(drv_data);
578 if (!pxa25x_ssp_comp(drv_data))
579 pxa2xx_spi_write(drv_data, SSTO, 0);
580
581 /* Update total byte transferred return count actual bytes read */
582 drv_data->cur_msg->actual_length += drv_data->len -
583 (drv_data->rx_end - drv_data->rx);
584
585 /* Transfer delays and chip select release are
586 * handled in pump_transfers or giveback
587 */
588
589 /* Move to next transfer */
590 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
591
592 /* Schedule transfer tasklet */
593 tasklet_schedule(&drv_data->pump_transfers);
594 }
595
596 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
597 {
598 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
599 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
600
601 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
602
603 if (irq_status & SSSR_ROR) {
604 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
605 return IRQ_HANDLED;
606 }
607
608 if (irq_status & SSSR_TINT) {
609 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
610 if (drv_data->read(drv_data)) {
611 int_transfer_complete(drv_data);
612 return IRQ_HANDLED;
613 }
614 }
615
616 /* Drain rx fifo, Fill tx fifo and prevent overruns */
617 do {
618 if (drv_data->read(drv_data)) {
619 int_transfer_complete(drv_data);
620 return IRQ_HANDLED;
621 }
622 } while (drv_data->write(drv_data));
623
624 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data);
626 return IRQ_HANDLED;
627 }
628
629 if (drv_data->tx == drv_data->tx_end) {
630 u32 bytes_left;
631 u32 sccr1_reg;
632
633 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
634 sccr1_reg &= ~SSCR1_TIE;
635
636 /*
637 * PXA25x_SSP has no timeout, set up rx threshould for the
638 * remaining RX bytes.
639 */
640 if (pxa25x_ssp_comp(drv_data)) {
641 u32 rx_thre;
642
643 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
644
645 bytes_left = drv_data->rx_end - drv_data->rx;
646 switch (drv_data->n_bytes) {
647 case 4:
648 bytes_left >>= 1;
649 case 2:
650 bytes_left >>= 1;
651 }
652
653 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
654 if (rx_thre > bytes_left)
655 rx_thre = bytes_left;
656
657 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
658 }
659 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
660 }
661
662 /* We did something */
663 return IRQ_HANDLED;
664 }
665
666 static irqreturn_t ssp_int(int irq, void *dev_id)
667 {
668 struct driver_data *drv_data = dev_id;
669 u32 sccr1_reg;
670 u32 mask = drv_data->mask_sr;
671 u32 status;
672
673 /*
674 * The IRQ might be shared with other peripherals so we must first
675 * check that are we RPM suspended or not. If we are we assume that
676 * the IRQ was not for us (we shouldn't be RPM suspended when the
677 * interrupt is enabled).
678 */
679 if (pm_runtime_suspended(&drv_data->pdev->dev))
680 return IRQ_NONE;
681
682 /*
683 * If the device is not yet in RPM suspended state and we get an
684 * interrupt that is meant for another device, check if status bits
685 * are all set to one. That means that the device is already
686 * powered off.
687 */
688 status = pxa2xx_spi_read(drv_data, SSSR);
689 if (status == ~0)
690 return IRQ_NONE;
691
692 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
693
694 /* Ignore possible writes if we don't need to write */
695 if (!(sccr1_reg & SSCR1_TIE))
696 mask &= ~SSSR_TFS;
697
698 /* Ignore RX timeout interrupt if it is disabled */
699 if (!(sccr1_reg & SSCR1_TINTE))
700 mask &= ~SSSR_TINT;
701
702 if (!(status & mask))
703 return IRQ_NONE;
704
705 if (!drv_data->cur_msg) {
706
707 pxa2xx_spi_write(drv_data, SSCR0,
708 pxa2xx_spi_read(drv_data, SSCR0)
709 & ~SSCR0_SSE);
710 pxa2xx_spi_write(drv_data, SSCR1,
711 pxa2xx_spi_read(drv_data, SSCR1)
712 & ~drv_data->int_cr1);
713 if (!pxa25x_ssp_comp(drv_data))
714 pxa2xx_spi_write(drv_data, SSTO, 0);
715 write_SSSR_CS(drv_data, drv_data->clear_sr);
716
717 dev_err(&drv_data->pdev->dev,
718 "bad message state in interrupt handler\n");
719
720 /* Never fail */
721 return IRQ_HANDLED;
722 }
723
724 return drv_data->transfer_handler(drv_data);
725 }
726
727 /*
728 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
729 * input frequency by fractions of 2^24. It also has a divider by 5.
730 *
731 * There are formulas to get baud rate value for given input frequency and
732 * divider parameters, such as DDS_CLK_RATE and SCR:
733 *
734 * Fsys = 200MHz
735 *
736 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
737 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
738 *
739 * DDS_CLK_RATE either 2^n or 2^n / 5.
740 * SCR is in range 0 .. 255
741 *
742 * Divisor = 5^i * 2^j * 2 * k
743 * i = [0, 1] i = 1 iff j = 0 or j > 3
744 * j = [0, 23] j = 0 iff i = 1
745 * k = [1, 256]
746 * Special case: j = 0, i = 1: Divisor = 2 / 5
747 *
748 * Accordingly to the specification the recommended values for DDS_CLK_RATE
749 * are:
750 * Case 1: 2^n, n = [0, 23]
751 * Case 2: 2^24 * 2 / 5 (0x666666)
752 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
753 *
754 * In all cases the lowest possible value is better.
755 *
756 * The function calculates parameters for all cases and chooses the one closest
757 * to the asked baud rate.
758 */
759 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
760 {
761 unsigned long xtal = 200000000;
762 unsigned long fref = xtal / 2; /* mandatory division by 2,
763 see (2) */
764 /* case 3 */
765 unsigned long fref1 = fref / 2; /* case 1 */
766 unsigned long fref2 = fref * 2 / 5; /* case 2 */
767 unsigned long scale;
768 unsigned long q, q1, q2;
769 long r, r1, r2;
770 u32 mul;
771
772 /* Case 1 */
773
774 /* Set initial value for DDS_CLK_RATE */
775 mul = (1 << 24) >> 1;
776
777 /* Calculate initial quot */
778 q1 = DIV_ROUND_UP(fref1, rate);
779
780 /* Scale q1 if it's too big */
781 if (q1 > 256) {
782 /* Scale q1 to range [1, 512] */
783 scale = fls_long(q1 - 1);
784 if (scale > 9) {
785 q1 >>= scale - 9;
786 mul >>= scale - 9;
787 }
788
789 /* Round the result if we have a remainder */
790 q1 += q1 & 1;
791 }
792
793 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
794 scale = __ffs(q1);
795 q1 >>= scale;
796 mul >>= scale;
797
798 /* Get the remainder */
799 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
800
801 /* Case 2 */
802
803 q2 = DIV_ROUND_UP(fref2, rate);
804 r2 = abs(fref2 / q2 - rate);
805
806 /*
807 * Choose the best between two: less remainder we have the better. We
808 * can't go case 2 if q2 is greater than 256 since SCR register can
809 * hold only values 0 .. 255.
810 */
811 if (r2 >= r1 || q2 > 256) {
812 /* case 1 is better */
813 r = r1;
814 q = q1;
815 } else {
816 /* case 2 is better */
817 r = r2;
818 q = q2;
819 mul = (1 << 24) * 2 / 5;
820 }
821
822 /* Check case 3 only if the divisor is big enough */
823 if (fref / rate >= 80) {
824 u64 fssp;
825 u32 m;
826
827 /* Calculate initial quot */
828 q1 = DIV_ROUND_UP(fref, rate);
829 m = (1 << 24) / q1;
830
831 /* Get the remainder */
832 fssp = (u64)fref * m;
833 do_div(fssp, 1 << 24);
834 r1 = abs(fssp - rate);
835
836 /* Choose this one if it suits better */
837 if (r1 < r) {
838 /* case 3 is better */
839 q = 1;
840 mul = m;
841 }
842 }
843
844 *dds = mul;
845 return q - 1;
846 }
847
848 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
849 {
850 unsigned long ssp_clk = drv_data->master->max_speed_hz;
851 const struct ssp_device *ssp = drv_data->ssp;
852
853 rate = min_t(int, ssp_clk, rate);
854
855 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
856 return (ssp_clk / (2 * rate) - 1) & 0xff;
857 else
858 return (ssp_clk / rate - 1) & 0xfff;
859 }
860
861 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
862 int rate)
863 {
864 struct chip_data *chip = drv_data->cur_chip;
865 unsigned int clk_div;
866
867 switch (drv_data->ssp_type) {
868 case QUARK_X1000_SSP:
869 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
870 break;
871 default:
872 clk_div = ssp_get_clk_div(drv_data, rate);
873 break;
874 }
875 return clk_div << 8;
876 }
877
878 static void pump_transfers(unsigned long data)
879 {
880 struct driver_data *drv_data = (struct driver_data *)data;
881 struct spi_message *message = NULL;
882 struct spi_transfer *transfer = NULL;
883 struct spi_transfer *previous = NULL;
884 struct chip_data *chip = NULL;
885 u32 clk_div = 0;
886 u8 bits = 0;
887 u32 speed = 0;
888 u32 cr0;
889 u32 cr1;
890 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
891 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
892 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
893
894 /* Get current state information */
895 message = drv_data->cur_msg;
896 transfer = drv_data->cur_transfer;
897 chip = drv_data->cur_chip;
898
899 /* Handle for abort */
900 if (message->state == ERROR_STATE) {
901 message->status = -EIO;
902 giveback(drv_data);
903 return;
904 }
905
906 /* Handle end of message */
907 if (message->state == DONE_STATE) {
908 message->status = 0;
909 giveback(drv_data);
910 return;
911 }
912
913 /* Delay if requested at end of transfer before CS change */
914 if (message->state == RUNNING_STATE) {
915 previous = list_entry(transfer->transfer_list.prev,
916 struct spi_transfer,
917 transfer_list);
918 if (previous->delay_usecs)
919 udelay(previous->delay_usecs);
920
921 /* Drop chip select only if cs_change is requested */
922 if (previous->cs_change)
923 cs_deassert(drv_data);
924 }
925
926 /* Check if we can DMA this transfer */
927 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
928
929 /* reject already-mapped transfers; PIO won't always work */
930 if (message->is_dma_mapped
931 || transfer->rx_dma || transfer->tx_dma) {
932 dev_err(&drv_data->pdev->dev,
933 "pump_transfers: mapped transfer length of "
934 "%u is greater than %d\n",
935 transfer->len, MAX_DMA_LEN);
936 message->status = -EINVAL;
937 giveback(drv_data);
938 return;
939 }
940
941 /* warn ... we force this to PIO mode */
942 dev_warn_ratelimited(&message->spi->dev,
943 "pump_transfers: DMA disabled for transfer length %ld "
944 "greater than %d\n",
945 (long)drv_data->len, MAX_DMA_LEN);
946 }
947
948 /* Setup the transfer state based on the type of transfer */
949 if (pxa2xx_spi_flush(drv_data) == 0) {
950 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
951 message->status = -EIO;
952 giveback(drv_data);
953 return;
954 }
955 drv_data->n_bytes = chip->n_bytes;
956 drv_data->tx = (void *)transfer->tx_buf;
957 drv_data->tx_end = drv_data->tx + transfer->len;
958 drv_data->rx = transfer->rx_buf;
959 drv_data->rx_end = drv_data->rx + transfer->len;
960 drv_data->rx_dma = transfer->rx_dma;
961 drv_data->tx_dma = transfer->tx_dma;
962 drv_data->len = transfer->len;
963 drv_data->write = drv_data->tx ? chip->write : null_writer;
964 drv_data->read = drv_data->rx ? chip->read : null_reader;
965
966 /* Change speed and bit per word on a per transfer */
967 bits = transfer->bits_per_word;
968 speed = transfer->speed_hz;
969
970 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
971
972 if (bits <= 8) {
973 drv_data->n_bytes = 1;
974 drv_data->read = drv_data->read != null_reader ?
975 u8_reader : null_reader;
976 drv_data->write = drv_data->write != null_writer ?
977 u8_writer : null_writer;
978 } else if (bits <= 16) {
979 drv_data->n_bytes = 2;
980 drv_data->read = drv_data->read != null_reader ?
981 u16_reader : null_reader;
982 drv_data->write = drv_data->write != null_writer ?
983 u16_writer : null_writer;
984 } else if (bits <= 32) {
985 drv_data->n_bytes = 4;
986 drv_data->read = drv_data->read != null_reader ?
987 u32_reader : null_reader;
988 drv_data->write = drv_data->write != null_writer ?
989 u32_writer : null_writer;
990 }
991 /*
992 * if bits/word is changed in dma mode, then must check the
993 * thresholds and burst also
994 */
995 if (chip->enable_dma) {
996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
997 message->spi,
998 bits, &dma_burst,
999 &dma_thresh))
1000 dev_warn_ratelimited(&message->spi->dev,
1001 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1002 }
1003
1004 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1005 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1006 if (!pxa25x_ssp_comp(drv_data))
1007 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1008 drv_data->master->max_speed_hz
1009 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1010 chip->enable_dma ? "DMA" : "PIO");
1011 else
1012 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1013 drv_data->master->max_speed_hz / 2
1014 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1015 chip->enable_dma ? "DMA" : "PIO");
1016
1017 message->state = RUNNING_STATE;
1018
1019 drv_data->dma_mapped = 0;
1020 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1021 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1022 if (drv_data->dma_mapped) {
1023
1024 /* Ensure we have the correct interrupt handler */
1025 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1026
1027 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1028
1029 /* Clear status and start DMA engine */
1030 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1031 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1032
1033 pxa2xx_spi_dma_start(drv_data);
1034 } else {
1035 /* Ensure we have the correct interrupt handler */
1036 drv_data->transfer_handler = interrupt_transfer;
1037
1038 /* Clear status */
1039 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1040 write_SSSR_CS(drv_data, drv_data->clear_sr);
1041 }
1042
1043 if (is_lpss_ssp(drv_data)) {
1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045 != chip->lpss_rx_threshold)
1046 pxa2xx_spi_write(drv_data, SSIRF,
1047 chip->lpss_rx_threshold);
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049 != chip->lpss_tx_threshold)
1050 pxa2xx_spi_write(drv_data, SSITF,
1051 chip->lpss_tx_threshold);
1052 }
1053
1054 if (is_quark_x1000_ssp(drv_data) &&
1055 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1056 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1057
1058 /* see if we need to reload the config registers */
1059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1060 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1061 != (cr1 & change_mask)) {
1062 /* stop the SSP, and update the other bits */
1063 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1064 if (!pxa25x_ssp_comp(drv_data))
1065 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1066 /* first set CR1 without interrupt and service enables */
1067 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1068 /* restart the SSP */
1069 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1070
1071 } else {
1072 if (!pxa25x_ssp_comp(drv_data))
1073 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1074 }
1075
1076 cs_assert(drv_data);
1077
1078 /* after chip select, release the data by enabling service
1079 * requests and interrupts, without changing any mode bits */
1080 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1081 }
1082
1083 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1084 struct spi_message *msg)
1085 {
1086 struct driver_data *drv_data = spi_master_get_devdata(master);
1087
1088 drv_data->cur_msg = msg;
1089 /* Initial message state*/
1090 drv_data->cur_msg->state = START_STATE;
1091 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1092 struct spi_transfer,
1093 transfer_list);
1094
1095 /* prepare to setup the SSP, in pump_transfers, using the per
1096 * chip configuration */
1097 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1098
1099 /* Mark as busy and launch transfers */
1100 tasklet_schedule(&drv_data->pump_transfers);
1101 return 0;
1102 }
1103
1104 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1105 {
1106 struct driver_data *drv_data = spi_master_get_devdata(master);
1107
1108 /* Disable the SSP now */
1109 pxa2xx_spi_write(drv_data, SSCR0,
1110 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1111
1112 return 0;
1113 }
1114
1115 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1116 struct pxa2xx_spi_chip *chip_info)
1117 {
1118 int err = 0;
1119
1120 if (chip == NULL || chip_info == NULL)
1121 return 0;
1122
1123 /* NOTE: setup() can be called multiple times, possibly with
1124 * different chip_info, release previously requested GPIO
1125 */
1126 if (gpio_is_valid(chip->gpio_cs))
1127 gpio_free(chip->gpio_cs);
1128
1129 /* If (*cs_control) is provided, ignore GPIO chip select */
1130 if (chip_info->cs_control) {
1131 chip->cs_control = chip_info->cs_control;
1132 return 0;
1133 }
1134
1135 if (gpio_is_valid(chip_info->gpio_cs)) {
1136 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1137 if (err) {
1138 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1139 chip_info->gpio_cs);
1140 return err;
1141 }
1142
1143 chip->gpio_cs = chip_info->gpio_cs;
1144 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1145
1146 err = gpio_direction_output(chip->gpio_cs,
1147 !chip->gpio_cs_inverted);
1148 }
1149
1150 return err;
1151 }
1152
1153 static int setup(struct spi_device *spi)
1154 {
1155 struct pxa2xx_spi_chip *chip_info = NULL;
1156 struct chip_data *chip;
1157 const struct lpss_config *config;
1158 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1159 uint tx_thres, tx_hi_thres, rx_thres;
1160
1161 switch (drv_data->ssp_type) {
1162 case QUARK_X1000_SSP:
1163 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1164 tx_hi_thres = 0;
1165 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1166 break;
1167 case LPSS_LPT_SSP:
1168 case LPSS_BYT_SSP:
1169 case LPSS_SPT_SSP:
1170 case LPSS_BXT_SSP:
1171 config = lpss_get_config(drv_data);
1172 tx_thres = config->tx_threshold_lo;
1173 tx_hi_thres = config->tx_threshold_hi;
1174 rx_thres = config->rx_threshold;
1175 break;
1176 default:
1177 tx_thres = TX_THRESH_DFLT;
1178 tx_hi_thres = 0;
1179 rx_thres = RX_THRESH_DFLT;
1180 break;
1181 }
1182
1183 /* Only alloc on first setup */
1184 chip = spi_get_ctldata(spi);
1185 if (!chip) {
1186 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1187 if (!chip)
1188 return -ENOMEM;
1189
1190 if (drv_data->ssp_type == CE4100_SSP) {
1191 if (spi->chip_select > 4) {
1192 dev_err(&spi->dev,
1193 "failed setup: cs number must not be > 4.\n");
1194 kfree(chip);
1195 return -EINVAL;
1196 }
1197
1198 chip->frm = spi->chip_select;
1199 } else
1200 chip->gpio_cs = -1;
1201 chip->enable_dma = 0;
1202 chip->timeout = TIMOUT_DFLT;
1203 }
1204
1205 /* protocol drivers may change the chip settings, so...
1206 * if chip_info exists, use it */
1207 chip_info = spi->controller_data;
1208
1209 /* chip_info isn't always needed */
1210 chip->cr1 = 0;
1211 if (chip_info) {
1212 if (chip_info->timeout)
1213 chip->timeout = chip_info->timeout;
1214 if (chip_info->tx_threshold)
1215 tx_thres = chip_info->tx_threshold;
1216 if (chip_info->tx_hi_threshold)
1217 tx_hi_thres = chip_info->tx_hi_threshold;
1218 if (chip_info->rx_threshold)
1219 rx_thres = chip_info->rx_threshold;
1220 chip->enable_dma = drv_data->master_info->enable_dma;
1221 chip->dma_threshold = 0;
1222 if (chip_info->enable_loopback)
1223 chip->cr1 = SSCR1_LBM;
1224 } else if (ACPI_HANDLE(&spi->dev)) {
1225 /*
1226 * Slave devices enumerated from ACPI namespace don't
1227 * usually have chip_info but we still might want to use
1228 * DMA with them.
1229 */
1230 chip->enable_dma = drv_data->master_info->enable_dma;
1231 }
1232
1233 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1234 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1235 | SSITF_TxHiThresh(tx_hi_thres);
1236
1237 /* set dma burst and threshold outside of chip_info path so that if
1238 * chip_info goes away after setting chip->enable_dma, the
1239 * burst and threshold can still respond to changes in bits_per_word */
1240 if (chip->enable_dma) {
1241 /* set up legal burst and threshold for dma */
1242 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1243 spi->bits_per_word,
1244 &chip->dma_burst_size,
1245 &chip->dma_threshold)) {
1246 dev_warn(&spi->dev,
1247 "in setup: DMA burst size reduced to match bits_per_word\n");
1248 }
1249 }
1250
1251 switch (drv_data->ssp_type) {
1252 case QUARK_X1000_SSP:
1253 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1254 & QUARK_X1000_SSCR1_RFT)
1255 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1256 & QUARK_X1000_SSCR1_TFT);
1257 break;
1258 default:
1259 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1260 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1261 break;
1262 }
1263
1264 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1265 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1266 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1267
1268 if (spi->mode & SPI_LOOP)
1269 chip->cr1 |= SSCR1_LBM;
1270
1271 if (spi->bits_per_word <= 8) {
1272 chip->n_bytes = 1;
1273 chip->read = u8_reader;
1274 chip->write = u8_writer;
1275 } else if (spi->bits_per_word <= 16) {
1276 chip->n_bytes = 2;
1277 chip->read = u16_reader;
1278 chip->write = u16_writer;
1279 } else if (spi->bits_per_word <= 32) {
1280 chip->n_bytes = 4;
1281 chip->read = u32_reader;
1282 chip->write = u32_writer;
1283 }
1284
1285 spi_set_ctldata(spi, chip);
1286
1287 if (drv_data->ssp_type == CE4100_SSP)
1288 return 0;
1289
1290 return setup_cs(spi, chip, chip_info);
1291 }
1292
1293 static void cleanup(struct spi_device *spi)
1294 {
1295 struct chip_data *chip = spi_get_ctldata(spi);
1296 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1297
1298 if (!chip)
1299 return;
1300
1301 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1302 gpio_free(chip->gpio_cs);
1303
1304 kfree(chip);
1305 }
1306
1307 #ifdef CONFIG_PCI
1308 #ifdef CONFIG_ACPI
1309
1310 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1311 { "INT33C0", LPSS_LPT_SSP },
1312 { "INT33C1", LPSS_LPT_SSP },
1313 { "INT3430", LPSS_LPT_SSP },
1314 { "INT3431", LPSS_LPT_SSP },
1315 { "80860F0E", LPSS_BYT_SSP },
1316 { "8086228E", LPSS_BYT_SSP },
1317 { },
1318 };
1319 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1320
1321 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1322 {
1323 unsigned int devid;
1324 int port_id = -1;
1325
1326 if (adev && adev->pnp.unique_id &&
1327 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1328 port_id = devid;
1329 return port_id;
1330 }
1331 #else /* !CONFIG_ACPI */
1332 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1333 {
1334 return -1;
1335 }
1336 #endif
1337
1338 /*
1339 * PCI IDs of compound devices that integrate both host controller and private
1340 * integrated DMA engine. Please note these are not used in module
1341 * autoloading and probing in this module but matching the LPSS SSP type.
1342 */
1343 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1344 /* SPT-LP */
1345 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1346 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1347 /* SPT-H */
1348 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1349 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1350 /* BXT */
1351 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1352 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1353 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1354 /* APL */
1355 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1356 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1357 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1358 { },
1359 };
1360
1361 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1362 {
1363 struct device *dev = param;
1364
1365 if (dev != chan->device->dev->parent)
1366 return false;
1367
1368 return true;
1369 }
1370
1371 static struct pxa2xx_spi_master *
1372 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1373 {
1374 struct pxa2xx_spi_master *pdata;
1375 struct acpi_device *adev;
1376 struct ssp_device *ssp;
1377 struct resource *res;
1378 const struct acpi_device_id *adev_id = NULL;
1379 const struct pci_device_id *pcidev_id = NULL;
1380 int type;
1381
1382 adev = ACPI_COMPANION(&pdev->dev);
1383
1384 if (dev_is_pci(pdev->dev.parent))
1385 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1386 to_pci_dev(pdev->dev.parent));
1387 else if (adev)
1388 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1389 &pdev->dev);
1390 else
1391 return NULL;
1392
1393 if (adev_id)
1394 type = (int)adev_id->driver_data;
1395 else if (pcidev_id)
1396 type = (int)pcidev_id->driver_data;
1397 else
1398 return NULL;
1399
1400 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1401 if (!pdata)
1402 return NULL;
1403
1404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405 if (!res)
1406 return NULL;
1407
1408 ssp = &pdata->ssp;
1409
1410 ssp->phys_base = res->start;
1411 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1412 if (IS_ERR(ssp->mmio_base))
1413 return NULL;
1414
1415 if (pcidev_id) {
1416 pdata->tx_param = pdev->dev.parent;
1417 pdata->rx_param = pdev->dev.parent;
1418 pdata->dma_filter = pxa2xx_spi_idma_filter;
1419 }
1420
1421 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1422 ssp->irq = platform_get_irq(pdev, 0);
1423 ssp->type = type;
1424 ssp->pdev = pdev;
1425 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1426
1427 pdata->num_chipselect = 1;
1428 pdata->enable_dma = true;
1429
1430 return pdata;
1431 }
1432
1433 #else /* !CONFIG_PCI */
1434 static inline struct pxa2xx_spi_master *
1435 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1436 {
1437 return NULL;
1438 }
1439 #endif
1440
1441 static int pxa2xx_spi_probe(struct platform_device *pdev)
1442 {
1443 struct device *dev = &pdev->dev;
1444 struct pxa2xx_spi_master *platform_info;
1445 struct spi_master *master;
1446 struct driver_data *drv_data;
1447 struct ssp_device *ssp;
1448 const struct lpss_config *config;
1449 int status;
1450 u32 tmp;
1451
1452 platform_info = dev_get_platdata(dev);
1453 if (!platform_info) {
1454 platform_info = pxa2xx_spi_init_pdata(pdev);
1455 if (!platform_info) {
1456 dev_err(&pdev->dev, "missing platform data\n");
1457 return -ENODEV;
1458 }
1459 }
1460
1461 ssp = pxa_ssp_request(pdev->id, pdev->name);
1462 if (!ssp)
1463 ssp = &platform_info->ssp;
1464
1465 if (!ssp->mmio_base) {
1466 dev_err(&pdev->dev, "failed to get ssp\n");
1467 return -ENODEV;
1468 }
1469
1470 master = spi_alloc_master(dev, sizeof(struct driver_data));
1471 if (!master) {
1472 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1473 pxa_ssp_free(ssp);
1474 return -ENOMEM;
1475 }
1476 drv_data = spi_master_get_devdata(master);
1477 drv_data->master = master;
1478 drv_data->master_info = platform_info;
1479 drv_data->pdev = pdev;
1480 drv_data->ssp = ssp;
1481
1482 master->dev.parent = &pdev->dev;
1483 master->dev.of_node = pdev->dev.of_node;
1484 /* the spi->mode bits understood by this driver: */
1485 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1486
1487 master->bus_num = ssp->port_id;
1488 master->dma_alignment = DMA_ALIGNMENT;
1489 master->cleanup = cleanup;
1490 master->setup = setup;
1491 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1492 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1493 master->auto_runtime_pm = true;
1494
1495 drv_data->ssp_type = ssp->type;
1496
1497 drv_data->ioaddr = ssp->mmio_base;
1498 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1499 if (pxa25x_ssp_comp(drv_data)) {
1500 switch (drv_data->ssp_type) {
1501 case QUARK_X1000_SSP:
1502 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1503 break;
1504 default:
1505 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1506 break;
1507 }
1508
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 } else {
1514 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1519 }
1520
1521 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1522 drv_data);
1523 if (status < 0) {
1524 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1525 goto out_error_master_alloc;
1526 }
1527
1528 /* Setup DMA if requested */
1529 if (platform_info->enable_dma) {
1530 status = pxa2xx_spi_dma_setup(drv_data);
1531 if (status) {
1532 dev_dbg(dev, "no DMA channels available, using PIO\n");
1533 platform_info->enable_dma = false;
1534 }
1535 }
1536
1537 /* Enable SOC clock */
1538 clk_prepare_enable(ssp->clk);
1539
1540 master->max_speed_hz = clk_get_rate(ssp->clk);
1541
1542 /* Load default SSP configuration */
1543 pxa2xx_spi_write(drv_data, SSCR0, 0);
1544 switch (drv_data->ssp_type) {
1545 case QUARK_X1000_SSP:
1546 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1547 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1548 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1549
1550 /* using the Motorola SPI protocol and use 8 bit frame */
1551 pxa2xx_spi_write(drv_data, SSCR0,
1552 QUARK_X1000_SSCR0_Motorola
1553 | QUARK_X1000_SSCR0_DataSize(8));
1554 break;
1555 default:
1556 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1557 SSCR1_TxTresh(TX_THRESH_DFLT);
1558 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1559 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1560 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1561 break;
1562 }
1563
1564 if (!pxa25x_ssp_comp(drv_data))
1565 pxa2xx_spi_write(drv_data, SSTO, 0);
1566
1567 if (!is_quark_x1000_ssp(drv_data))
1568 pxa2xx_spi_write(drv_data, SSPSP, 0);
1569
1570 if (is_lpss_ssp(drv_data)) {
1571 lpss_ssp_setup(drv_data);
1572 config = lpss_get_config(drv_data);
1573 if (config->reg_capabilities >= 0) {
1574 tmp = __lpss_ssp_read_priv(drv_data,
1575 config->reg_capabilities);
1576 tmp &= LPSS_CAPS_CS_EN_MASK;
1577 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1578 platform_info->num_chipselect = ffz(tmp);
1579 }
1580 }
1581 master->num_chipselect = platform_info->num_chipselect;
1582
1583 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1584 (unsigned long)drv_data);
1585
1586 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1587 pm_runtime_use_autosuspend(&pdev->dev);
1588 pm_runtime_set_active(&pdev->dev);
1589 pm_runtime_enable(&pdev->dev);
1590
1591 /* Register with the SPI framework */
1592 platform_set_drvdata(pdev, drv_data);
1593 status = devm_spi_register_master(&pdev->dev, master);
1594 if (status != 0) {
1595 dev_err(&pdev->dev, "problem registering spi master\n");
1596 goto out_error_clock_enabled;
1597 }
1598
1599 return status;
1600
1601 out_error_clock_enabled:
1602 clk_disable_unprepare(ssp->clk);
1603 pxa2xx_spi_dma_release(drv_data);
1604 free_irq(ssp->irq, drv_data);
1605
1606 out_error_master_alloc:
1607 spi_master_put(master);
1608 pxa_ssp_free(ssp);
1609 return status;
1610 }
1611
1612 static int pxa2xx_spi_remove(struct platform_device *pdev)
1613 {
1614 struct driver_data *drv_data = platform_get_drvdata(pdev);
1615 struct ssp_device *ssp;
1616
1617 if (!drv_data)
1618 return 0;
1619 ssp = drv_data->ssp;
1620
1621 pm_runtime_get_sync(&pdev->dev);
1622
1623 /* Disable the SSP at the peripheral and SOC level */
1624 pxa2xx_spi_write(drv_data, SSCR0, 0);
1625 clk_disable_unprepare(ssp->clk);
1626
1627 /* Release DMA */
1628 if (drv_data->master_info->enable_dma)
1629 pxa2xx_spi_dma_release(drv_data);
1630
1631 pm_runtime_put_noidle(&pdev->dev);
1632 pm_runtime_disable(&pdev->dev);
1633
1634 /* Release IRQ */
1635 free_irq(ssp->irq, drv_data);
1636
1637 /* Release SSP */
1638 pxa_ssp_free(ssp);
1639
1640 return 0;
1641 }
1642
1643 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1644 {
1645 int status = 0;
1646
1647 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1648 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1649 }
1650
1651 #ifdef CONFIG_PM_SLEEP
1652 static int pxa2xx_spi_suspend(struct device *dev)
1653 {
1654 struct driver_data *drv_data = dev_get_drvdata(dev);
1655 struct ssp_device *ssp = drv_data->ssp;
1656 int status = 0;
1657
1658 status = spi_master_suspend(drv_data->master);
1659 if (status != 0)
1660 return status;
1661 pxa2xx_spi_write(drv_data, SSCR0, 0);
1662
1663 if (!pm_runtime_suspended(dev))
1664 clk_disable_unprepare(ssp->clk);
1665
1666 return 0;
1667 }
1668
1669 static int pxa2xx_spi_resume(struct device *dev)
1670 {
1671 struct driver_data *drv_data = dev_get_drvdata(dev);
1672 struct ssp_device *ssp = drv_data->ssp;
1673 int status = 0;
1674
1675 /* Enable the SSP clock */
1676 if (!pm_runtime_suspended(dev))
1677 clk_prepare_enable(ssp->clk);
1678
1679 /* Restore LPSS private register bits */
1680 if (is_lpss_ssp(drv_data))
1681 lpss_ssp_setup(drv_data);
1682
1683 /* Start the queue running */
1684 status = spi_master_resume(drv_data->master);
1685 if (status != 0) {
1686 dev_err(dev, "problem starting queue (%d)\n", status);
1687 return status;
1688 }
1689
1690 return 0;
1691 }
1692 #endif
1693
1694 #ifdef CONFIG_PM
1695 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1696 {
1697 struct driver_data *drv_data = dev_get_drvdata(dev);
1698
1699 clk_disable_unprepare(drv_data->ssp->clk);
1700 return 0;
1701 }
1702
1703 static int pxa2xx_spi_runtime_resume(struct device *dev)
1704 {
1705 struct driver_data *drv_data = dev_get_drvdata(dev);
1706
1707 clk_prepare_enable(drv_data->ssp->clk);
1708 return 0;
1709 }
1710 #endif
1711
1712 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1713 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1714 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1715 pxa2xx_spi_runtime_resume, NULL)
1716 };
1717
1718 static struct platform_driver driver = {
1719 .driver = {
1720 .name = "pxa2xx-spi",
1721 .pm = &pxa2xx_spi_pm_ops,
1722 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1723 },
1724 .probe = pxa2xx_spi_probe,
1725 .remove = pxa2xx_spi_remove,
1726 .shutdown = pxa2xx_spi_shutdown,
1727 };
1728
1729 static int __init pxa2xx_spi_init(void)
1730 {
1731 return platform_driver_register(&driver);
1732 }
1733 subsys_initcall(pxa2xx_spi_init);
1734
1735 static void __exit pxa2xx_spi_exit(void)
1736 {
1737 platform_driver_unregister(&driver);
1738 }
1739 module_exit(pxa2xx_spi_exit);
Linux with added FPC-III support