LiteX: driver for MMCM
[linux/fpc-iii.git] / drivers / bcma / host_pci.c
blob69c10a7b7c617b0155637c42e53821693445b826
1 /*
2 * Broadcom specific AMBA
3 * PCI Host
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
8 #include "bcma_private.h"
9 #include <linux/slab.h>
10 #include <linux/bcma/bcma.h>
11 #include <linux/pci.h>
12 #include <linux/module.h>
14 static void bcma_host_pci_switch_core(struct bcma_device *core)
16 int win2 = core->bus->host_is_pcie2 ?
17 BCMA_PCIE2_BAR0_WIN2 : BCMA_PCI_BAR0_WIN2;
19 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
20 core->addr);
21 pci_write_config_dword(core->bus->host_pci, win2, core->wrap);
22 core->bus->mapped_core = core;
23 bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
26 /* Provides access to the requested core. Returns base offset that has to be
27 * used. It makes use of fixed windows when possible. */
28 static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
30 switch (core->id.id) {
31 case BCMA_CORE_CHIPCOMMON:
32 return 3 * BCMA_CORE_SIZE;
33 case BCMA_CORE_PCIE:
34 return 2 * BCMA_CORE_SIZE;
37 if (core->bus->mapped_core != core)
38 bcma_host_pci_switch_core(core);
39 return 0;
42 static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
44 offset += bcma_host_pci_provide_access_to_core(core);
45 return ioread8(core->bus->mmio + offset);
48 static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
50 offset += bcma_host_pci_provide_access_to_core(core);
51 return ioread16(core->bus->mmio + offset);
54 static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
56 offset += bcma_host_pci_provide_access_to_core(core);
57 return ioread32(core->bus->mmio + offset);
60 static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
61 u8 value)
63 offset += bcma_host_pci_provide_access_to_core(core);
64 iowrite8(value, core->bus->mmio + offset);
67 static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
68 u16 value)
70 offset += bcma_host_pci_provide_access_to_core(core);
71 iowrite16(value, core->bus->mmio + offset);
74 static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
75 u32 value)
77 offset += bcma_host_pci_provide_access_to_core(core);
78 iowrite32(value, core->bus->mmio + offset);
81 #ifdef CONFIG_BCMA_BLOCKIO
82 static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
83 size_t count, u16 offset, u8 reg_width)
85 void __iomem *addr = core->bus->mmio + offset;
86 if (core->bus->mapped_core != core)
87 bcma_host_pci_switch_core(core);
88 switch (reg_width) {
89 case sizeof(u8):
90 ioread8_rep(addr, buffer, count);
91 break;
92 case sizeof(u16):
93 WARN_ON(count & 1);
94 ioread16_rep(addr, buffer, count >> 1);
95 break;
96 case sizeof(u32):
97 WARN_ON(count & 3);
98 ioread32_rep(addr, buffer, count >> 2);
99 break;
100 default:
101 WARN_ON(1);
105 static void bcma_host_pci_block_write(struct bcma_device *core,
106 const void *buffer, size_t count,
107 u16 offset, u8 reg_width)
109 void __iomem *addr = core->bus->mmio + offset;
110 if (core->bus->mapped_core != core)
111 bcma_host_pci_switch_core(core);
112 switch (reg_width) {
113 case sizeof(u8):
114 iowrite8_rep(addr, buffer, count);
115 break;
116 case sizeof(u16):
117 WARN_ON(count & 1);
118 iowrite16_rep(addr, buffer, count >> 1);
119 break;
120 case sizeof(u32):
121 WARN_ON(count & 3);
122 iowrite32_rep(addr, buffer, count >> 2);
123 break;
124 default:
125 WARN_ON(1);
128 #endif
130 static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
132 if (core->bus->mapped_core != core)
133 bcma_host_pci_switch_core(core);
134 return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
137 static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
138 u32 value)
140 if (core->bus->mapped_core != core)
141 bcma_host_pci_switch_core(core);
142 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
145 static const struct bcma_host_ops bcma_host_pci_ops = {
146 .read8 = bcma_host_pci_read8,
147 .read16 = bcma_host_pci_read16,
148 .read32 = bcma_host_pci_read32,
149 .write8 = bcma_host_pci_write8,
150 .write16 = bcma_host_pci_write16,
151 .write32 = bcma_host_pci_write32,
152 #ifdef CONFIG_BCMA_BLOCKIO
153 .block_read = bcma_host_pci_block_read,
154 .block_write = bcma_host_pci_block_write,
155 #endif
156 .aread32 = bcma_host_pci_aread32,
157 .awrite32 = bcma_host_pci_awrite32,
160 static int bcma_host_pci_probe(struct pci_dev *dev,
161 const struct pci_device_id *id)
163 struct bcma_bus *bus;
164 int err = -ENOMEM;
165 const char *name;
166 u32 val;
168 /* Alloc */
169 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
170 if (!bus)
171 goto out;
173 /* Basic PCI configuration */
174 err = pci_enable_device(dev);
175 if (err)
176 goto err_kfree_bus;
178 name = dev_name(&dev->dev);
179 if (dev->driver && dev->driver->name)
180 name = dev->driver->name;
181 err = pci_request_regions(dev, name);
182 if (err)
183 goto err_pci_disable;
184 pci_set_master(dev);
186 /* Disable the RETRY_TIMEOUT register (0x41) to keep
187 * PCI Tx retries from interfering with C3 CPU state */
188 pci_read_config_dword(dev, 0x40, &val);
189 if ((val & 0x0000ff00) != 0)
190 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
192 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
193 if (!pci_is_pcie(dev)) {
194 bcma_err(bus, "PCI card detected, they are not supported.\n");
195 err = -ENXIO;
196 goto err_pci_release_regions;
199 bus->dev = &dev->dev;
201 /* Map MMIO */
202 err = -ENOMEM;
203 bus->mmio = pci_iomap(dev, 0, ~0UL);
204 if (!bus->mmio)
205 goto err_pci_release_regions;
207 /* Host specific */
208 bus->host_pci = dev;
209 bus->hosttype = BCMA_HOSTTYPE_PCI;
210 bus->ops = &bcma_host_pci_ops;
212 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
213 bus->boardinfo.type = bus->host_pci->subsystem_device;
215 /* Initialize struct, detect chip */
216 bcma_init_bus(bus);
218 /* Scan bus to find out generation of PCIe core */
219 err = bcma_bus_scan(bus);
220 if (err)
221 goto err_pci_unmap_mmio;
223 if (bcma_find_core(bus, BCMA_CORE_PCIE2))
224 bus->host_is_pcie2 = true;
226 /* Register */
227 err = bcma_bus_register(bus);
228 if (err)
229 goto err_unregister_cores;
231 pci_set_drvdata(dev, bus);
233 out:
234 return err;
236 err_unregister_cores:
237 bcma_unregister_cores(bus);
238 err_pci_unmap_mmio:
239 pci_iounmap(dev, bus->mmio);
240 err_pci_release_regions:
241 pci_release_regions(dev);
242 err_pci_disable:
243 pci_disable_device(dev);
244 err_kfree_bus:
245 kfree(bus);
246 return err;
249 static void bcma_host_pci_remove(struct pci_dev *dev)
251 struct bcma_bus *bus = pci_get_drvdata(dev);
253 bcma_bus_unregister(bus);
254 pci_iounmap(dev, bus->mmio);
255 pci_release_regions(dev);
256 pci_disable_device(dev);
257 kfree(bus);
260 #ifdef CONFIG_PM_SLEEP
261 static int bcma_host_pci_suspend(struct device *dev)
263 struct bcma_bus *bus = dev_get_drvdata(dev);
265 bus->mapped_core = NULL;
267 return bcma_bus_suspend(bus);
270 static int bcma_host_pci_resume(struct device *dev)
272 struct bcma_bus *bus = dev_get_drvdata(dev);
274 return bcma_bus_resume(bus);
277 static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
278 bcma_host_pci_resume);
279 #define BCMA_PM_OPS (&bcma_pm_ops)
281 #else /* CONFIG_PM_SLEEP */
283 #define BCMA_PM_OPS NULL
285 #endif /* CONFIG_PM_SLEEP */
287 static const struct pci_device_id bcma_pci_bridge_tbl[] = {
288 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
289 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
290 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
291 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
292 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
293 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
294 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
295 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
296 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
297 { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
298 { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0018) },
299 { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_FOXCONN, 0xe092) },
300 { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_HP, 0x804a) },
301 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
302 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
303 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
304 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43b1) },
305 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
306 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
307 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
308 { 0, },
310 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
312 static struct pci_driver bcma_pci_bridge_driver = {
313 .name = "bcma-pci-bridge",
314 .id_table = bcma_pci_bridge_tbl,
315 .probe = bcma_host_pci_probe,
316 .remove = bcma_host_pci_remove,
317 .driver.pm = BCMA_PM_OPS,
320 int __init bcma_host_pci_init(void)
322 return pci_register_driver(&bcma_pci_bridge_driver);
325 void __exit bcma_host_pci_exit(void)
327 pci_unregister_driver(&bcma_pci_bridge_driver);
330 /**************************************************
331 * Runtime ops for drivers.
332 **************************************************/
334 /* See also pcicore_up */
335 void bcma_host_pci_up(struct bcma_bus *bus)
337 if (bus->hosttype != BCMA_HOSTTYPE_PCI)
338 return;
340 if (bus->host_is_pcie2)
341 bcma_core_pcie2_up(&bus->drv_pcie2);
342 else
343 bcma_core_pci_up(&bus->drv_pci[0]);
345 EXPORT_SYMBOL_GPL(bcma_host_pci_up);
347 /* See also pcicore_down */
348 void bcma_host_pci_down(struct bcma_bus *bus)
350 if (bus->hosttype != BCMA_HOSTTYPE_PCI)
351 return;
353 if (!bus->host_is_pcie2)
354 bcma_core_pci_down(&bus->drv_pci[0]);
356 EXPORT_SYMBOL_GPL(bcma_host_pci_down);
358 /* See also si_pci_setup */
359 int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,
360 bool enable)
362 struct pci_dev *pdev;
363 u32 coremask, tmp;
364 int err = 0;
366 if (bus->hosttype != BCMA_HOSTTYPE_PCI) {
367 /* This bcma device is not on a PCI host-bus. So the IRQs are
368 * not routed through the PCI core.
369 * So we must not enable routing through the PCI core. */
370 goto out;
373 pdev = bus->host_pci;
375 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
376 if (err)
377 goto out;
379 coremask = BIT(core->core_index) << 8;
380 if (enable)
381 tmp |= coremask;
382 else
383 tmp &= ~coremask;
385 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
387 out:
388 return err;
390 EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl);