LiteX: driver for MMCM
[linux/fpc-iii.git] / drivers / ptp / idt8a340_reg.h
bloba664dfe5fd2f8ead2725f42f3e65529cf040cb3b
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* idt8a340_reg.h
4 * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019
5 * https://github.com/richardcochran/regen
7 * Hand modified to include some HW registers.
8 * Based on 4.8.0, SCSR rev C commit a03c7ae5
9 */
10 #ifndef HAVE_IDT8A340_REG
11 #define HAVE_IDT8A340_REG
13 #define PAGE_ADDR_BASE 0x0000
14 #define PAGE_ADDR 0x00fc
16 #define HW_REVISION 0x8180
17 #define REV_ID 0x007a
19 #define HW_DPLL_0 (0x8a00)
20 #define HW_DPLL_1 (0x8b00)
21 #define HW_DPLL_2 (0x8c00)
22 #define HW_DPLL_3 (0x8d00)
23 #define HW_DPLL_4 (0x8e00)
24 #define HW_DPLL_5 (0x8f00)
25 #define HW_DPLL_6 (0x9000)
26 #define HW_DPLL_7 (0x9100)
28 #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
29 #define HW_DPLL_TOD_CTRL_1 (0x089)
30 #define HW_DPLL_TOD_CTRL_2 (0x08A)
31 #define HW_DPLL_TOD_OVR__0 (0x098)
32 #define HW_DPLL_TOD_OUT_0__0 (0x0B0)
34 #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
35 #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
36 #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
37 #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
38 #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
39 #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
40 #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
41 #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
42 #define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
43 #define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
44 #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
45 #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
46 #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
47 #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
48 #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
49 #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
51 #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
52 #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
53 #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
54 #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
56 #define SYNCTRL1_MASTER_SYNC_RST BIT(7)
57 #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
58 #define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
59 #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
60 #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
61 #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
62 #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
64 #define HW_Q8_CTRL_SPARE (0xa7d4)
65 #define HW_Q11_CTRL_SPARE (0xa7ec)
67 /**
68 * Select FOD5 as sync_trigger for Q8 divider.
69 * Transition from logic zero to one
70 * sets trigger to sync Q8 divider.
72 * Unused when FOD4 is driving Q8 divider (normal operation).
74 #define Q9_TO_Q8_SYNC_TRIG BIT(1)
76 /**
77 * Enable FOD5 as driver for clock and sync for Q8 divider.
78 * Enable fanout buffer for FOD5.
80 * Unused when FOD4 is driving Q8 divider (normal operation).
82 #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
84 /**
85 * Select FOD6 as sync_trigger for Q11 divider.
86 * Transition from logic zero to one
87 * sets trigger to sync Q11 divider.
89 * Unused when FOD7 is driving Q11 divider (normal operation).
91 #define Q10_TO_Q11_SYNC_TRIG BIT(1)
93 /**
94 * Enable FOD6 as driver for clock and sync for Q11 divider.
95 * Enable fanout buffer for FOD6.
97 * Unused when FOD7 is driving Q11 divider (normal operation).
99 #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
101 #define RESET_CTRL 0xc000
102 #define SM_RESET 0x0012
103 #define SM_RESET_CMD 0x5A
105 #define GENERAL_STATUS 0xc014
106 #define BOOT_STATUS 0x0000
107 #define HW_REV_ID 0x000A
108 #define BOND_ID 0x000B
109 #define HW_CSR_ID 0x000C
110 #define HW_IRQ_ID 0x000E
112 #define MAJ_REL 0x0010
113 #define MIN_REL 0x0011
114 #define HOTFIX_REL 0x0012
116 #define PIPELINE_ID 0x0014
117 #define BUILD_ID 0x0018
119 #define JTAG_DEVICE_ID 0x001c
120 #define PRODUCT_ID 0x001e
122 #define OTP_SCSR_CONFIG_SELECT 0x0022
124 #define STATUS 0xc03c
125 #define USER_GPIO0_TO_7_STATUS 0x008a
126 #define USER_GPIO8_TO_15_STATUS 0x008b
128 #define GPIO_USER_CONTROL 0xc160
129 #define GPIO0_TO_7_OUT 0x0000
130 #define GPIO8_TO_15_OUT 0x0001
132 #define STICKY_STATUS_CLEAR 0xc164
134 #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
136 #define ALERT_CFG 0xc188
138 #define SYS_DPLL_XO 0xc194
140 #define SYS_APLL 0xc19c
142 #define INPUT_0 0xc1b0
144 #define INPUT_1 0xc1c0
146 #define INPUT_2 0xc1d0
148 #define INPUT_3 0xc200
150 #define INPUT_4 0xc210
152 #define INPUT_5 0xc220
154 #define INPUT_6 0xc230
156 #define INPUT_7 0xc240
158 #define INPUT_8 0xc250
160 #define INPUT_9 0xc260
162 #define INPUT_10 0xc280
164 #define INPUT_11 0xc290
166 #define INPUT_12 0xc2a0
168 #define INPUT_13 0xc2b0
170 #define INPUT_14 0xc2c0
172 #define INPUT_15 0xc2d0
174 #define REF_MON_0 0xc2e0
176 #define REF_MON_1 0xc2ec
178 #define REF_MON_2 0xc300
180 #define REF_MON_3 0xc30c
182 #define REF_MON_4 0xc318
184 #define REF_MON_5 0xc324
186 #define REF_MON_6 0xc330
188 #define REF_MON_7 0xc33c
190 #define REF_MON_8 0xc348
192 #define REF_MON_9 0xc354
194 #define REF_MON_10 0xc360
196 #define REF_MON_11 0xc36c
198 #define REF_MON_12 0xc380
200 #define REF_MON_13 0xc38c
202 #define REF_MON_14 0xc398
204 #define REF_MON_15 0xc3a4
206 #define DPLL_0 0xc3b0
207 #define DPLL_CTRL_REG_0 0x0002
208 #define DPLL_CTRL_REG_1 0x0003
209 #define DPLL_CTRL_REG_2 0x0004
210 #define DPLL_TOD_SYNC_CFG 0x0031
211 #define DPLL_COMBO_SLAVE_CFG_0 0x0032
212 #define DPLL_COMBO_SLAVE_CFG_1 0x0033
213 #define DPLL_SLAVE_REF_CFG 0x0034
214 #define DPLL_REF_MODE 0x0035
215 #define DPLL_PHASE_MEASUREMENT_CFG 0x0036
216 #define DPLL_MODE 0x0037
218 #define DPLL_1 0xc400
220 #define DPLL_2 0xc438
222 #define DPLL_3 0xc480
224 #define DPLL_4 0xc4b8
226 #define DPLL_5 0xc500
228 #define DPLL_6 0xc538
230 #define DPLL_7 0xc580
232 #define SYS_DPLL 0xc5b8
234 #define DPLL_CTRL_0 0xc600
235 #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
236 #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
238 #define DPLL_CTRL_1 0xc63c
240 #define DPLL_CTRL_2 0xc680
242 #define DPLL_CTRL_3 0xc6bc
244 #define DPLL_CTRL_4 0xc700
246 #define DPLL_CTRL_5 0xc73c
248 #define DPLL_CTRL_6 0xc780
250 #define DPLL_CTRL_7 0xc7bc
252 #define SYS_DPLL_CTRL 0xc800
254 #define DPLL_PHASE_0 0xc818
256 /* Signed 42-bit FFO in units of 2^(-53) */
257 #define DPLL_WR_PHASE 0x0000
259 #define DPLL_PHASE_1 0xc81c
261 #define DPLL_PHASE_2 0xc820
263 #define DPLL_PHASE_3 0xc824
265 #define DPLL_PHASE_4 0xc828
267 #define DPLL_PHASE_5 0xc82c
269 #define DPLL_PHASE_6 0xc830
271 #define DPLL_PHASE_7 0xc834
273 #define DPLL_FREQ_0 0xc838
275 /* Signed 42-bit FFO in units of 2^(-53) */
276 #define DPLL_WR_FREQ 0x0000
278 #define DPLL_FREQ_1 0xc840
280 #define DPLL_FREQ_2 0xc848
282 #define DPLL_FREQ_3 0xc850
284 #define DPLL_FREQ_4 0xc858
286 #define DPLL_FREQ_5 0xc860
288 #define DPLL_FREQ_6 0xc868
290 #define DPLL_FREQ_7 0xc870
292 #define DPLL_PHASE_PULL_IN_0 0xc880
293 #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
294 #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
295 #define PULL_IN_CTRL 0x0007
297 #define DPLL_PHASE_PULL_IN_1 0xc888
299 #define DPLL_PHASE_PULL_IN_2 0xc890
301 #define DPLL_PHASE_PULL_IN_3 0xc898
303 #define DPLL_PHASE_PULL_IN_4 0xc8a0
305 #define DPLL_PHASE_PULL_IN_5 0xc8a8
307 #define DPLL_PHASE_PULL_IN_6 0xc8b0
309 #define DPLL_PHASE_PULL_IN_7 0xc8b8
311 #define GPIO_CFG 0xc8c0
312 #define GPIO_CFG_GBL 0x0000
314 #define GPIO_0 0xc8c2
315 #define GPIO_DCO_INC_DEC 0x0000
316 #define GPIO_OUT_CTRL_0 0x0001
317 #define GPIO_OUT_CTRL_1 0x0002
318 #define GPIO_TOD_TRIG 0x0003
319 #define GPIO_DPLL_INDICATOR 0x0004
320 #define GPIO_LOS_INDICATOR 0x0005
321 #define GPIO_REF_INPUT_DSQ_0 0x0006
322 #define GPIO_REF_INPUT_DSQ_1 0x0007
323 #define GPIO_REF_INPUT_DSQ_2 0x0008
324 #define GPIO_REF_INPUT_DSQ_3 0x0009
325 #define GPIO_MAN_CLK_SEL_0 0x000a
326 #define GPIO_MAN_CLK_SEL_1 0x000b
327 #define GPIO_MAN_CLK_SEL_2 0x000c
328 #define GPIO_SLAVE 0x000d
329 #define GPIO_ALERT_OUT_CFG 0x000e
330 #define GPIO_TOD_NOTIFICATION_CFG 0x000f
331 #define GPIO_CTRL 0x0010
333 #define GPIO_1 0xc8d4
335 #define GPIO_2 0xc8e6
337 #define GPIO_3 0xc900
339 #define GPIO_4 0xc912
341 #define GPIO_5 0xc924
343 #define GPIO_6 0xc936
345 #define GPIO_7 0xc948
347 #define GPIO_8 0xc95a
349 #define GPIO_9 0xc980
351 #define GPIO_10 0xc992
353 #define GPIO_11 0xc9a4
355 #define GPIO_12 0xc9b6
357 #define GPIO_13 0xc9c8
359 #define GPIO_14 0xc9da
361 #define GPIO_15 0xca00
363 #define OUT_DIV_MUX 0xca12
365 #define OUTPUT_0 0xca14
366 /* FOD frequency output divider value */
367 #define OUT_DIV 0x0000
368 #define OUT_DUTY_CYCLE_HIGH 0x0004
369 #define OUT_CTRL_0 0x0008
370 #define OUT_CTRL_1 0x0009
371 /* Phase adjustment in FOD cycles */
372 #define OUT_PHASE_ADJ 0x000c
374 #define OUTPUT_1 0xca24
376 #define OUTPUT_2 0xca34
378 #define OUTPUT_3 0xca44
380 #define OUTPUT_4 0xca54
382 #define OUTPUT_5 0xca64
384 #define OUTPUT_6 0xca80
386 #define OUTPUT_7 0xca90
388 #define OUTPUT_8 0xcaa0
390 #define OUTPUT_9 0xcab0
392 #define OUTPUT_10 0xcac0
394 #define OUTPUT_11 0xcad0
396 #define SERIAL 0xcae0
398 #define PWM_ENCODER_0 0xcb00
400 #define PWM_ENCODER_1 0xcb08
402 #define PWM_ENCODER_2 0xcb10
404 #define PWM_ENCODER_3 0xcb18
406 #define PWM_ENCODER_4 0xcb20
408 #define PWM_ENCODER_5 0xcb28
410 #define PWM_ENCODER_6 0xcb30
412 #define PWM_ENCODER_7 0xcb38
414 #define PWM_DECODER_0 0xcb40
416 #define PWM_DECODER_1 0xcb48
418 #define PWM_DECODER_2 0xcb50
420 #define PWM_DECODER_3 0xcb58
422 #define PWM_DECODER_4 0xcb60
424 #define PWM_DECODER_5 0xcb68
426 #define PWM_DECODER_6 0xcb70
428 #define PWM_DECODER_7 0xcb80
430 #define PWM_DECODER_8 0xcb88
432 #define PWM_DECODER_9 0xcb90
434 #define PWM_DECODER_10 0xcb98
436 #define PWM_DECODER_11 0xcba0
438 #define PWM_DECODER_12 0xcba8
440 #define PWM_DECODER_13 0xcbb0
442 #define PWM_DECODER_14 0xcbb8
444 #define PWM_DECODER_15 0xcbc0
446 #define PWM_USER_DATA 0xcbc8
448 #define TOD_0 0xcbcc
450 /* Enable TOD counter, output channel sync and even-PPS mode */
451 #define TOD_CFG 0x0000
453 #define TOD_1 0xcbce
455 #define TOD_2 0xcbd0
457 #define TOD_3 0xcbd2
460 #define TOD_WRITE_0 0xcc00
461 /* 8-bit subns, 32-bit ns, 48-bit seconds */
462 #define TOD_WRITE 0x0000
463 /* Counter increments after TOD write is completed */
464 #define TOD_WRITE_COUNTER 0x000c
465 /* TOD write trigger configuration */
466 #define TOD_WRITE_SELECT_CFG_0 0x000d
467 /* TOD write trigger selection */
468 #define TOD_WRITE_CMD 0x000f
470 #define TOD_WRITE_1 0xcc10
472 #define TOD_WRITE_2 0xcc20
474 #define TOD_WRITE_3 0xcc30
476 #define TOD_READ_PRIMARY_0 0xcc40
477 /* 8-bit subns, 32-bit ns, 48-bit seconds */
478 #define TOD_READ_PRIMARY 0x0000
479 /* Counter increments after TOD write is completed */
480 #define TOD_READ_PRIMARY_COUNTER 0x000b
481 /* Read trigger configuration */
482 #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
483 /* Read trigger selection */
484 #define TOD_READ_PRIMARY_CMD 0x000e
486 #define TOD_READ_PRIMARY_1 0xcc50
488 #define TOD_READ_PRIMARY_2 0xcc60
490 #define TOD_READ_PRIMARY_3 0xcc80
492 #define TOD_READ_SECONDARY_0 0xcc90
494 #define TOD_READ_SECONDARY_1 0xcca0
496 #define TOD_READ_SECONDARY_2 0xccb0
498 #define TOD_READ_SECONDARY_3 0xccc0
500 #define OUTPUT_TDC_CFG 0xccd0
502 #define OUTPUT_TDC_0 0xcd00
504 #define OUTPUT_TDC_1 0xcd08
506 #define OUTPUT_TDC_2 0xcd10
508 #define OUTPUT_TDC_3 0xcd18
510 #define INPUT_TDC 0xcd20
512 #define SCRATCH 0xcf50
514 #define EEPROM 0xcf68
516 #define OTP 0xcf70
518 #define BYTE 0xcf80
520 /* Bit definitions for the MAJ_REL register */
521 #define MAJOR_SHIFT (1)
522 #define MAJOR_MASK (0x7f)
523 #define PR_BUILD BIT(0)
525 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
526 #define GPIO0_LEVEL BIT(0)
527 #define GPIO1_LEVEL BIT(1)
528 #define GPIO2_LEVEL BIT(2)
529 #define GPIO3_LEVEL BIT(3)
530 #define GPIO4_LEVEL BIT(4)
531 #define GPIO5_LEVEL BIT(5)
532 #define GPIO6_LEVEL BIT(6)
533 #define GPIO7_LEVEL BIT(7)
535 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
536 #define GPIO8_LEVEL BIT(0)
537 #define GPIO9_LEVEL BIT(1)
538 #define GPIO10_LEVEL BIT(2)
539 #define GPIO11_LEVEL BIT(3)
540 #define GPIO12_LEVEL BIT(4)
541 #define GPIO13_LEVEL BIT(5)
542 #define GPIO14_LEVEL BIT(6)
543 #define GPIO15_LEVEL BIT(7)
545 /* Bit definitions for the GPIO0_TO_7_OUT register */
546 #define GPIO0_DRIVE_LEVEL BIT(0)
547 #define GPIO1_DRIVE_LEVEL BIT(1)
548 #define GPIO2_DRIVE_LEVEL BIT(2)
549 #define GPIO3_DRIVE_LEVEL BIT(3)
550 #define GPIO4_DRIVE_LEVEL BIT(4)
551 #define GPIO5_DRIVE_LEVEL BIT(5)
552 #define GPIO6_DRIVE_LEVEL BIT(6)
553 #define GPIO7_DRIVE_LEVEL BIT(7)
555 /* Bit definitions for the GPIO8_TO_15_OUT register */
556 #define GPIO8_DRIVE_LEVEL BIT(0)
557 #define GPIO9_DRIVE_LEVEL BIT(1)
558 #define GPIO10_DRIVE_LEVEL BIT(2)
559 #define GPIO11_DRIVE_LEVEL BIT(3)
560 #define GPIO12_DRIVE_LEVEL BIT(4)
561 #define GPIO13_DRIVE_LEVEL BIT(5)
562 #define GPIO14_DRIVE_LEVEL BIT(6)
563 #define GPIO15_DRIVE_LEVEL BIT(7)
565 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
566 #define TOD_SYNC_SOURCE_SHIFT (1)
567 #define TOD_SYNC_SOURCE_MASK (0x3)
568 #define TOD_SYNC_EN BIT(0)
570 /* Bit definitions for the DPLL_MODE register */
571 #define WRITE_TIMER_MODE BIT(6)
572 #define PLL_MODE_SHIFT (3)
573 #define PLL_MODE_MASK (0x7)
574 #define STATE_MODE_SHIFT (0)
575 #define STATE_MODE_MASK (0x7)
577 /* Bit definitions for the GPIO_CFG_GBL register */
578 #define SUPPLY_MODE_SHIFT (0)
579 #define SUPPLY_MODE_MASK (0x3)
581 /* Bit definitions for the GPIO_DCO_INC_DEC register */
582 #define INCDEC_DPLL_INDEX_SHIFT (0)
583 #define INCDEC_DPLL_INDEX_MASK (0x7)
585 /* Bit definitions for the GPIO_OUT_CTRL_0 register */
586 #define CTRL_OUT_0 BIT(0)
587 #define CTRL_OUT_1 BIT(1)
588 #define CTRL_OUT_2 BIT(2)
589 #define CTRL_OUT_3 BIT(3)
590 #define CTRL_OUT_4 BIT(4)
591 #define CTRL_OUT_5 BIT(5)
592 #define CTRL_OUT_6 BIT(6)
593 #define CTRL_OUT_7 BIT(7)
595 /* Bit definitions for the GPIO_OUT_CTRL_1 register */
596 #define CTRL_OUT_8 BIT(0)
597 #define CTRL_OUT_9 BIT(1)
598 #define CTRL_OUT_10 BIT(2)
599 #define CTRL_OUT_11 BIT(3)
600 #define CTRL_OUT_12 BIT(4)
601 #define CTRL_OUT_13 BIT(5)
602 #define CTRL_OUT_14 BIT(6)
603 #define CTRL_OUT_15 BIT(7)
605 /* Bit definitions for the GPIO_TOD_TRIG register */
606 #define TOD_TRIG_0 BIT(0)
607 #define TOD_TRIG_1 BIT(1)
608 #define TOD_TRIG_2 BIT(2)
609 #define TOD_TRIG_3 BIT(3)
611 /* Bit definitions for the GPIO_DPLL_INDICATOR register */
612 #define IND_DPLL_INDEX_SHIFT (0)
613 #define IND_DPLL_INDEX_MASK (0x7)
615 /* Bit definitions for the GPIO_LOS_INDICATOR register */
616 #define REFMON_INDEX_SHIFT (0)
617 #define REFMON_INDEX_MASK (0xf)
618 /* Active level of LOS indicator, 0=low 1=high */
619 #define ACTIVE_LEVEL BIT(4)
621 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
622 #define DSQ_INP_0 BIT(0)
623 #define DSQ_INP_1 BIT(1)
624 #define DSQ_INP_2 BIT(2)
625 #define DSQ_INP_3 BIT(3)
626 #define DSQ_INP_4 BIT(4)
627 #define DSQ_INP_5 BIT(5)
628 #define DSQ_INP_6 BIT(6)
629 #define DSQ_INP_7 BIT(7)
631 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
632 #define DSQ_INP_8 BIT(0)
633 #define DSQ_INP_9 BIT(1)
634 #define DSQ_INP_10 BIT(2)
635 #define DSQ_INP_11 BIT(3)
636 #define DSQ_INP_12 BIT(4)
637 #define DSQ_INP_13 BIT(5)
638 #define DSQ_INP_14 BIT(6)
639 #define DSQ_INP_15 BIT(7)
641 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
642 #define DSQ_DPLL_0 BIT(0)
643 #define DSQ_DPLL_1 BIT(1)
644 #define DSQ_DPLL_2 BIT(2)
645 #define DSQ_DPLL_3 BIT(3)
646 #define DSQ_DPLL_4 BIT(4)
647 #define DSQ_DPLL_5 BIT(5)
648 #define DSQ_DPLL_6 BIT(6)
649 #define DSQ_DPLL_7 BIT(7)
651 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
652 #define DSQ_DPLL_SYS BIT(0)
653 #define GPIO_DSQ_LEVEL BIT(1)
655 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
656 #define DPLL_TOD_SHIFT (0)
657 #define DPLL_TOD_MASK (0x3)
658 #define TOD_READ_SECONDARY BIT(2)
659 #define GPIO_ASSERT_LEVEL BIT(3)
661 /* Bit definitions for the GPIO_CTRL register */
662 #define GPIO_FUNCTION_EN BIT(0)
663 #define GPIO_CMOS_OD_MODE BIT(1)
664 #define GPIO_CONTROL_DIR BIT(2)
665 #define GPIO_PU_PD_MODE BIT(3)
666 #define GPIO_FUNCTION_SHIFT (4)
667 #define GPIO_FUNCTION_MASK (0xf)
669 /* Bit definitions for the OUT_CTRL_1 register */
670 #define OUT_SYNC_DISABLE BIT(7)
671 #define SQUELCH_VALUE BIT(6)
672 #define SQUELCH_DISABLE BIT(5)
673 #define PAD_VDDO_SHIFT (2)
674 #define PAD_VDDO_MASK (0x7)
675 #define PAD_CMOSDRV_SHIFT (0)
676 #define PAD_CMOSDRV_MASK (0x3)
678 /* Bit definitions for the TOD_CFG register */
679 #define TOD_EVEN_PPS_MODE BIT(2)
680 #define TOD_OUT_SYNC_ENABLE BIT(1)
681 #define TOD_ENABLE BIT(0)
683 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
684 #define WR_PWM_DECODER_INDEX_SHIFT (4)
685 #define WR_PWM_DECODER_INDEX_MASK (0xf)
686 #define WR_REF_INDEX_SHIFT (0)
687 #define WR_REF_INDEX_MASK (0xf)
689 /* Bit definitions for the TOD_WRITE_CMD register */
690 #define TOD_WRITE_SELECTION_SHIFT (0)
691 #define TOD_WRITE_SELECTION_MASK (0xf)
692 /* 4.8.7 */
693 #define TOD_WRITE_TYPE_SHIFT (4)
694 #define TOD_WRITE_TYPE_MASK (0x3)
696 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
697 #define RD_PWM_DECODER_INDEX_SHIFT (4)
698 #define RD_PWM_DECODER_INDEX_MASK (0xf)
699 #define RD_REF_INDEX_SHIFT (0)
700 #define RD_REF_INDEX_MASK (0xf)
702 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
703 #define TOD_READ_TRIGGER_MODE BIT(4)
704 #define TOD_READ_TRIGGER_SHIFT (0)
705 #define TOD_READ_TRIGGER_MASK (0xf)
707 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
708 #define COMBO_MASTER_HOLD BIT(0)
710 #endif