drivers/spi/spi-dw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DW_SPI_HEADER_H
   3 #define DW_SPI_HEADER_H
   4
   5 #include <linux/bits.h>
   6 #include <linux/completion.h>
   7 #include <linux/debugfs.h>
   8 #include <linux/irqreturn.h>
   9 #include <linux/io.h>
  10 #include <linux/scatterlist.h>
  11 #include <linux/spi/spi-mem.h>
  12 #include <linux/bitfield.h>
  13
  14 /* Register offsets */
  15 #define DW_SPI_CTRLR0                   0x00
  16 #define DW_SPI_CTRLR1                   0x04
  17 #define DW_SPI_SSIENR                   0x08
  18 #define DW_SPI_MWCR                     0x0c
  19 #define DW_SPI_SER                      0x10
  20 #define DW_SPI_BAUDR                    0x14
  21 #define DW_SPI_TXFTLR                   0x18
  22 #define DW_SPI_RXFTLR                   0x1c
  23 #define DW_SPI_TXFLR                    0x20
  24 #define DW_SPI_RXFLR                    0x24
  25 #define DW_SPI_SR                       0x28
  26 #define DW_SPI_IMR                      0x2c
  27 #define DW_SPI_ISR                      0x30
  28 #define DW_SPI_RISR                     0x34
  29 #define DW_SPI_TXOICR                   0x38
  30 #define DW_SPI_RXOICR                   0x3c
  31 #define DW_SPI_RXUICR                   0x40
  32 #define DW_SPI_MSTICR                   0x44
  33 #define DW_SPI_ICR                      0x48
  34 #define DW_SPI_DMACR                    0x4c
  35 #define DW_SPI_DMATDLR                  0x50
  36 #define DW_SPI_DMARDLR                  0x54
  37 #define DW_SPI_IDR                      0x58
  38 #define DW_SPI_VERSION                  0x5c
  39 #define DW_SPI_DR                       0x60
  40 #define DW_SPI_RX_SAMPLE_DLY            0xf0
  41 #define DW_SPI_CS_OVERRIDE              0xf4
  42
  43 /* Bit fields in CTRLR0 */
  44 #define SPI_DFS_OFFSET                  0
  45 #define SPI_DFS_MASK                    GENMASK(3, 0)
  46 #define SPI_DFS32_OFFSET                16
  47
  48 #define SPI_FRF_OFFSET                  4
  49 #define SPI_FRF_SPI                     0x0
  50 #define SPI_FRF_SSP                     0x1
  51 #define SPI_FRF_MICROWIRE               0x2
  52 #define SPI_FRF_RESV                    0x3
  53
  54 #define SPI_MODE_OFFSET                 6
  55 #define SPI_SCPH_OFFSET                 6
  56 #define SPI_SCOL_OFFSET                 7
  57
  58 #define SPI_TMOD_OFFSET                 8
  59 #define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  60 #define SPI_TMOD_TR                     0x0             /* xmit & recv */
  61 #define SPI_TMOD_TO                     0x1             /* xmit only */
  62 #define SPI_TMOD_RO                     0x2             /* recv only */
  63 #define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  64
  65 #define SPI_SLVOE_OFFSET                10
  66 #define SPI_SRL_OFFSET                  11
  67 #define SPI_CFS_OFFSET                  12
  68
  69 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
  70 #define DWC_SSI_CTRLR0_SRL_OFFSET       13
  71 #define DWC_SSI_CTRLR0_TMOD_OFFSET      10
  72 #define DWC_SSI_CTRLR0_TMOD_MASK        GENMASK(11, 10)
  73 #define DWC_SSI_CTRLR0_SCPOL_OFFSET     9
  74 #define DWC_SSI_CTRLR0_SCPH_OFFSET      8
  75 #define DWC_SSI_CTRLR0_FRF_OFFSET       6
  76 #define DWC_SSI_CTRLR0_DFS_OFFSET       0
  77
  78 /*
  79  * For Keem Bay, CTRLR0[31] is used to select controller mode.
  80  * 0: SSI is slave
  81  * 1: SSI is master
  82  */
  83 #define DWC_SSI_CTRLR0_KEEMBAY_MST      BIT(31)
  84
  85 /* Bit fields in CTRLR1 */
  86 #define SPI_NDF_MASK                    GENMASK(15, 0)
  87
  88 /* Bit fields in SR, 7 bits */
  89 #define SR_MASK                         0x7f            /* cover 7 bits */
  90 #define SR_BUSY                         (1 << 0)
  91 #define SR_TF_NOT_FULL                  (1 << 1)
  92 #define SR_TF_EMPT                      (1 << 2)
  93 #define SR_RF_NOT_EMPT                  (1 << 3)
  94 #define SR_RF_FULL                      (1 << 4)
  95 #define SR_TX_ERR                       (1 << 5)
  96 #define SR_DCOL                         (1 << 6)
  97
  98 /* Bit fields in ISR, IMR, RISR, 7 bits */
  99 #define SPI_INT_TXEI                    (1 << 0)
 100 #define SPI_INT_TXOI                    (1 << 1)
 101 #define SPI_INT_RXUI                    (1 << 2)
 102 #define SPI_INT_RXOI                    (1 << 3)
 103 #define SPI_INT_RXFI                    (1 << 4)
 104 #define SPI_INT_MSTI                    (1 << 5)
 105
 106 /* Bit fields in DMACR */
 107 #define SPI_DMA_RDMAE                   (1 << 0)
 108 #define SPI_DMA_TDMAE                   (1 << 1)
 109
 110 #define SPI_WAIT_RETRIES                5
 111 #define SPI_BUF_SIZE \
 112         (sizeof_field(struct spi_mem_op, cmd.opcode) + \
 113          sizeof_field(struct spi_mem_op, addr.val) + 256)
 114 #define SPI_GET_BYTE(_val, _idx) \
 115         ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
 116
 117 enum dw_ssi_type {
 118         SSI_MOTO_SPI = 0,
 119         SSI_TI_SSP,
 120         SSI_NS_MICROWIRE,
 121 };
 122
 123 /* DW SPI capabilities */
 124 #define DW_SPI_CAP_CS_OVERRIDE          BIT(0)
 125 #define DW_SPI_CAP_KEEMBAY_MST          BIT(1)
 126 #define DW_SPI_CAP_DWC_SSI              BIT(2)
 127 #define DW_SPI_CAP_DFS32                BIT(3)
 128
 129 /* Slave spi_transfer/spi_mem_op related */
 130 struct dw_spi_cfg {
 131         u8 tmode;
 132         u8 dfs;
 133         u32 ndf;
 134         u32 freq;
 135 };
 136
 137 struct dw_spi;
 138 struct dw_spi_dma_ops {
 139         int (*dma_init)(struct device *dev, struct dw_spi *dws);
 140         void (*dma_exit)(struct dw_spi *dws);
 141         int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
 142         bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
 143                         struct spi_transfer *xfer);
 144         int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
 145         void (*dma_stop)(struct dw_spi *dws);
 146 };
 147
 148 struct dw_spi {
 149         struct spi_controller   *master;
 150
 151         void __iomem            *regs;
 152         unsigned long           paddr;
 153         int                     irq;
 154         u32                     fifo_len;       /* depth of the FIFO buffer */
 155         unsigned int            dfs_offset;     /* CTRLR0 DFS field offset */
 156         u32                     max_mem_freq;   /* max mem-ops bus freq */
 157         u32                     max_freq;       /* max bus freq supported */
 158
 159         u32                     caps;           /* DW SPI capabilities */
 160
 161         u32                     reg_io_width;   /* DR I/O width in bytes */
 162         u16                     bus_num;
 163         u16                     num_cs;         /* supported slave numbers */
 164         void (*set_cs)(struct spi_device *spi, bool enable);
 165
 166         /* Current message transfer state info */
 167         void                    *tx;
 168         unsigned int            tx_len;
 169         void                    *rx;
 170         unsigned int            rx_len;
 171         u8                      buf[SPI_BUF_SIZE];
 172         int                     dma_mapped;
 173         u8                      n_bytes;        /* current is a 1/2 bytes op */
 174         irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 175         u32                     current_freq;   /* frequency in hz */
 176         u32                     cur_rx_sample_dly;
 177         u32                     def_rx_sample_dly_ns;
 178
 179         /* Custom memory operations */
 180         struct spi_controller_mem_ops mem_ops;
 181
 182         /* DMA info */
 183         struct dma_chan         *txchan;
 184         u32                     txburst;
 185         struct dma_chan         *rxchan;
 186         u32                     rxburst;
 187         u32                     dma_sg_burst;
 188         unsigned long           dma_chan_busy;
 189         dma_addr_t              dma_addr; /* phy address of the Data register */
 190         const struct dw_spi_dma_ops *dma_ops;
 191         struct completion       dma_completion;
 192
 193 #ifdef CONFIG_DEBUG_FS
 194         struct dentry *debugfs;
 195         struct debugfs_regset32 regset;
 196 #endif
 197 };
 198
 199 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
 200 {
 201         return __raw_readl(dws->regs + offset);
 202 }
 203
 204 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
 205 {
 206         __raw_writel(val, dws->regs + offset);
 207 }
 208
 209 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
 210 {
 211         switch (dws->reg_io_width) {
 212         case 2:
 213                 return readw_relaxed(dws->regs + offset);
 214         case 4:
 215         default:
 216                 return readl_relaxed(dws->regs + offset);
 217         }
 218 }
 219
 220 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
 221 {
 222         switch (dws->reg_io_width) {
 223         case 2:
 224                 writew_relaxed(val, dws->regs + offset);
 225                 break;
 226         case 4:
 227         default:
 228                 writel_relaxed(val, dws->regs + offset);
 229                 break;
 230         }
 231 }
 232
 233 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 234 {
 235         dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
 236 }
 237
 238 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 239 {
 240         dw_writel(dws, DW_SPI_BAUDR, div);
 241 }
 242
 243 /* Disable IRQ bits */
 244 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 245 {
 246         u32 new_mask;
 247
 248         new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
 249         dw_writel(dws, DW_SPI_IMR, new_mask);
 250 }
 251
 252 /* Enable IRQ bits */
 253 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 254 {
 255         u32 new_mask;
 256
 257         new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
 258         dw_writel(dws, DW_SPI_IMR, new_mask);
 259 }
 260
 261 /*
 262  * This disables the SPI controller, interrupts, clears the interrupts status
 263  * and CS, then re-enables the controller back. Transmit and receive FIFO
 264  * buffers are cleared when the device is disabled.
 265  */
 266 static inline void spi_reset_chip(struct dw_spi *dws)
 267 {
 268         spi_enable_chip(dws, 0);
 269         spi_mask_intr(dws, 0xff);
 270         dw_readl(dws, DW_SPI_ICR);
 271         dw_writel(dws, DW_SPI_SER, 0);
 272         spi_enable_chip(dws, 1);
 273 }
 274
 275 static inline void spi_shutdown_chip(struct dw_spi *dws)
 276 {
 277         spi_enable_chip(dws, 0);
 278         spi_set_clk(dws, 0);
 279 }
 280
 281 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
 282 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
 283                                  struct dw_spi_cfg *cfg);
 284 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
 285 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
 286 extern void dw_spi_remove_host(struct dw_spi *dws);
 287 extern int dw_spi_suspend_host(struct dw_spi *dws);
 288 extern int dw_spi_resume_host(struct dw_spi *dws);
 289
 290 #ifdef CONFIG_SPI_DW_DMA
 291
 292 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
 293 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
 294
 295 #else
 296
 297 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
 298 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
 299
 300 #endif /* !CONFIG_SPI_DW_DMA */
 301
 302 #endif /* DW_SPI_HEADER_H */