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LiteX: driver for MMCM
[linux/fpc-iii.git] / drivers / spi / spi-fsl-dspi.c
blob0287366874882de8bd941b8617b9625288088772
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4 // Copyright 2020 NXP
5 //
6 // Freescale DSPI driver
7 // This file contains a driver for the Freescale DSPI
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-fsl-dspi.h>
21
22 #define DRIVER_NAME "fsl-dspi"
23
24 #define SPI_MCR 0x00
25 #define SPI_MCR_MASTER BIT(31)
26 #define SPI_MCR_PCSIS(x) ((x) << 16)
27 #define SPI_MCR_CLR_TXF BIT(11)
28 #define SPI_MCR_CLR_RXF BIT(10)
29 #define SPI_MCR_XSPI BIT(3)
30 #define SPI_MCR_DIS_TXF BIT(13)
31 #define SPI_MCR_DIS_RXF BIT(12)
32 #define SPI_MCR_HALT BIT(0)
33
34 #define SPI_TCR 0x08
35 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
36
37 #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
38 #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
39 #define SPI_CTAR_CPOL BIT(26)
40 #define SPI_CTAR_CPHA BIT(25)
41 #define SPI_CTAR_LSBFE BIT(24)
42 #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
43 #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
44 #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
45 #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
46 #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
47 #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
48 #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
49 #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
50 #define SPI_CTAR_SCALE_BITS 0xf
51
52 #define SPI_CTAR0_SLAVE 0x0c
53
54 #define SPI_SR 0x2c
55 #define SPI_SR_TCFQF BIT(31)
56 #define SPI_SR_TFUF BIT(27)
57 #define SPI_SR_TFFF BIT(25)
58 #define SPI_SR_CMDTCF BIT(23)
59 #define SPI_SR_SPEF BIT(21)
60 #define SPI_SR_RFOF BIT(19)
61 #define SPI_SR_TFIWF BIT(18)
62 #define SPI_SR_RFDF BIT(17)
63 #define SPI_SR_CMDFFF BIT(16)
64 #define SPI_SR_CLEAR (SPI_SR_TCFQF | \
65 SPI_SR_TFUF | SPI_SR_TFFF | \
66 SPI_SR_CMDTCF | SPI_SR_SPEF | \
67 SPI_SR_RFOF | SPI_SR_TFIWF | \
68 SPI_SR_RFDF | SPI_SR_CMDFFF)
69
70 #define SPI_RSER_TFFFE BIT(25)
71 #define SPI_RSER_TFFFD BIT(24)
72 #define SPI_RSER_RFDFE BIT(17)
73 #define SPI_RSER_RFDFD BIT(16)
74
75 #define SPI_RSER 0x30
76 #define SPI_RSER_TCFQE BIT(31)
77 #define SPI_RSER_CMDTCFE BIT(23)
78
79 #define SPI_PUSHR 0x34
80 #define SPI_PUSHR_CMD_CONT BIT(15)
81 #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
82 #define SPI_PUSHR_CMD_EOQ BIT(11)
83 #define SPI_PUSHR_CMD_CTCNT BIT(10)
84 #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
85
86 #define SPI_PUSHR_SLAVE 0x34
87
88 #define SPI_POPR 0x38
89
90 #define SPI_TXFR0 0x3c
91 #define SPI_TXFR1 0x40
92 #define SPI_TXFR2 0x44
93 #define SPI_TXFR3 0x48
94 #define SPI_RXFR0 0x7c
95 #define SPI_RXFR1 0x80
96 #define SPI_RXFR2 0x84
97 #define SPI_RXFR3 0x88
98
99 #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
100 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
101 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
102
103 #define SPI_SREX 0x13c
104
105 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
106 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
107
108 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
109
110 struct chip_data {
111 u32 ctar_val;
112 };
113
114 enum dspi_trans_mode {
115 DSPI_XSPI_MODE,
116 DSPI_DMA_MODE,
117 };
118
119 struct fsl_dspi_devtype_data {
120 enum dspi_trans_mode trans_mode;
121 u8 max_clock_factor;
122 int fifo_size;
123 };
124
125 enum {
126 LS1021A,
127 LS1012A,
128 LS1028A,
129 LS1043A,
130 LS1046A,
131 LS2080A,
132 LS2085A,
133 LX2160A,
134 MCF5441X,
135 VF610,
136 };
137
138 static const struct fsl_dspi_devtype_data devtype_data[] = {
139 [VF610] = {
140 .trans_mode = DSPI_DMA_MODE,
141 .max_clock_factor = 2,
142 .fifo_size = 4,
143 },
144 [LS1021A] = {
145 /* Has A-011218 DMA erratum */
146 .trans_mode = DSPI_XSPI_MODE,
147 .max_clock_factor = 8,
148 .fifo_size = 4,
149 },
150 [LS1012A] = {
151 /* Has A-011218 DMA erratum */
152 .trans_mode = DSPI_XSPI_MODE,
153 .max_clock_factor = 8,
154 .fifo_size = 16,
155 },
156 [LS1028A] = {
157 .trans_mode = DSPI_XSPI_MODE,
158 .max_clock_factor = 8,
159 .fifo_size = 4,
160 },
161 [LS1043A] = {
162 /* Has A-011218 DMA erratum */
163 .trans_mode = DSPI_XSPI_MODE,
164 .max_clock_factor = 8,
165 .fifo_size = 16,
166 },
167 [LS1046A] = {
168 /* Has A-011218 DMA erratum */
169 .trans_mode = DSPI_XSPI_MODE,
170 .max_clock_factor = 8,
171 .fifo_size = 16,
172 },
173 [LS2080A] = {
174 .trans_mode = DSPI_XSPI_MODE,
175 .max_clock_factor = 8,
176 .fifo_size = 4,
177 },
178 [LS2085A] = {
179 .trans_mode = DSPI_XSPI_MODE,
180 .max_clock_factor = 8,
181 .fifo_size = 4,
182 },
183 [LX2160A] = {
184 .trans_mode = DSPI_XSPI_MODE,
185 .max_clock_factor = 8,
186 .fifo_size = 4,
187 },
188 [MCF5441X] = {
189 .trans_mode = DSPI_DMA_MODE,
190 .max_clock_factor = 8,
191 .fifo_size = 16,
192 },
193 };
194
195 struct fsl_dspi_dma {
196 u32 *tx_dma_buf;
197 struct dma_chan *chan_tx;
198 dma_addr_t tx_dma_phys;
199 struct completion cmd_tx_complete;
200 struct dma_async_tx_descriptor *tx_desc;
201
202 u32 *rx_dma_buf;
203 struct dma_chan *chan_rx;
204 dma_addr_t rx_dma_phys;
205 struct completion cmd_rx_complete;
206 struct dma_async_tx_descriptor *rx_desc;
207 };
208
209 struct fsl_dspi {
210 struct spi_controller *ctlr;
211 struct platform_device *pdev;
212
213 struct regmap *regmap;
214 struct regmap *regmap_pushr;
215 int irq;
216 struct clk *clk;
217
218 struct spi_transfer *cur_transfer;
219 struct spi_message *cur_msg;
220 struct chip_data *cur_chip;
221 size_t progress;
222 size_t len;
223 const void *tx;
224 void *rx;
225 u16 tx_cmd;
226 const struct fsl_dspi_devtype_data *devtype_data;
227
228 struct completion xfer_done;
229
230 struct fsl_dspi_dma *dma;
231
232 int oper_word_size;
233 int oper_bits_per_word;
234
235 int words_in_flight;
236
237 /*
238 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
239 * individually (in XSPI mode)
240 */
241 int pushr_cmd;
242 int pushr_tx;
243
244 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
245 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
246 };
247
248 static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
249 {
250 switch (dspi->oper_word_size) {
251 case 1:
252 *txdata = *(u8 *)dspi->tx;
253 break;
254 case 2:
255 *txdata = *(u16 *)dspi->tx;
256 break;
257 case 4:
258 *txdata = *(u32 *)dspi->tx;
259 break;
260 }
261 dspi->tx += dspi->oper_word_size;
262 }
263
264 static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
265 {
266 switch (dspi->oper_word_size) {
267 case 1:
268 *(u8 *)dspi->rx = rxdata;
269 break;
270 case 2:
271 *(u16 *)dspi->rx = rxdata;
272 break;
273 case 4:
274 *(u32 *)dspi->rx = rxdata;
275 break;
276 }
277 dspi->rx += dspi->oper_word_size;
278 }
279
280 static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
281 {
282 *txdata = cpu_to_be32(*(u32 *)dspi->tx);
283 dspi->tx += sizeof(u32);
284 }
285
286 static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
287 {
288 *(u32 *)dspi->rx = be32_to_cpu(rxdata);
289 dspi->rx += sizeof(u32);
290 }
291
292 static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
293 {
294 *txdata = cpu_to_be16(*(u16 *)dspi->tx);
295 dspi->tx += sizeof(u16);
296 }
297
298 static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
299 {
300 *(u16 *)dspi->rx = be16_to_cpu(rxdata);
301 dspi->rx += sizeof(u16);
302 }
303
304 static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
305 {
306 u16 hi = *(u16 *)dspi->tx;
307 u16 lo = *(u16 *)(dspi->tx + 2);
308
309 *txdata = (u32)hi << 16 | lo;
310 dspi->tx += sizeof(u32);
311 }
312
313 static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
314 {
315 u16 hi = rxdata & 0xffff;
316 u16 lo = rxdata >> 16;
317
318 *(u16 *)dspi->rx = lo;
319 *(u16 *)(dspi->rx + 2) = hi;
320 dspi->rx += sizeof(u32);
321 }
322
323 /*
324 * Pop one word from the TX buffer for pushing into the
325 * PUSHR register (TX FIFO)
326 */
327 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
328 {
329 u32 txdata = 0;
330
331 if (dspi->tx)
332 dspi->host_to_dev(dspi, &txdata);
333 dspi->len -= dspi->oper_word_size;
334 return txdata;
335 }
336
337 /* Prepare one TX FIFO entry (txdata plus cmd) */
338 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
339 {
340 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
341
342 if (spi_controller_is_slave(dspi->ctlr))
343 return data;
344
345 if (dspi->len > 0)
346 cmd |= SPI_PUSHR_CMD_CONT;
347 return cmd << 16 | data;
348 }
349
350 /* Push one word to the RX buffer from the POPR register (RX FIFO) */
351 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
352 {
353 if (!dspi->rx)
354 return;
355 dspi->dev_to_host(dspi, rxdata);
356 }
357
358 static void dspi_tx_dma_callback(void *arg)
359 {
360 struct fsl_dspi *dspi = arg;
361 struct fsl_dspi_dma *dma = dspi->dma;
362
363 complete(&dma->cmd_tx_complete);
364 }
365
366 static void dspi_rx_dma_callback(void *arg)
367 {
368 struct fsl_dspi *dspi = arg;
369 struct fsl_dspi_dma *dma = dspi->dma;
370 int i;
371
372 if (dspi->rx) {
373 for (i = 0; i < dspi->words_in_flight; i++)
374 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
375 }
376
377 complete(&dma->cmd_rx_complete);
378 }
379
380 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
381 {
382 struct device *dev = &dspi->pdev->dev;
383 struct fsl_dspi_dma *dma = dspi->dma;
384 int time_left;
385 int i;
386
387 for (i = 0; i < dspi->words_in_flight; i++)
388 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
389
390 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
391 dma->tx_dma_phys,
392 dspi->words_in_flight *
393 DMA_SLAVE_BUSWIDTH_4_BYTES,
394 DMA_MEM_TO_DEV,
395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
396 if (!dma->tx_desc) {
397 dev_err(dev, "Not able to get desc for DMA xfer\n");
398 return -EIO;
399 }
400
401 dma->tx_desc->callback = dspi_tx_dma_callback;
402 dma->tx_desc->callback_param = dspi;
403 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
404 dev_err(dev, "DMA submit failed\n");
405 return -EINVAL;
406 }
407
408 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
409 dma->rx_dma_phys,
410 dspi->words_in_flight *
411 DMA_SLAVE_BUSWIDTH_4_BYTES,
412 DMA_DEV_TO_MEM,
413 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
414 if (!dma->rx_desc) {
415 dev_err(dev, "Not able to get desc for DMA xfer\n");
416 return -EIO;
417 }
418
419 dma->rx_desc->callback = dspi_rx_dma_callback;
420 dma->rx_desc->callback_param = dspi;
421 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
422 dev_err(dev, "DMA submit failed\n");
423 return -EINVAL;
424 }
425
426 reinit_completion(&dspi->dma->cmd_rx_complete);
427 reinit_completion(&dspi->dma->cmd_tx_complete);
428
429 dma_async_issue_pending(dma->chan_rx);
430 dma_async_issue_pending(dma->chan_tx);
431
432 if (spi_controller_is_slave(dspi->ctlr)) {
433 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
434 return 0;
435 }
436
437 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
438 DMA_COMPLETION_TIMEOUT);
439 if (time_left == 0) {
440 dev_err(dev, "DMA tx timeout\n");
441 dmaengine_terminate_all(dma->chan_tx);
442 dmaengine_terminate_all(dma->chan_rx);
443 return -ETIMEDOUT;
444 }
445
446 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
447 DMA_COMPLETION_TIMEOUT);
448 if (time_left == 0) {
449 dev_err(dev, "DMA rx timeout\n");
450 dmaengine_terminate_all(dma->chan_tx);
451 dmaengine_terminate_all(dma->chan_rx);
452 return -ETIMEDOUT;
453 }
454
455 return 0;
456 }
457
458 static void dspi_setup_accel(struct fsl_dspi *dspi);
459
460 static int dspi_dma_xfer(struct fsl_dspi *dspi)
461 {
462 struct spi_message *message = dspi->cur_msg;
463 struct device *dev = &dspi->pdev->dev;
464 int ret = 0;
465
466 /*
467 * dspi->len gets decremented by dspi_pop_tx_pushr in
468 * dspi_next_xfer_dma_submit
469 */
470 while (dspi->len) {
471 /* Figure out operational bits-per-word for this chunk */
472 dspi_setup_accel(dspi);
473
474 dspi->words_in_flight = dspi->len / dspi->oper_word_size;
475 if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
476 dspi->words_in_flight = dspi->devtype_data->fifo_size;
477
478 message->actual_length += dspi->words_in_flight *
479 dspi->oper_word_size;
480
481 ret = dspi_next_xfer_dma_submit(dspi);
482 if (ret) {
483 dev_err(dev, "DMA transfer failed\n");
484 break;
485 }
486 }
487
488 return ret;
489 }
490
491 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
492 {
493 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
494 struct device *dev = &dspi->pdev->dev;
495 struct dma_slave_config cfg;
496 struct fsl_dspi_dma *dma;
497 int ret;
498
499 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
500 if (!dma)
501 return -ENOMEM;
502
503 dma->chan_rx = dma_request_chan(dev, "rx");
504 if (IS_ERR(dma->chan_rx)) {
505 dev_err(dev, "rx dma channel not available\n");
506 ret = PTR_ERR(dma->chan_rx);
507 return ret;
508 }
509
510 dma->chan_tx = dma_request_chan(dev, "tx");
511 if (IS_ERR(dma->chan_tx)) {
512 dev_err(dev, "tx dma channel not available\n");
513 ret = PTR_ERR(dma->chan_tx);
514 goto err_tx_channel;
515 }
516
517 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
518 dma_bufsize, &dma->tx_dma_phys,
519 GFP_KERNEL);
520 if (!dma->tx_dma_buf) {
521 ret = -ENOMEM;
522 goto err_tx_dma_buf;
523 }
524
525 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
526 dma_bufsize, &dma->rx_dma_phys,
527 GFP_KERNEL);
528 if (!dma->rx_dma_buf) {
529 ret = -ENOMEM;
530 goto err_rx_dma_buf;
531 }
532
533 cfg.src_addr = phy_addr + SPI_POPR;
534 cfg.dst_addr = phy_addr + SPI_PUSHR;
535 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
537 cfg.src_maxburst = 1;
538 cfg.dst_maxburst = 1;
539
540 cfg.direction = DMA_DEV_TO_MEM;
541 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
542 if (ret) {
543 dev_err(dev, "can't configure rx dma channel\n");
544 ret = -EINVAL;
545 goto err_slave_config;
546 }
547
548 cfg.direction = DMA_MEM_TO_DEV;
549 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
550 if (ret) {
551 dev_err(dev, "can't configure tx dma channel\n");
552 ret = -EINVAL;
553 goto err_slave_config;
554 }
555
556 dspi->dma = dma;
557 init_completion(&dma->cmd_tx_complete);
558 init_completion(&dma->cmd_rx_complete);
559
560 return 0;
561
562 err_slave_config:
563 dma_free_coherent(dma->chan_rx->device->dev,
564 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
565 err_rx_dma_buf:
566 dma_free_coherent(dma->chan_tx->device->dev,
567 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
568 err_tx_dma_buf:
569 dma_release_channel(dma->chan_tx);
570 err_tx_channel:
571 dma_release_channel(dma->chan_rx);
572
573 devm_kfree(dev, dma);
574 dspi->dma = NULL;
575
576 return ret;
577 }
578
579 static void dspi_release_dma(struct fsl_dspi *dspi)
580 {
581 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
582 struct fsl_dspi_dma *dma = dspi->dma;
583
584 if (!dma)
585 return;
586
587 if (dma->chan_tx) {
588 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
589 dma->tx_dma_buf, dma->tx_dma_phys);
590 dma_release_channel(dma->chan_tx);
591 }
592
593 if (dma->chan_rx) {
594 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
595 dma->rx_dma_buf, dma->rx_dma_phys);
596 dma_release_channel(dma->chan_rx);
597 }
598 }
599
600 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
601 unsigned long clkrate)
602 {
603 /* Valid baud rate pre-scaler values */
604 int pbr_tbl[4] = {2, 3, 5, 7};
605 int brs[16] = { 2, 4, 6, 8,
606 16, 32, 64, 128,
607 256, 512, 1024, 2048,
608 4096, 8192, 16384, 32768 };
609 int scale_needed, scale, minscale = INT_MAX;
610 int i, j;
611
612 scale_needed = clkrate / speed_hz;
613 if (clkrate % speed_hz)
614 scale_needed++;
615
616 for (i = 0; i < ARRAY_SIZE(brs); i++)
617 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
618 scale = brs[i] * pbr_tbl[j];
619 if (scale >= scale_needed) {
620 if (scale < minscale) {
621 minscale = scale;
622 *br = i;
623 *pbr = j;
624 }
625 break;
626 }
627 }
628
629 if (minscale == INT_MAX) {
630 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
631 speed_hz, clkrate);
632 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
633 *br = ARRAY_SIZE(brs) - 1;
634 }
635 }
636
637 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
638 unsigned long clkrate)
639 {
640 int scale_needed, scale, minscale = INT_MAX;
641 int pscale_tbl[4] = {1, 3, 5, 7};
642 u32 remainder;
643 int i, j;
644
645 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
646 &remainder);
647 if (remainder)
648 scale_needed++;
649
650 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
651 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
652 scale = pscale_tbl[i] * (2 << j);
653 if (scale >= scale_needed) {
654 if (scale < minscale) {
655 minscale = scale;
656 *psc = i;
657 *sc = j;
658 }
659 break;
660 }
661 }
662
663 if (minscale == INT_MAX) {
664 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
665 delay_ns, clkrate);
666 *psc = ARRAY_SIZE(pscale_tbl) - 1;
667 *sc = SPI_CTAR_SCALE_BITS;
668 }
669 }
670
671 static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
672 {
673 /*
674 * The only time when the PCS doesn't need continuation after this word
675 * is when it's last. We need to look ahead, because we actually call
676 * dspi_pop_tx (the function that decrements dspi->len) _after_
677 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
678 * word is enough. If there's more to transmit than that,
679 * dspi_xspi_write will know to split the FIFO writes in 2, and
680 * generate a new PUSHR command with the final word that will have PCS
681 * deasserted (not continued) here.
682 */
683 if (dspi->len > dspi->oper_word_size)
684 cmd |= SPI_PUSHR_CMD_CONT;
685 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
686 }
687
688 static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
689 {
690 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
691 }
692
693 static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
694 {
695 int num_bytes = num_words * dspi->oper_word_size;
696 u16 tx_cmd = dspi->tx_cmd;
697
698 /*
699 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
700 * and cs_change does not want the PCS to stay on), then we need a new
701 * PUSHR command, since this one (for the body of the buffer)
702 * necessarily has the CONT bit set.
703 * So send one word less during this go, to force a split and a command
704 * with a single word next time, when CONT will be unset.
705 */
706 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
707 tx_cmd |= SPI_PUSHR_CMD_EOQ;
708
709 /* Update CTARE */
710 regmap_write(dspi->regmap, SPI_CTARE(0),
711 SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
712 SPI_CTARE_DTCP(num_words));
713
714 /*
715 * Write the CMD FIFO entry first, and then the two
716 * corresponding TX FIFO entries (or one...).
717 */
718 dspi_pushr_cmd_write(dspi, tx_cmd);
719
720 /* Fill TX FIFO with as many transfers as possible */
721 while (num_words--) {
722 u32 data = dspi_pop_tx(dspi);
723
724 dspi_pushr_txdata_write(dspi, data & 0xFFFF);
725 if (dspi->oper_bits_per_word > 16)
726 dspi_pushr_txdata_write(dspi, data >> 16);
727 }
728 }
729
730 static u32 dspi_popr_read(struct fsl_dspi *dspi)
731 {
732 u32 rxdata = 0;
733
734 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
735 return rxdata;
736 }
737
738 static void dspi_fifo_read(struct fsl_dspi *dspi)
739 {
740 int num_fifo_entries = dspi->words_in_flight;
741
742 /* Read one FIFO entry and push to rx buffer */
743 while (num_fifo_entries--)
744 dspi_push_rx(dspi, dspi_popr_read(dspi));
745 }
746
747 static void dspi_setup_accel(struct fsl_dspi *dspi)
748 {
749 struct spi_transfer *xfer = dspi->cur_transfer;
750 bool odd = !!(dspi->len & 1);
751
752 /* No accel for frames not multiple of 8 bits at the moment */
753 if (xfer->bits_per_word % 8)
754 goto no_accel;
755
756 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
757 dspi->oper_bits_per_word = 16;
758 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
759 dspi->oper_bits_per_word = 8;
760 } else {
761 /* Start off with maximum supported by hardware */
762 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
763 dspi->oper_bits_per_word = 32;
764 else
765 dspi->oper_bits_per_word = 16;
766
767 /*
768 * And go down only if the buffer can't be sent with
769 * words this big
770 */
771 do {
772 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
773 break;
774
775 dspi->oper_bits_per_word /= 2;
776 } while (dspi->oper_bits_per_word > 8);
777 }
778
779 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
780 dspi->dev_to_host = dspi_8on32_dev_to_host;
781 dspi->host_to_dev = dspi_8on32_host_to_dev;
782 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
783 dspi->dev_to_host = dspi_8on16_dev_to_host;
784 dspi->host_to_dev = dspi_8on16_host_to_dev;
785 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
786 dspi->dev_to_host = dspi_16on32_dev_to_host;
787 dspi->host_to_dev = dspi_16on32_host_to_dev;
788 } else {
789 no_accel:
790 dspi->dev_to_host = dspi_native_dev_to_host;
791 dspi->host_to_dev = dspi_native_host_to_dev;
792 dspi->oper_bits_per_word = xfer->bits_per_word;
793 }
794
795 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
796
797 /*
798 * Update CTAR here (code is common for XSPI and DMA modes).
799 * We will update CTARE in the portion specific to XSPI, when we
800 * also know the preload value (DTCP).
801 */
802 regmap_write(dspi->regmap, SPI_CTAR(0),
803 dspi->cur_chip->ctar_val |
804 SPI_FRAME_BITS(dspi->oper_bits_per_word));
805 }
806
807 static void dspi_fifo_write(struct fsl_dspi *dspi)
808 {
809 int num_fifo_entries = dspi->devtype_data->fifo_size;
810 struct spi_transfer *xfer = dspi->cur_transfer;
811 struct spi_message *msg = dspi->cur_msg;
812 int num_words, num_bytes;
813
814 dspi_setup_accel(dspi);
815
816 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
817 if (dspi->oper_word_size == 4)
818 num_fifo_entries /= 2;
819
820 /*
821 * Integer division intentionally trims off odd (or non-multiple of 4)
822 * numbers of bytes at the end of the buffer, which will be sent next
823 * time using a smaller oper_word_size.
824 */
825 num_words = dspi->len / dspi->oper_word_size;
826 if (num_words > num_fifo_entries)
827 num_words = num_fifo_entries;
828
829 /* Update total number of bytes that were transferred */
830 num_bytes = num_words * dspi->oper_word_size;
831 msg->actual_length += num_bytes;
832 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
833
834 /*
835 * Update shared variable for use in the next interrupt (both in
836 * dspi_fifo_read and in dspi_fifo_write).
837 */
838 dspi->words_in_flight = num_words;
839
840 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
841
842 dspi_xspi_fifo_write(dspi, num_words);
843 /*
844 * Everything after this point is in a potential race with the next
845 * interrupt, so we must never use dspi->words_in_flight again since it
846 * might already be modified by the next dspi_fifo_write.
847 */
848
849 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
850 dspi->progress, !dspi->irq);
851 }
852
853 static int dspi_rxtx(struct fsl_dspi *dspi)
854 {
855 dspi_fifo_read(dspi);
856
857 if (!dspi->len)
858 /* Success! */
859 return 0;
860
861 dspi_fifo_write(dspi);
862
863 return -EINPROGRESS;
864 }
865
866 static int dspi_poll(struct fsl_dspi *dspi)
867 {
868 int tries = 1000;
869 u32 spi_sr;
870
871 do {
872 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
873 regmap_write(dspi->regmap, SPI_SR, spi_sr);
874
875 if (spi_sr & SPI_SR_CMDTCF)
876 break;
877 } while (--tries);
878
879 if (!tries)
880 return -ETIMEDOUT;
881
882 return dspi_rxtx(dspi);
883 }
884
885 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
886 {
887 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
888 u32 spi_sr;
889
890 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
891 regmap_write(dspi->regmap, SPI_SR, spi_sr);
892
893 if (!(spi_sr & SPI_SR_CMDTCF))
894 return IRQ_NONE;
895
896 if (dspi_rxtx(dspi) == 0)
897 complete(&dspi->xfer_done);
898
899 return IRQ_HANDLED;
900 }
901
902 static int dspi_transfer_one_message(struct spi_controller *ctlr,
903 struct spi_message *message)
904 {
905 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
906 struct spi_device *spi = message->spi;
907 struct spi_transfer *transfer;
908 int status = 0;
909
910 message->actual_length = 0;
911
912 list_for_each_entry(transfer, &message->transfers, transfer_list) {
913 dspi->cur_transfer = transfer;
914 dspi->cur_msg = message;
915 dspi->cur_chip = spi_get_ctldata(spi);
916 /* Prepare command word for CMD FIFO */
917 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
918 SPI_PUSHR_CMD_PCS(spi->chip_select);
919 if (list_is_last(&dspi->cur_transfer->transfer_list,
920 &dspi->cur_msg->transfers)) {
921 /* Leave PCS activated after last transfer when
922 * cs_change is set.
923 */
924 if (transfer->cs_change)
925 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
926 } else {
927 /* Keep PCS active between transfers in same message
928 * when cs_change is not set, and de-activate PCS
929 * between transfers in the same message when
930 * cs_change is set.
931 */
932 if (!transfer->cs_change)
933 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
934 }
935
936 dspi->tx = transfer->tx_buf;
937 dspi->rx = transfer->rx_buf;
938 dspi->len = transfer->len;
939 dspi->progress = 0;
940
941 regmap_update_bits(dspi->regmap, SPI_MCR,
942 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
943 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
944
945 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
946 dspi->progress, !dspi->irq);
947
948 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
949 status = dspi_dma_xfer(dspi);
950 } else {
951 dspi_fifo_write(dspi);
952
953 if (dspi->irq) {
954 wait_for_completion(&dspi->xfer_done);
955 reinit_completion(&dspi->xfer_done);
956 } else {
957 do {
958 status = dspi_poll(dspi);
959 } while (status == -EINPROGRESS);
960 }
961 }
962 if (status)
963 break;
964
965 spi_transfer_delay_exec(transfer);
966 }
967
968 message->status = status;
969 spi_finalize_current_message(ctlr);
970
971 return status;
972 }
973
974 static int dspi_setup(struct spi_device *spi)
975 {
976 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
977 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
978 u32 cs_sck_delay = 0, sck_cs_delay = 0;
979 struct fsl_dspi_platform_data *pdata;
980 unsigned char pasc = 0, asc = 0;
981 struct chip_data *chip;
982 unsigned long clkrate;
983
984 /* Only alloc on first setup */
985 chip = spi_get_ctldata(spi);
986 if (chip == NULL) {
987 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
988 if (!chip)
989 return -ENOMEM;
990 }
991
992 pdata = dev_get_platdata(&dspi->pdev->dev);
993
994 if (!pdata) {
995 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
996 &cs_sck_delay);
997
998 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
999 &sck_cs_delay);
1000 } else {
1001 cs_sck_delay = pdata->cs_sck_delay;
1002 sck_cs_delay = pdata->sck_cs_delay;
1003 }
1004
1005 clkrate = clk_get_rate(dspi->clk);
1006 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1007
1008 /* Set PCS to SCK delay scale values */
1009 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1010
1011 /* Set After SCK delay scale values */
1012 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1013
1014 chip->ctar_val = 0;
1015 if (spi->mode & SPI_CPOL)
1016 chip->ctar_val |= SPI_CTAR_CPOL;
1017 if (spi->mode & SPI_CPHA)
1018 chip->ctar_val |= SPI_CTAR_CPHA;
1019
1020 if (!spi_controller_is_slave(dspi->ctlr)) {
1021 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1022 SPI_CTAR_CSSCK(cssck) |
1023 SPI_CTAR_PASC(pasc) |
1024 SPI_CTAR_ASC(asc) |
1025 SPI_CTAR_PBR(pbr) |
1026 SPI_CTAR_BR(br);
1027
1028 if (spi->mode & SPI_LSB_FIRST)
1029 chip->ctar_val |= SPI_CTAR_LSBFE;
1030 }
1031
1032 spi_set_ctldata(spi, chip);
1033
1034 return 0;
1035 }
1036
1037 static void dspi_cleanup(struct spi_device *spi)
1038 {
1039 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1040
1041 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1042 spi->controller->bus_num, spi->chip_select);
1043
1044 kfree(chip);
1045 }
1046
1047 static const struct of_device_id fsl_dspi_dt_ids[] = {
1048 {
1049 .compatible = "fsl,vf610-dspi",
1050 .data = &devtype_data[VF610],
1051 }, {
1052 .compatible = "fsl,ls1021a-v1.0-dspi",
1053 .data = &devtype_data[LS1021A],
1054 }, {
1055 .compatible = "fsl,ls1012a-dspi",
1056 .data = &devtype_data[LS1012A],
1057 }, {
1058 .compatible = "fsl,ls1028a-dspi",
1059 .data = &devtype_data[LS1028A],
1060 }, {
1061 .compatible = "fsl,ls1043a-dspi",
1062 .data = &devtype_data[LS1043A],
1063 }, {
1064 .compatible = "fsl,ls1046a-dspi",
1065 .data = &devtype_data[LS1046A],
1066 }, {
1067 .compatible = "fsl,ls2080a-dspi",
1068 .data = &devtype_data[LS2080A],
1069 }, {
1070 .compatible = "fsl,ls2085a-dspi",
1071 .data = &devtype_data[LS2085A],
1072 }, {
1073 .compatible = "fsl,lx2160a-dspi",
1074 .data = &devtype_data[LX2160A],
1075 },
1076 { /* sentinel */ }
1077 };
1078 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1079
1080 #ifdef CONFIG_PM_SLEEP
1081 static int dspi_suspend(struct device *dev)
1082 {
1083 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1084
1085 if (dspi->irq)
1086 disable_irq(dspi->irq);
1087 spi_controller_suspend(dspi->ctlr);
1088 clk_disable_unprepare(dspi->clk);
1089
1090 pinctrl_pm_select_sleep_state(dev);
1091
1092 return 0;
1093 }
1094
1095 static int dspi_resume(struct device *dev)
1096 {
1097 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1098 int ret;
1099
1100 pinctrl_pm_select_default_state(dev);
1101
1102 ret = clk_prepare_enable(dspi->clk);
1103 if (ret)
1104 return ret;
1105 spi_controller_resume(dspi->ctlr);
1106 if (dspi->irq)
1107 enable_irq(dspi->irq);
1108
1109 return 0;
1110 }
1111 #endif /* CONFIG_PM_SLEEP */
1112
1113 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1114
1115 static const struct regmap_range dspi_volatile_ranges[] = {
1116 regmap_reg_range(SPI_MCR, SPI_TCR),
1117 regmap_reg_range(SPI_SR, SPI_SR),
1118 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1119 };
1120
1121 static const struct regmap_access_table dspi_volatile_table = {
1122 .yes_ranges = dspi_volatile_ranges,
1123 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1124 };
1125
1126 static const struct regmap_config dspi_regmap_config = {
1127 .reg_bits = 32,
1128 .val_bits = 32,
1129 .reg_stride = 4,
1130 .max_register = 0x88,
1131 .volatile_table = &dspi_volatile_table,
1132 };
1133
1134 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1135 regmap_reg_range(SPI_MCR, SPI_TCR),
1136 regmap_reg_range(SPI_SR, SPI_SR),
1137 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1138 regmap_reg_range(SPI_SREX, SPI_SREX),
1139 };
1140
1141 static const struct regmap_access_table dspi_xspi_volatile_table = {
1142 .yes_ranges = dspi_xspi_volatile_ranges,
1143 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1144 };
1145
1146 static const struct regmap_config dspi_xspi_regmap_config[] = {
1147 {
1148 .reg_bits = 32,
1149 .val_bits = 32,
1150 .reg_stride = 4,
1151 .max_register = 0x13c,
1152 .volatile_table = &dspi_xspi_volatile_table,
1153 },
1154 {
1155 .name = "pushr",
1156 .reg_bits = 16,
1157 .val_bits = 16,
1158 .reg_stride = 2,
1159 .max_register = 0x2,
1160 },
1161 };
1162
1163 static int dspi_init(struct fsl_dspi *dspi)
1164 {
1165 unsigned int mcr;
1166
1167 /* Set idle states for all chip select signals to high */
1168 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1169
1170 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1171 mcr |= SPI_MCR_XSPI;
1172 if (!spi_controller_is_slave(dspi->ctlr))
1173 mcr |= SPI_MCR_MASTER;
1174
1175 regmap_write(dspi->regmap, SPI_MCR, mcr);
1176 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1177
1178 switch (dspi->devtype_data->trans_mode) {
1179 case DSPI_XSPI_MODE:
1180 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1181 break;
1182 case DSPI_DMA_MODE:
1183 regmap_write(dspi->regmap, SPI_RSER,
1184 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1185 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1186 break;
1187 default:
1188 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1189 dspi->devtype_data->trans_mode);
1190 return -EINVAL;
1191 }
1192
1193 return 0;
1194 }
1195
1196 static int dspi_slave_abort(struct spi_master *master)
1197 {
1198 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1199
1200 /*
1201 * Terminate all pending DMA transactions for the SPI working
1202 * in SLAVE mode.
1203 */
1204 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1205 dmaengine_terminate_sync(dspi->dma->chan_rx);
1206 dmaengine_terminate_sync(dspi->dma->chan_tx);
1207 }
1208
1209 /* Clear the internal DSPI RX and TX FIFO buffers */
1210 regmap_update_bits(dspi->regmap, SPI_MCR,
1211 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1212 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1213
1214 return 0;
1215 }
1216
1217 static int dspi_probe(struct platform_device *pdev)
1218 {
1219 struct device_node *np = pdev->dev.of_node;
1220 const struct regmap_config *regmap_config;
1221 struct fsl_dspi_platform_data *pdata;
1222 struct spi_controller *ctlr;
1223 int ret, cs_num, bus_num = -1;
1224 struct fsl_dspi *dspi;
1225 struct resource *res;
1226 void __iomem *base;
1227 bool big_endian;
1228
1229 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1230 if (!dspi)
1231 return -ENOMEM;
1232
1233 ctlr = spi_alloc_master(&pdev->dev, 0);
1234 if (!ctlr)
1235 return -ENOMEM;
1236
1237 spi_controller_set_devdata(ctlr, dspi);
1238 platform_set_drvdata(pdev, dspi);
1239
1240 dspi->pdev = pdev;
1241 dspi->ctlr = ctlr;
1242
1243 ctlr->setup = dspi_setup;
1244 ctlr->transfer_one_message = dspi_transfer_one_message;
1245 ctlr->dev.of_node = pdev->dev.of_node;
1246
1247 ctlr->cleanup = dspi_cleanup;
1248 ctlr->slave_abort = dspi_slave_abort;
1249 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1250
1251 pdata = dev_get_platdata(&pdev->dev);
1252 if (pdata) {
1253 ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1254 ctlr->bus_num = pdata->bus_num;
1255
1256 /* Only Coldfire uses platform data */
1257 dspi->devtype_data = &devtype_data[MCF5441X];
1258 big_endian = true;
1259 } else {
1260
1261 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1262 if (ret < 0) {
1263 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1264 goto out_ctlr_put;
1265 }
1266 ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1267
1268 of_property_read_u32(np, "bus-num", &bus_num);
1269 ctlr->bus_num = bus_num;
1270
1271 if (of_property_read_bool(np, "spi-slave"))
1272 ctlr->slave = true;
1273
1274 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1275 if (!dspi->devtype_data) {
1276 dev_err(&pdev->dev, "can't get devtype_data\n");
1277 ret = -EFAULT;
1278 goto out_ctlr_put;
1279 }
1280
1281 big_endian = of_device_is_big_endian(np);
1282 }
1283 if (big_endian) {
1284 dspi->pushr_cmd = 0;
1285 dspi->pushr_tx = 2;
1286 } else {
1287 dspi->pushr_cmd = 2;
1288 dspi->pushr_tx = 0;
1289 }
1290
1291 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1292 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1293 else
1294 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1295
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 base = devm_ioremap_resource(&pdev->dev, res);
1298 if (IS_ERR(base)) {
1299 ret = PTR_ERR(base);
1300 goto out_ctlr_put;
1301 }
1302
1303 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1304 regmap_config = &dspi_xspi_regmap_config[0];
1305 else
1306 regmap_config = &dspi_regmap_config;
1307 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1308 if (IS_ERR(dspi->regmap)) {
1309 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1310 PTR_ERR(dspi->regmap));
1311 ret = PTR_ERR(dspi->regmap);
1312 goto out_ctlr_put;
1313 }
1314
1315 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1316 dspi->regmap_pushr = devm_regmap_init_mmio(
1317 &pdev->dev, base + SPI_PUSHR,
1318 &dspi_xspi_regmap_config[1]);
1319 if (IS_ERR(dspi->regmap_pushr)) {
1320 dev_err(&pdev->dev,
1321 "failed to init pushr regmap: %ld\n",
1322 PTR_ERR(dspi->regmap_pushr));
1323 ret = PTR_ERR(dspi->regmap_pushr);
1324 goto out_ctlr_put;
1325 }
1326 }
1327
1328 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1329 if (IS_ERR(dspi->clk)) {
1330 ret = PTR_ERR(dspi->clk);
1331 dev_err(&pdev->dev, "unable to get clock\n");
1332 goto out_ctlr_put;
1333 }
1334 ret = clk_prepare_enable(dspi->clk);
1335 if (ret)
1336 goto out_ctlr_put;
1337
1338 ret = dspi_init(dspi);
1339 if (ret)
1340 goto out_clk_put;
1341
1342 dspi->irq = platform_get_irq(pdev, 0);
1343 if (dspi->irq <= 0) {
1344 dev_info(&pdev->dev,
1345 "can't get platform irq, using poll mode\n");
1346 dspi->irq = 0;
1347 goto poll_mode;
1348 }
1349
1350 init_completion(&dspi->xfer_done);
1351
1352 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1353 IRQF_SHARED, pdev->name, dspi);
1354 if (ret < 0) {
1355 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1356 goto out_clk_put;
1357 }
1358
1359 poll_mode:
1360
1361 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1362 ret = dspi_request_dma(dspi, res->start);
1363 if (ret < 0) {
1364 dev_err(&pdev->dev, "can't get dma channels\n");
1365 goto out_free_irq;
1366 }
1367 }
1368
1369 ctlr->max_speed_hz =
1370 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1371
1372 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1373 ctlr->ptp_sts_supported = true;
1374
1375 ret = spi_register_controller(ctlr);
1376 if (ret != 0) {
1377 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1378 goto out_free_irq;
1379 }
1380
1381 return ret;
1382
1383 out_free_irq:
1384 if (dspi->irq)
1385 free_irq(dspi->irq, dspi);
1386 out_clk_put:
1387 clk_disable_unprepare(dspi->clk);
1388 out_ctlr_put:
1389 spi_controller_put(ctlr);
1390
1391 return ret;
1392 }
1393
1394 static int dspi_remove(struct platform_device *pdev)
1395 {
1396 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1397
1398 /* Disconnect from the SPI framework */
1399 spi_unregister_controller(dspi->ctlr);
1400
1401 /* Disable RX and TX */
1402 regmap_update_bits(dspi->regmap, SPI_MCR,
1403 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1404 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1405
1406 /* Stop Running */
1407 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1408
1409 dspi_release_dma(dspi);
1410 if (dspi->irq)
1411 free_irq(dspi->irq, dspi);
1412 clk_disable_unprepare(dspi->clk);
1413
1414 return 0;
1415 }
1416
1417 static void dspi_shutdown(struct platform_device *pdev)
1418 {
1419 dspi_remove(pdev);
1420 }
1421
1422 static struct platform_driver fsl_dspi_driver = {
1423 .driver.name = DRIVER_NAME,
1424 .driver.of_match_table = fsl_dspi_dt_ids,
1425 .driver.owner = THIS_MODULE,
1426 .driver.pm = &dspi_pm,
1427 .probe = dspi_probe,
1428 .remove = dspi_remove,
1429 .shutdown = dspi_shutdown,
1430 };
1431 module_platform_driver(fsl_dspi_driver);
1432
1433 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1434 MODULE_LICENSE("GPL");
1435 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support