?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
LiteX: driver for MMCM
[linux/fpc-iii.git] / drivers / spi / spi-nxp-fspi.c
blobab9035662717a3b0464bdefb6bb3ca4d10376401
1 // SPDX-License-Identifier: GPL-2.0+
2
3 /*
4 * NXP FlexSPI(FSPI) controller driver.
5 *
6 * Copyright 2019-2020 NXP
7 * Copyright 2020 Puresoftware Ltd.
8 *
9 * FlexSPI is a flexsible SPI host controller which supports two SPI
10 * channels and up to 4 external devices. Each channel supports
11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
12 * data lines).
13 *
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
16 * A valid sequence consists of four LUT registers.
17 * Maximum 32 LUT sequences can be programmed simultaneously.
18 *
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
21 *
22 * Software triggered Flash read/write access by IP Bus.
23 *
24 * Memory mapped read access by AHB Bus.
25 *
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
27 *
28 * Author:
29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
30 * Boris Brezillon <bbrezillon@kernel.org>
31 * Frieder Schrempf <frieder.schrempf@kontron.de>
32 */
33
34 #include <linux/acpi.h>
35 #include <linux/bitops.h>
36 #include <linux/clk.h>
37 #include <linux/completion.h>
38 #include <linux/delay.h>
39 #include <linux/err.h>
40 #include <linux/errno.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43 #include <linux/iopoll.h>
44 #include <linux/jiffies.h>
45 #include <linux/kernel.h>
46 #include <linux/module.h>
47 #include <linux/mutex.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/platform_device.h>
51 #include <linux/pm_qos.h>
52 #include <linux/sizes.h>
53
54 #include <linux/spi/spi.h>
55 #include <linux/spi/spi-mem.h>
56
57 /*
58 * The driver only uses one single LUT entry, that is updated on
59 * each call of exec_op(). Index 0 is preset at boot with a basic
60 * read operation, so let's use the last entry (31).
61 */
62 #define SEQID_LUT 31
63
64 /* Registers used by the driver */
65 #define FSPI_MCR0 0x00
66 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
67 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
68 #define FSPI_MCR0_LEARN_EN BIT(15)
69 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
70 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
71 #define FSPI_MCR0_DOZE_EN BIT(12)
72 #define FSPI_MCR0_HSEN BIT(11)
73 #define FSPI_MCR0_SERCLKDIV BIT(8)
74 #define FSPI_MCR0_ATDF_EN BIT(7)
75 #define FSPI_MCR0_ARDF_EN BIT(6)
76 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
77 #define FSPI_MCR0_END_CFG(x) ((x) << 2)
78 #define FSPI_MCR0_MDIS BIT(1)
79 #define FSPI_MCR0_SWRST BIT(0)
80
81 #define FSPI_MCR1 0x04
82 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
83 #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
84
85 #define FSPI_MCR2 0x08
86 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
87 #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
88 #define FSPI_MCR2_CLRLRPHS BIT(14)
89 #define FSPI_MCR2_ABRDATSZ BIT(8)
90 #define FSPI_MCR2_ABRLEARN BIT(7)
91 #define FSPI_MCR2_ABR_READ BIT(6)
92 #define FSPI_MCR2_ABRWRITE BIT(5)
93 #define FSPI_MCR2_ABRDUMMY BIT(4)
94 #define FSPI_MCR2_ABR_MODE BIT(3)
95 #define FSPI_MCR2_ABRCADDR BIT(2)
96 #define FSPI_MCR2_ABRRADDR BIT(1)
97 #define FSPI_MCR2_ABR_CMD BIT(0)
98
99 #define FSPI_AHBCR 0x0c
100 #define FSPI_AHBCR_RDADDROPT BIT(6)
101 #define FSPI_AHBCR_PREF_EN BIT(5)
102 #define FSPI_AHBCR_BUFF_EN BIT(4)
103 #define FSPI_AHBCR_CACH_EN BIT(3)
104 #define FSPI_AHBCR_CLRTXBUF BIT(2)
105 #define FSPI_AHBCR_CLRRXBUF BIT(1)
106 #define FSPI_AHBCR_PAR_EN BIT(0)
107
108 #define FSPI_INTEN 0x10
109 #define FSPI_INTEN_SCLKSBWR BIT(9)
110 #define FSPI_INTEN_SCLKSBRD BIT(8)
111 #define FSPI_INTEN_DATALRNFL BIT(7)
112 #define FSPI_INTEN_IPTXWE BIT(6)
113 #define FSPI_INTEN_IPRXWA BIT(5)
114 #define FSPI_INTEN_AHBCMDERR BIT(4)
115 #define FSPI_INTEN_IPCMDERR BIT(3)
116 #define FSPI_INTEN_AHBCMDGE BIT(2)
117 #define FSPI_INTEN_IPCMDGE BIT(1)
118 #define FSPI_INTEN_IPCMDDONE BIT(0)
119
120 #define FSPI_INTR 0x14
121 #define FSPI_INTR_SCLKSBWR BIT(9)
122 #define FSPI_INTR_SCLKSBRD BIT(8)
123 #define FSPI_INTR_DATALRNFL BIT(7)
124 #define FSPI_INTR_IPTXWE BIT(6)
125 #define FSPI_INTR_IPRXWA BIT(5)
126 #define FSPI_INTR_AHBCMDERR BIT(4)
127 #define FSPI_INTR_IPCMDERR BIT(3)
128 #define FSPI_INTR_AHBCMDGE BIT(2)
129 #define FSPI_INTR_IPCMDGE BIT(1)
130 #define FSPI_INTR_IPCMDDONE BIT(0)
131
132 #define FSPI_LUTKEY 0x18
133 #define FSPI_LUTKEY_VALUE 0x5AF05AF0
134
135 #define FSPI_LCKCR 0x1C
136
137 #define FSPI_LCKER_LOCK 0x1
138 #define FSPI_LCKER_UNLOCK 0x2
139
140 #define FSPI_BUFXCR_INVALID_MSTRID 0xE
141 #define FSPI_AHBRX_BUF0CR0 0x20
142 #define FSPI_AHBRX_BUF1CR0 0x24
143 #define FSPI_AHBRX_BUF2CR0 0x28
144 #define FSPI_AHBRX_BUF3CR0 0x2C
145 #define FSPI_AHBRX_BUF4CR0 0x30
146 #define FSPI_AHBRX_BUF5CR0 0x34
147 #define FSPI_AHBRX_BUF6CR0 0x38
148 #define FSPI_AHBRX_BUF7CR0 0x3C
149 #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
150
151 #define FSPI_AHBRX_BUF0CR1 0x40
152 #define FSPI_AHBRX_BUF1CR1 0x44
153 #define FSPI_AHBRX_BUF2CR1 0x48
154 #define FSPI_AHBRX_BUF3CR1 0x4C
155 #define FSPI_AHBRX_BUF4CR1 0x50
156 #define FSPI_AHBRX_BUF5CR1 0x54
157 #define FSPI_AHBRX_BUF6CR1 0x58
158 #define FSPI_AHBRX_BUF7CR1 0x5C
159
160 #define FSPI_FLSHA1CR0 0x60
161 #define FSPI_FLSHA2CR0 0x64
162 #define FSPI_FLSHB1CR0 0x68
163 #define FSPI_FLSHB2CR0 0x6C
164 #define FSPI_FLSHXCR0_SZ_KB 10
165 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
166
167 #define FSPI_FLSHA1CR1 0x70
168 #define FSPI_FLSHA2CR1 0x74
169 #define FSPI_FLSHB1CR1 0x78
170 #define FSPI_FLSHB2CR1 0x7C
171 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
172 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
173 #define FSPI_FLSHXCR1_WA BIT(10)
174 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
175 #define FSPI_FLSHXCR1_TCSS(x) (x)
176
177 #define FSPI_FLSHA1CR2 0x80
178 #define FSPI_FLSHA2CR2 0x84
179 #define FSPI_FLSHB1CR2 0x88
180 #define FSPI_FLSHB2CR2 0x8C
181 #define FSPI_FLSHXCR2_CLRINSP BIT(24)
182 #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
183 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
184 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
185 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
186 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
187
188 #define FSPI_IPCR0 0xA0
189
190 #define FSPI_IPCR1 0xA4
191 #define FSPI_IPCR1_IPAREN BIT(31)
192 #define FSPI_IPCR1_SEQNUM_SHIFT 24
193 #define FSPI_IPCR1_SEQID_SHIFT 16
194 #define FSPI_IPCR1_IDATSZ(x) (x)
195
196 #define FSPI_IPCMD 0xB0
197 #define FSPI_IPCMD_TRG BIT(0)
198
199 #define FSPI_DLPR 0xB4
200
201 #define FSPI_IPRXFCR 0xB8
202 #define FSPI_IPRXFCR_CLR BIT(0)
203 #define FSPI_IPRXFCR_DMA_EN BIT(1)
204 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
205
206 #define FSPI_IPTXFCR 0xBC
207 #define FSPI_IPTXFCR_CLR BIT(0)
208 #define FSPI_IPTXFCR_DMA_EN BIT(1)
209 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
210
211 #define FSPI_DLLACR 0xC0
212 #define FSPI_DLLACR_OVRDEN BIT(8)
213
214 #define FSPI_DLLBCR 0xC4
215 #define FSPI_DLLBCR_OVRDEN BIT(8)
216
217 #define FSPI_STS0 0xE0
218 #define FSPI_STS0_DLPHB(x) ((x) << 8)
219 #define FSPI_STS0_DLPHA(x) ((x) << 4)
220 #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
221 #define FSPI_STS0_ARB_IDLE BIT(1)
222 #define FSPI_STS0_SEQ_IDLE BIT(0)
223
224 #define FSPI_STS1 0xE4
225 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
226 #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
227 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
228 #define FSPI_STS1_AHB_ERRID(x) (x)
229
230 #define FSPI_AHBSPNST 0xEC
231 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
232 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
233 #define FSPI_AHBSPNST_ACTIVE BIT(0)
234
235 #define FSPI_IPRXFSTS 0xF0
236 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
237 #define FSPI_IPRXFSTS_FILL(x) (x)
238
239 #define FSPI_IPTXFSTS 0xF4
240 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
241 #define FSPI_IPTXFSTS_FILL(x) (x)
242
243 #define FSPI_RFDR 0x100
244 #define FSPI_TFDR 0x180
245
246 #define FSPI_LUT_BASE 0x200
247 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
248 #define FSPI_LUT_REG(idx) \
249 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
250
251 /* register map end */
252
253 /* Instruction set for the LUT register. */
254 #define LUT_STOP 0x00
255 #define LUT_CMD 0x01
256 #define LUT_ADDR 0x02
257 #define LUT_CADDR_SDR 0x03
258 #define LUT_MODE 0x04
259 #define LUT_MODE2 0x05
260 #define LUT_MODE4 0x06
261 #define LUT_MODE8 0x07
262 #define LUT_NXP_WRITE 0x08
263 #define LUT_NXP_READ 0x09
264 #define LUT_LEARN_SDR 0x0A
265 #define LUT_DATSZ_SDR 0x0B
266 #define LUT_DUMMY 0x0C
267 #define LUT_DUMMY_RWDS_SDR 0x0D
268 #define LUT_JMP_ON_CS 0x1F
269 #define LUT_CMD_DDR 0x21
270 #define LUT_ADDR_DDR 0x22
271 #define LUT_CADDR_DDR 0x23
272 #define LUT_MODE_DDR 0x24
273 #define LUT_MODE2_DDR 0x25
274 #define LUT_MODE4_DDR 0x26
275 #define LUT_MODE8_DDR 0x27
276 #define LUT_WRITE_DDR 0x28
277 #define LUT_READ_DDR 0x29
278 #define LUT_LEARN_DDR 0x2A
279 #define LUT_DATSZ_DDR 0x2B
280 #define LUT_DUMMY_DDR 0x2C
281 #define LUT_DUMMY_RWDS_DDR 0x2D
282
283 /*
284 * Calculate number of required PAD bits for LUT register.
285 *
286 * The pad stands for the number of IO lines [0:7].
287 * For example, the octal read needs eight IO lines,
288 * so you should use LUT_PAD(8). This macro
289 * returns 3 i.e. use eight (2^3) IP lines for read.
290 */
291 #define LUT_PAD(x) (fls(x) - 1)
292
293 /*
294 * Macro for constructing the LUT entries with the following
295 * register layout:
296 *
297 * ---------------------------------------------------
298 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
299 * ---------------------------------------------------
300 */
301 #define PAD_SHIFT 8
302 #define INSTR_SHIFT 10
303 #define OPRND_SHIFT 16
304
305 /* Macros for constructing the LUT register. */
306 #define LUT_DEF(idx, ins, pad, opr) \
307 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
308 (opr)) << (((idx) % 2) * OPRND_SHIFT))
309
310 #define POLL_TOUT 5000
311 #define NXP_FSPI_MAX_CHIPSELECT 4
312 #define NXP_FSPI_MIN_IOMAP SZ_4M
313
314 struct nxp_fspi_devtype_data {
315 unsigned int rxfifo;
316 unsigned int txfifo;
317 unsigned int ahb_buf_size;
318 unsigned int quirks;
319 bool little_endian;
320 };
321
322 static const struct nxp_fspi_devtype_data lx2160a_data = {
323 .rxfifo = SZ_512, /* (64 * 64 bits) */
324 .txfifo = SZ_1K, /* (128 * 64 bits) */
325 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
326 .quirks = 0,
327 .little_endian = true, /* little-endian */
328 };
329
330 static const struct nxp_fspi_devtype_data imx8mm_data = {
331 .rxfifo = SZ_512, /* (64 * 64 bits) */
332 .txfifo = SZ_1K, /* (128 * 64 bits) */
333 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
334 .quirks = 0,
335 .little_endian = true, /* little-endian */
336 };
337
338 static const struct nxp_fspi_devtype_data imx8qxp_data = {
339 .rxfifo = SZ_512, /* (64 * 64 bits) */
340 .txfifo = SZ_1K, /* (128 * 64 bits) */
341 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
342 .quirks = 0,
343 .little_endian = true, /* little-endian */
344 };
345
346 struct nxp_fspi {
347 void __iomem *iobase;
348 void __iomem *ahb_addr;
349 u32 memmap_phy;
350 u32 memmap_phy_size;
351 u32 memmap_start;
352 u32 memmap_len;
353 struct clk *clk, *clk_en;
354 struct device *dev;
355 struct completion c;
356 const struct nxp_fspi_devtype_data *devtype_data;
357 struct mutex lock;
358 struct pm_qos_request pm_qos_req;
359 int selected;
360 };
361
362 /*
363 * R/W functions for big- or little-endian registers:
364 * The FSPI controller's endianness is independent of
365 * the CPU core's endianness. So far, although the CPU
366 * core is little-endian the FSPI controller can use
367 * big-endian or little-endian.
368 */
369 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
370 {
371 if (f->devtype_data->little_endian)
372 iowrite32(val, addr);
373 else
374 iowrite32be(val, addr);
375 }
376
377 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
378 {
379 if (f->devtype_data->little_endian)
380 return ioread32(addr);
381 else
382 return ioread32be(addr);
383 }
384
385 static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
386 {
387 struct nxp_fspi *f = dev_id;
388 u32 reg;
389
390 /* clear interrupt */
391 reg = fspi_readl(f, f->iobase + FSPI_INTR);
392 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR);
393
394 if (reg & FSPI_INTR_IPCMDDONE)
395 complete(&f->c);
396
397 return IRQ_HANDLED;
398 }
399
400 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
401 {
402 switch (width) {
403 case 1:
404 case 2:
405 case 4:
406 case 8:
407 return 0;
408 }
409
410 return -ENOTSUPP;
411 }
412
413 static bool nxp_fspi_supports_op(struct spi_mem *mem,
414 const struct spi_mem_op *op)
415 {
416 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
417 int ret;
418
419 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
420
421 if (op->addr.nbytes)
422 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
423
424 if (op->dummy.nbytes)
425 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
426
427 if (op->data.nbytes)
428 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
429
430 if (ret)
431 return false;
432
433 /*
434 * The number of address bytes should be equal to or less than 4 bytes.
435 */
436 if (op->addr.nbytes > 4)
437 return false;
438
439 /*
440 * If requested address value is greater than controller assigned
441 * memory mapped space, return error as it didn't fit in the range
442 * of assigned address space.
443 */
444 if (op->addr.val >= f->memmap_phy_size)
445 return false;
446
447 /* Max 64 dummy clock cycles supported */
448 if (op->dummy.buswidth &&
449 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
450 return false;
451
452 /* Max data length, check controller limits and alignment */
453 if (op->data.dir == SPI_MEM_DATA_IN &&
454 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
455 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
456 !IS_ALIGNED(op->data.nbytes, 8))))
457 return false;
458
459 if (op->data.dir == SPI_MEM_DATA_OUT &&
460 op->data.nbytes > f->devtype_data->txfifo)
461 return false;
462
463 return spi_mem_default_supports_op(mem, op);
464 }
465
466 /* Instead of busy looping invoke readl_poll_timeout functionality. */
467 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
468 u32 mask, u32 delay_us,
469 u32 timeout_us, bool c)
470 {
471 u32 reg;
472
473 if (!f->devtype_data->little_endian)
474 mask = (u32)cpu_to_be32(mask);
475
476 if (c)
477 return readl_poll_timeout(base, reg, (reg & mask),
478 delay_us, timeout_us);
479 else
480 return readl_poll_timeout(base, reg, !(reg & mask),
481 delay_us, timeout_us);
482 }
483
484 /*
485 * If the slave device content being changed by Write/Erase, need to
486 * invalidate the AHB buffer. This can be achieved by doing the reset
487 * of controller after setting MCR0[SWRESET] bit.
488 */
489 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
490 {
491 u32 reg;
492 int ret;
493
494 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
495 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
496
497 /* w1c register, wait unit clear */
498 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
499 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
500 WARN_ON(ret);
501 }
502
503 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
504 const struct spi_mem_op *op)
505 {
506 void __iomem *base = f->iobase;
507 u32 lutval[4] = {};
508 int lutidx = 1, i;
509
510 /* cmd */
511 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
512 op->cmd.opcode);
513
514 /* addr bytes */
515 if (op->addr.nbytes) {
516 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
517 LUT_PAD(op->addr.buswidth),
518 op->addr.nbytes * 8);
519 lutidx++;
520 }
521
522 /* dummy bytes, if needed */
523 if (op->dummy.nbytes) {
524 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
525 /*
526 * Due to FlexSPI controller limitation number of PAD for dummy
527 * buswidth needs to be programmed as equal to data buswidth.
528 */
529 LUT_PAD(op->data.buswidth),
530 op->dummy.nbytes * 8 /
531 op->dummy.buswidth);
532 lutidx++;
533 }
534
535 /* read/write data bytes */
536 if (op->data.nbytes) {
537 lutval[lutidx / 2] |= LUT_DEF(lutidx,
538 op->data.dir == SPI_MEM_DATA_IN ?
539 LUT_NXP_READ : LUT_NXP_WRITE,
540 LUT_PAD(op->data.buswidth),
541 0);
542 lutidx++;
543 }
544
545 /* stop condition. */
546 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
547
548 /* unlock LUT */
549 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
550 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
551
552 /* fill LUT */
553 for (i = 0; i < ARRAY_SIZE(lutval); i++)
554 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
555
556 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
557 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
558
559 /* lock LUT */
560 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
561 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
562 }
563
564 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
565 {
566 int ret;
567
568 if (is_acpi_node(f->dev->fwnode))
569 return 0;
570
571 ret = clk_prepare_enable(f->clk_en);
572 if (ret)
573 return ret;
574
575 ret = clk_prepare_enable(f->clk);
576 if (ret) {
577 clk_disable_unprepare(f->clk_en);
578 return ret;
579 }
580
581 return 0;
582 }
583
584 static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
585 {
586 if (is_acpi_node(f->dev->fwnode))
587 return 0;
588
589 clk_disable_unprepare(f->clk);
590 clk_disable_unprepare(f->clk_en);
591
592 return 0;
593 }
594
595 /*
596 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
597 * register and start base address of the slave device.
598 *
599 * (Higher address)
600 * -------- <-- FLSHB2CR0
601 * | B2 |
602 * | |
603 * B2 start address --> -------- <-- FLSHB1CR0
604 * | B1 |
605 * | |
606 * B1 start address --> -------- <-- FLSHA2CR0
607 * | A2 |
608 * | |
609 * A2 start address --> -------- <-- FLSHA1CR0
610 * | A1 |
611 * | |
612 * A1 start address --> -------- (Lower address)
613 *
614 *
615 * Start base address defines the starting address range for given CS and
616 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
617 *
618 * But, different targets are having different combinations of number of CS,
619 * some targets only have single CS or two CS covering controller's full
620 * memory mapped space area.
621 * Thus, implementation is being done as independent of the size and number
622 * of the connected slave device.
623 * Assign controller memory mapped space size as the size to the connected
624 * slave device.
625 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
626 * chip-select Flash configuration register.
627 *
628 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
629 * memory mapped size of the controller.
630 * Value for rest of the CS FLSHxxCR0 register would be zero.
631 *
632 */
633 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
634 {
635 unsigned long rate = spi->max_speed_hz;
636 int ret;
637 uint64_t size_kb;
638
639 /*
640 * Return, if previously selected slave device is same as current
641 * requested slave device.
642 */
643 if (f->selected == spi->chip_select)
644 return;
645
646 /* Reset FLSHxxCR0 registers */
647 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
648 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
649 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
650 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
651
652 /* Assign controller memory mapped space as size, KBytes, of flash. */
653 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
654
655 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
656 4 * spi->chip_select);
657
658 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select);
659
660 nxp_fspi_clk_disable_unprep(f);
661
662 ret = clk_set_rate(f->clk, rate);
663 if (ret)
664 return;
665
666 ret = nxp_fspi_clk_prep_enable(f);
667 if (ret)
668 return;
669
670 f->selected = spi->chip_select;
671 }
672
673 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
674 {
675 u32 start = op->addr.val;
676 u32 len = op->data.nbytes;
677
678 /* if necessary, ioremap before AHB read */
679 if ((!f->ahb_addr) || start < f->memmap_start ||
680 start + len > f->memmap_start + f->memmap_len) {
681 if (f->ahb_addr)
682 iounmap(f->ahb_addr);
683
684 f->memmap_start = start;
685 f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
686 len : NXP_FSPI_MIN_IOMAP;
687
688 f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
689 f->memmap_len);
690
691 if (!f->ahb_addr) {
692 dev_err(f->dev, "failed to alloc memory\n");
693 return -ENOMEM;
694 }
695 }
696
697 /* Read out the data directly from the AHB buffer. */
698 memcpy_fromio(op->data.buf.in,
699 f->ahb_addr + start - f->memmap_start, len);
700
701 return 0;
702 }
703
704 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
705 const struct spi_mem_op *op)
706 {
707 void __iomem *base = f->iobase;
708 int i, ret;
709 u8 *buf = (u8 *) op->data.buf.out;
710
711 /* clear the TX FIFO. */
712 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
713
714 /*
715 * Default value of water mark level is 8 bytes, hence in single
716 * write request controller can write max 8 bytes of data.
717 */
718
719 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
720 /* Wait for TXFIFO empty */
721 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
722 FSPI_INTR_IPTXWE, 0,
723 POLL_TOUT, true);
724 WARN_ON(ret);
725
726 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR);
727 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4);
728 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
729 }
730
731 if (i < op->data.nbytes) {
732 u32 data = 0;
733 int j;
734 /* Wait for TXFIFO empty */
735 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
736 FSPI_INTR_IPTXWE, 0,
737 POLL_TOUT, true);
738 WARN_ON(ret);
739
740 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
741 memcpy(&data, buf + i + j, 4);
742 fspi_writel(f, data, base + FSPI_TFDR + j);
743 }
744 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
745 }
746 }
747
748 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
749 const struct spi_mem_op *op)
750 {
751 void __iomem *base = f->iobase;
752 int i, ret;
753 int len = op->data.nbytes;
754 u8 *buf = (u8 *) op->data.buf.in;
755
756 /*
757 * Default value of water mark level is 8 bytes, hence in single
758 * read request controller can read max 8 bytes of data.
759 */
760 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
761 /* Wait for RXFIFO available */
762 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
763 FSPI_INTR_IPRXWA, 0,
764 POLL_TOUT, true);
765 WARN_ON(ret);
766
767 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
768 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
769 /* move the FIFO pointer */
770 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
771 }
772
773 if (i < len) {
774 u32 tmp;
775 int size, j;
776
777 buf = op->data.buf.in + i;
778 /* Wait for RXFIFO available */
779 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
780 FSPI_INTR_IPRXWA, 0,
781 POLL_TOUT, true);
782 WARN_ON(ret);
783
784 len = op->data.nbytes - i;
785 for (j = 0; j < op->data.nbytes - i; j += 4) {
786 tmp = fspi_readl(f, base + FSPI_RFDR + j);
787 size = min(len, 4);
788 memcpy(buf + j, &tmp, size);
789 len -= size;
790 }
791 }
792
793 /* invalid the RXFIFO */
794 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
795 /* move the FIFO pointer */
796 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
797 }
798
799 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
800 {
801 void __iomem *base = f->iobase;
802 int seqnum = 0;
803 int err = 0;
804 u32 reg;
805
806 reg = fspi_readl(f, base + FSPI_IPRXFCR);
807 /* invalid RXFIFO first */
808 reg &= ~FSPI_IPRXFCR_DMA_EN;
809 reg = reg | FSPI_IPRXFCR_CLR;
810 fspi_writel(f, reg, base + FSPI_IPRXFCR);
811
812 init_completion(&f->c);
813
814 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
815 /*
816 * Always start the sequence at the same index since we update
817 * the LUT at each exec_op() call. And also specify the DATA
818 * length, since it's has not been specified in the LUT.
819 */
820 fspi_writel(f, op->data.nbytes |
821 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
822 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
823 base + FSPI_IPCR1);
824
825 /* Trigger the LUT now. */
826 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
827
828 /* Wait for the interrupt. */
829 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000)))
830 err = -ETIMEDOUT;
831
832 /* Invoke IP data read, if request is of data read. */
833 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
834 nxp_fspi_read_rxfifo(f, op);
835
836 return err;
837 }
838
839 static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
840 {
841 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
842 int err = 0;
843
844 mutex_lock(&f->lock);
845
846 /* Wait for controller being ready. */
847 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
848 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
849 WARN_ON(err);
850
851 nxp_fspi_select_mem(f, mem->spi);
852
853 nxp_fspi_prepare_lut(f, op);
854 /*
855 * If we have large chunks of data, we read them through the AHB bus
856 * by accessing the mapped memory. In all other cases we use
857 * IP commands to access the flash.
858 */
859 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
860 op->data.dir == SPI_MEM_DATA_IN) {
861 err = nxp_fspi_read_ahb(f, op);
862 } else {
863 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
864 nxp_fspi_fill_txfifo(f, op);
865
866 err = nxp_fspi_do_op(f, op);
867 }
868
869 /* Invalidate the data in the AHB buffer. */
870 nxp_fspi_invalid(f);
871
872 mutex_unlock(&f->lock);
873
874 return err;
875 }
876
877 static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
878 {
879 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
880
881 if (op->data.dir == SPI_MEM_DATA_OUT) {
882 if (op->data.nbytes > f->devtype_data->txfifo)
883 op->data.nbytes = f->devtype_data->txfifo;
884 } else {
885 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
886 op->data.nbytes = f->devtype_data->ahb_buf_size;
887 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
888 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
889 }
890
891 return 0;
892 }
893
894 static int nxp_fspi_default_setup(struct nxp_fspi *f)
895 {
896 void __iomem *base = f->iobase;
897 int ret, i;
898 u32 reg;
899
900 /* disable and unprepare clock to avoid glitch pass to controller */
901 nxp_fspi_clk_disable_unprep(f);
902
903 /* the default frequency, we will change it later if necessary. */
904 ret = clk_set_rate(f->clk, 20000000);
905 if (ret)
906 return ret;
907
908 ret = nxp_fspi_clk_prep_enable(f);
909 if (ret)
910 return ret;
911
912 /* Reset the module */
913 /* w1c register, wait unit clear */
914 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
915 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
916 WARN_ON(ret);
917
918 /* Disable the module */
919 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
920
921 /* Reset the DLL register to default value */
922 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
923 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
924
925 /* enable module */
926 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
927 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
928 base + FSPI_MCR0);
929
930 /*
931 * Disable same device enable bit and configure all slave devices
932 * independently.
933 */
934 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
935 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
936 fspi_writel(f, reg, base + FSPI_MCR2);
937
938 /* AHB configuration for access buffer 0~7. */
939 for (i = 0; i < 7; i++)
940 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
941
942 /*
943 * Set ADATSZ with the maximum AHB buffer size to improve the read
944 * performance.
945 */
946 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
947 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
948
949 /* prefetch and no start address alignment limitation */
950 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
951 base + FSPI_AHBCR);
952
953 /* AHB Read - Set lut sequence ID for all CS. */
954 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
955 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
956 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
957 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
958
959 f->selected = -1;
960
961 /* enable the interrupt */
962 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN);
963
964 return 0;
965 }
966
967 static const char *nxp_fspi_get_name(struct spi_mem *mem)
968 {
969 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
970 struct device *dev = &mem->spi->dev;
971 const char *name;
972
973 // Set custom name derived from the platform_device of the controller.
974 if (of_get_available_child_count(f->dev->of_node) == 1)
975 return dev_name(f->dev);
976
977 name = devm_kasprintf(dev, GFP_KERNEL,
978 "%s-%d", dev_name(f->dev),
979 mem->spi->chip_select);
980
981 if (!name) {
982 dev_err(dev, "failed to get memory for custom flash name\n");
983 return ERR_PTR(-ENOMEM);
984 }
985
986 return name;
987 }
988
989 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
990 .adjust_op_size = nxp_fspi_adjust_op_size,
991 .supports_op = nxp_fspi_supports_op,
992 .exec_op = nxp_fspi_exec_op,
993 .get_name = nxp_fspi_get_name,
994 };
995
996 static int nxp_fspi_probe(struct platform_device *pdev)
997 {
998 struct spi_controller *ctlr;
999 struct device *dev = &pdev->dev;
1000 struct device_node *np = dev->of_node;
1001 struct resource *res;
1002 struct nxp_fspi *f;
1003 int ret;
1004 u32 reg;
1005
1006 ctlr = spi_alloc_master(&pdev->dev, sizeof(*f));
1007 if (!ctlr)
1008 return -ENOMEM;
1009
1010 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
1011 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
1012
1013 f = spi_controller_get_devdata(ctlr);
1014 f->dev = dev;
1015 f->devtype_data = device_get_match_data(dev);
1016 if (!f->devtype_data) {
1017 ret = -ENODEV;
1018 goto err_put_ctrl;
1019 }
1020
1021 platform_set_drvdata(pdev, f);
1022
1023 /* find the resources - configuration register address space */
1024 if (is_acpi_node(f->dev->fwnode))
1025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026 else
1027 res = platform_get_resource_byname(pdev,
1028 IORESOURCE_MEM, "fspi_base");
1029
1030 f->iobase = devm_ioremap_resource(dev, res);
1031 if (IS_ERR(f->iobase)) {
1032 ret = PTR_ERR(f->iobase);
1033 goto err_put_ctrl;
1034 }
1035
1036 /* Clear potential interrupts */
1037 reg = fspi_readl(f, f->iobase + FSPI_INTR);
1038 if (reg)
1039 fspi_writel(f, reg, f->iobase + FSPI_INTR);
1040
1041
1042 /* find the resources - controller memory mapped space */
1043 if (is_acpi_node(f->dev->fwnode))
1044 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1045 else
1046 res = platform_get_resource_byname(pdev,
1047 IORESOURCE_MEM, "fspi_mmap");
1048
1049 if (!res) {
1050 ret = -ENODEV;
1051 goto err_put_ctrl;
1052 }
1053
1054 /* assign memory mapped starting address and mapped size. */
1055 f->memmap_phy = res->start;
1056 f->memmap_phy_size = resource_size(res);
1057
1058 /* find the clocks */
1059 if (dev_of_node(&pdev->dev)) {
1060 f->clk_en = devm_clk_get(dev, "fspi_en");
1061 if (IS_ERR(f->clk_en)) {
1062 ret = PTR_ERR(f->clk_en);
1063 goto err_put_ctrl;
1064 }
1065
1066 f->clk = devm_clk_get(dev, "fspi");
1067 if (IS_ERR(f->clk)) {
1068 ret = PTR_ERR(f->clk);
1069 goto err_put_ctrl;
1070 }
1071
1072 ret = nxp_fspi_clk_prep_enable(f);
1073 if (ret) {
1074 dev_err(dev, "can not enable the clock\n");
1075 goto err_put_ctrl;
1076 }
1077 }
1078
1079 /* find the irq */
1080 ret = platform_get_irq(pdev, 0);
1081 if (ret < 0)
1082 goto err_disable_clk;
1083
1084 ret = devm_request_irq(dev, ret,
1085 nxp_fspi_irq_handler, 0, pdev->name, f);
1086 if (ret) {
1087 dev_err(dev, "failed to request irq: %d\n", ret);
1088 goto err_disable_clk;
1089 }
1090
1091 mutex_init(&f->lock);
1092
1093 ctlr->bus_num = -1;
1094 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
1095 ctlr->mem_ops = &nxp_fspi_mem_ops;
1096
1097 nxp_fspi_default_setup(f);
1098
1099 ctlr->dev.of_node = np;
1100
1101 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1102 if (ret)
1103 goto err_destroy_mutex;
1104
1105 return 0;
1106
1107 err_destroy_mutex:
1108 mutex_destroy(&f->lock);
1109
1110 err_disable_clk:
1111 nxp_fspi_clk_disable_unprep(f);
1112
1113 err_put_ctrl:
1114 spi_controller_put(ctlr);
1115
1116 dev_err(dev, "NXP FSPI probe failed\n");
1117 return ret;
1118 }
1119
1120 static int nxp_fspi_remove(struct platform_device *pdev)
1121 {
1122 struct nxp_fspi *f = platform_get_drvdata(pdev);
1123
1124 /* disable the hardware */
1125 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
1126
1127 nxp_fspi_clk_disable_unprep(f);
1128
1129 mutex_destroy(&f->lock);
1130
1131 if (f->ahb_addr)
1132 iounmap(f->ahb_addr);
1133
1134 return 0;
1135 }
1136
1137 static int nxp_fspi_suspend(struct device *dev)
1138 {
1139 return 0;
1140 }
1141
1142 static int nxp_fspi_resume(struct device *dev)
1143 {
1144 struct nxp_fspi *f = dev_get_drvdata(dev);
1145
1146 nxp_fspi_default_setup(f);
1147
1148 return 0;
1149 }
1150
1151 static const struct of_device_id nxp_fspi_dt_ids[] = {
1152 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1153 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1154 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1155 { /* sentinel */ }
1156 };
1157 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
1158
1159 #ifdef CONFIG_ACPI
1160 static const struct acpi_device_id nxp_fspi_acpi_ids[] = {
1161 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, },
1162 {}
1163 };
1164 MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids);
1165 #endif
1166
1167 static const struct dev_pm_ops nxp_fspi_pm_ops = {
1168 .suspend = nxp_fspi_suspend,
1169 .resume = nxp_fspi_resume,
1170 };
1171
1172 static struct platform_driver nxp_fspi_driver = {
1173 .driver = {
1174 .name = "nxp-fspi",
1175 .of_match_table = nxp_fspi_dt_ids,
1176 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids),
1177 .pm = &nxp_fspi_pm_ops,
1178 },
1179 .probe = nxp_fspi_probe,
1180 .remove = nxp_fspi_remove,
1181 };
1182 module_platform_driver(nxp_fspi_driver);
1183
1184 MODULE_DESCRIPTION("NXP FSPI Controller Driver");
1185 MODULE_AUTHOR("NXP Semiconductor");
1186 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
1187 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
1188 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
1189 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support