drivers/pinctrl/pinctrl-tegra124.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra124 pinmux
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21
  22 #include "pinctrl-tegra.h"
  23
  24 /*
  25  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26  * These must match how the GPIO driver names/numbers its pins.
  27  */
  28 #define _GPIO(offset)                           (offset)
  29
  30 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  31 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  32 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  33 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  34 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  35 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  36 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  37 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  38 #define TEGRA_PIN_PB0                           _GPIO(8)
  39 #define TEGRA_PIN_PB1                           _GPIO(9)
  40 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  41 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  42 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  43 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  44 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  45 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  46 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  47 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  48 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  49 #define TEGRA_PIN_PC7                           _GPIO(23)
  50 #define TEGRA_PIN_PG0                           _GPIO(48)
  51 #define TEGRA_PIN_PG1                           _GPIO(49)
  52 #define TEGRA_PIN_PG2                           _GPIO(50)
  53 #define TEGRA_PIN_PG3                           _GPIO(51)
  54 #define TEGRA_PIN_PG4                           _GPIO(52)
  55 #define TEGRA_PIN_PG5                           _GPIO(53)
  56 #define TEGRA_PIN_PG6                           _GPIO(54)
  57 #define TEGRA_PIN_PG7                           _GPIO(55)
  58 #define TEGRA_PIN_PH0                           _GPIO(56)
  59 #define TEGRA_PIN_PH1                           _GPIO(57)
  60 #define TEGRA_PIN_PH2                           _GPIO(58)
  61 #define TEGRA_PIN_PH3                           _GPIO(59)
  62 #define TEGRA_PIN_PH4                           _GPIO(60)
  63 #define TEGRA_PIN_PH5                           _GPIO(61)
  64 #define TEGRA_PIN_PH6                           _GPIO(62)
  65 #define TEGRA_PIN_PH7                           _GPIO(63)
  66 #define TEGRA_PIN_PI0                           _GPIO(64)
  67 #define TEGRA_PIN_PI1                           _GPIO(65)
  68 #define TEGRA_PIN_PI2                           _GPIO(66)
  69 #define TEGRA_PIN_PI3                           _GPIO(67)
  70 #define TEGRA_PIN_PI4                           _GPIO(68)
  71 #define TEGRA_PIN_PI5                           _GPIO(69)
  72 #define TEGRA_PIN_PI6                           _GPIO(70)
  73 #define TEGRA_PIN_PI7                           _GPIO(71)
  74 #define TEGRA_PIN_PJ0                           _GPIO(72)
  75 #define TEGRA_PIN_PJ2                           _GPIO(74)
  76 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  77 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  78 #define TEGRA_PIN_PJ7                           _GPIO(79)
  79 #define TEGRA_PIN_PK0                           _GPIO(80)
  80 #define TEGRA_PIN_PK1                           _GPIO(81)
  81 #define TEGRA_PIN_PK2                           _GPIO(82)
  82 #define TEGRA_PIN_PK3                           _GPIO(83)
  83 #define TEGRA_PIN_PK4                           _GPIO(84)
  84 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  85 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  86 #define TEGRA_PIN_PK7                           _GPIO(87)
  87 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  88 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  89 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  90 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  91 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  92 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  93 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  94 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  95 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  96 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  97 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
  98 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
  99 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
 100 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
 101 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
 102 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
 103 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
 104 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
 105 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 106 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 107 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 108 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 109 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 110 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 111 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 112 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 113 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 114 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 115 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 116 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 117 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 118 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 119 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 120 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 121 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 122 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 123 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 124 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 125 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 126 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 127 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 128 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 129 #define TEGRA_PIN_KB_ROW11_PS3                  _GPIO(147)
 130 #define TEGRA_PIN_KB_ROW12_PS4                  _GPIO(148)
 131 #define TEGRA_PIN_KB_ROW13_PS5                  _GPIO(149)
 132 #define TEGRA_PIN_KB_ROW14_PS6                  _GPIO(150)
 133 #define TEGRA_PIN_KB_ROW15_PS7                  _GPIO(151)
 134 #define TEGRA_PIN_KB_ROW16_PT0                  _GPIO(152)
 135 #define TEGRA_PIN_KB_ROW17_PT1                  _GPIO(153)
 136 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 137 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 138 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 139 #define TEGRA_PIN_PU0                           _GPIO(160)
 140 #define TEGRA_PIN_PU1                           _GPIO(161)
 141 #define TEGRA_PIN_PU2                           _GPIO(162)
 142 #define TEGRA_PIN_PU3                           _GPIO(163)
 143 #define TEGRA_PIN_PU4                           _GPIO(164)
 144 #define TEGRA_PIN_PU5                           _GPIO(165)
 145 #define TEGRA_PIN_PU6                           _GPIO(166)
 146 #define TEGRA_PIN_PV0                           _GPIO(168)
 147 #define TEGRA_PIN_PV1                           _GPIO(169)
 148 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 149 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 150 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 151 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 152 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 153 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 154 #define TEGRA_PIN_DAP_MCLK1_PW4                 _GPIO(180)
 155 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 156 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 157 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 158 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 159 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 160 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 161 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 162 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 163 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 164 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 165 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 166 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 167 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 168 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 169 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 170 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 171 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 172 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 173 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 174 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 175 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 176 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 177 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 178 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 179 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 180 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 181 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 182 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 183 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 184 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 185 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 186 #define TEGRA_PIN_PBB0                          _GPIO(216)
 187 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 188 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 189 #define TEGRA_PIN_PBB3                          _GPIO(219)
 190 #define TEGRA_PIN_PBB4                          _GPIO(220)
 191 #define TEGRA_PIN_PBB5                          _GPIO(221)
 192 #define TEGRA_PIN_PBB6                          _GPIO(222)
 193 #define TEGRA_PIN_PBB7                          _GPIO(223)
 194 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 195 #define TEGRA_PIN_PCC1                          _GPIO(225)
 196 #define TEGRA_PIN_PCC2                          _GPIO(226)
 197 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 198 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 199 #define TEGRA_PIN_PEX_L0_RST_N_PDD1             _GPIO(233)
 200 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2          _GPIO(234)
 201 #define TEGRA_PIN_PEX_WAKE_N_PDD3               _GPIO(235)
 202 #define TEGRA_PIN_PEX_L1_RST_N_PDD5             _GPIO(237)
 203 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6          _GPIO(238)
 204 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 205 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 206 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2            _GPIO(242)
 207 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 208 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 209 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 210 #define TEGRA_PIN_DP_HPD_PFF0                   _GPIO(248)
 211 #define TEGRA_PIN_USB_VBUS_EN2_PFF1             _GPIO(249)
 212 #define TEGRA_PIN_PFF2                          _GPIO(250)
 213
 214 /* All non-GPIO pins follow */
 215 #define NUM_GPIOS       (TEGRA_PIN_PFF2 + 1)
 216 #define _PIN(offset)    (NUM_GPIOS + (offset))
 217
 218 /* Non-GPIO pins */
 219 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 220 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 221 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 222 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(3)
 223 #define TEGRA_PIN_RESET_OUT_N                   _PIN(4)
 224 #define TEGRA_PIN_OWR                           _PIN(5)
 225 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
 226 #define TEGRA_PIN_JTAG_RTCK                     _PIN(7)
 227
 228 static const struct pinctrl_pin_desc tegra124_pins[] = {
 229         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 230         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 231         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 232         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 233         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 234         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 235         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 236         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 237         PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
 238         PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
 239         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 240         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 241         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 242         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 243         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 244         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 245         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 246         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 247         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 248         PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
 249         PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
 250         PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
 251         PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
 252         PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
 253         PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
 254         PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
 255         PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
 256         PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
 257         PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
 258         PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
 259         PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
 260         PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
 261         PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
 262         PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
 263         PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
 264         PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
 265         PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
 266         PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
 267         PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
 268         PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
 269         PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
 270         PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
 271         PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
 272         PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
 273         PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
 274         PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
 275         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 276         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 277         PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
 278         PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
 279         PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
 280         PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
 281         PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
 282         PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
 283         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 284         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 285         PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
 286         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 287         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 288         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 289         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 290         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 291         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 292         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 293         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 294         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 295         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 296         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 297         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 298         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 299         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 300         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 301         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 302         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 303         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 304         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 305         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 306         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 307         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 308         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 309         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 310         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 311         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 312         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 313         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 314         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 315         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 316         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 317         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 318         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 319         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 320         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 321         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 322         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 323         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 324         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 325         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 326         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 327         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 328         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"),
 329         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"),
 330         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"),
 331         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"),
 332         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"),
 333         PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"),
 334         PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"),
 335         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 336         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 337         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 338         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 339         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 340         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 341         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 342         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 343         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 344         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 345         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 346         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 347         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 348         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 349         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 350         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 351         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 352         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 353         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 354         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 355         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 356         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 357         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 358         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 359         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 360         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 361         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 362         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 363         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 364         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 365         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 366         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 367         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 368         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 369         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 370         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 371         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 372         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 373         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 374         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 375         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 376         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 377         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 378         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 379         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 380         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 381         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 382         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 383         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 384         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 385         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 386         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 387         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 388         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 389         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 390         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 391         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 392         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 393         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 394         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 395         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 396         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 397         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 398         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
 399         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
 400         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
 401         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
 402         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
 403         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 404         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 405         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
 406         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 407         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 408         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 409         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 410         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 411         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 412         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 413         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 414         PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
 415         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
 416         PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
 417         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 418         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
 419         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
 420 };
 421
 422 static const unsigned clk_32k_out_pa0_pins[] = {
 423         TEGRA_PIN_CLK_32K_OUT_PA0,
 424 };
 425
 426 static const unsigned uart3_cts_n_pa1_pins[] = {
 427         TEGRA_PIN_UART3_CTS_N_PA1,
 428 };
 429
 430 static const unsigned dap2_fs_pa2_pins[] = {
 431         TEGRA_PIN_DAP2_FS_PA2,
 432 };
 433
 434 static const unsigned dap2_sclk_pa3_pins[] = {
 435         TEGRA_PIN_DAP2_SCLK_PA3,
 436 };
 437
 438 static const unsigned dap2_din_pa4_pins[] = {
 439         TEGRA_PIN_DAP2_DIN_PA4,
 440 };
 441
 442 static const unsigned dap2_dout_pa5_pins[] = {
 443         TEGRA_PIN_DAP2_DOUT_PA5,
 444 };
 445
 446 static const unsigned sdmmc3_clk_pa6_pins[] = {
 447         TEGRA_PIN_SDMMC3_CLK_PA6,
 448 };
 449
 450 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 451         TEGRA_PIN_SDMMC3_CMD_PA7,
 452 };
 453
 454 static const unsigned pb0_pins[] = {
 455         TEGRA_PIN_PB0,
 456 };
 457
 458 static const unsigned pb1_pins[] = {
 459         TEGRA_PIN_PB1,
 460 };
 461
 462 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 463         TEGRA_PIN_SDMMC3_DAT3_PB4,
 464 };
 465
 466 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 467         TEGRA_PIN_SDMMC3_DAT2_PB5,
 468 };
 469
 470 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 471         TEGRA_PIN_SDMMC3_DAT1_PB6,
 472 };
 473
 474 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 475         TEGRA_PIN_SDMMC3_DAT0_PB7,
 476 };
 477
 478 static const unsigned uart3_rts_n_pc0_pins[] = {
 479         TEGRA_PIN_UART3_RTS_N_PC0,
 480 };
 481
 482 static const unsigned uart2_txd_pc2_pins[] = {
 483         TEGRA_PIN_UART2_TXD_PC2,
 484 };
 485
 486 static const unsigned uart2_rxd_pc3_pins[] = {
 487         TEGRA_PIN_UART2_RXD_PC3,
 488 };
 489
 490 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 491         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 492 };
 493
 494 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 495         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 496 };
 497
 498 static const unsigned pc7_pins[] = {
 499         TEGRA_PIN_PC7,
 500 };
 501
 502 static const unsigned pg0_pins[] = {
 503         TEGRA_PIN_PG0,
 504 };
 505
 506 static const unsigned pg1_pins[] = {
 507         TEGRA_PIN_PG1,
 508 };
 509
 510 static const unsigned pg2_pins[] = {
 511         TEGRA_PIN_PG2,
 512 };
 513
 514 static const unsigned pg3_pins[] = {
 515         TEGRA_PIN_PG3,
 516 };
 517
 518 static const unsigned pg4_pins[] = {
 519         TEGRA_PIN_PG4,
 520 };
 521
 522 static const unsigned pg5_pins[] = {
 523         TEGRA_PIN_PG5,
 524 };
 525
 526 static const unsigned pg6_pins[] = {
 527         TEGRA_PIN_PG6,
 528 };
 529
 530 static const unsigned pg7_pins[] = {
 531         TEGRA_PIN_PG7,
 532 };
 533
 534 static const unsigned ph0_pins[] = {
 535         TEGRA_PIN_PH0,
 536 };
 537
 538 static const unsigned ph1_pins[] = {
 539         TEGRA_PIN_PH1,
 540 };
 541
 542 static const unsigned ph2_pins[] = {
 543         TEGRA_PIN_PH2,
 544 };
 545
 546 static const unsigned ph3_pins[] = {
 547         TEGRA_PIN_PH3,
 548 };
 549
 550 static const unsigned ph4_pins[] = {
 551         TEGRA_PIN_PH4,
 552 };
 553
 554 static const unsigned ph5_pins[] = {
 555         TEGRA_PIN_PH5,
 556 };
 557
 558 static const unsigned ph6_pins[] = {
 559         TEGRA_PIN_PH6,
 560 };
 561
 562 static const unsigned ph7_pins[] = {
 563         TEGRA_PIN_PH7,
 564 };
 565
 566 static const unsigned pi0_pins[] = {
 567         TEGRA_PIN_PI0,
 568 };
 569
 570 static const unsigned pi1_pins[] = {
 571         TEGRA_PIN_PI1,
 572 };
 573
 574 static const unsigned pi2_pins[] = {
 575         TEGRA_PIN_PI2,
 576 };
 577
 578 static const unsigned pi3_pins[] = {
 579         TEGRA_PIN_PI3,
 580 };
 581
 582 static const unsigned pi4_pins[] = {
 583         TEGRA_PIN_PI4,
 584 };
 585
 586 static const unsigned pi5_pins[] = {
 587         TEGRA_PIN_PI5,
 588 };
 589
 590 static const unsigned pi6_pins[] = {
 591         TEGRA_PIN_PI6,
 592 };
 593
 594 static const unsigned pi7_pins[] = {
 595         TEGRA_PIN_PI7,
 596 };
 597
 598 static const unsigned pj0_pins[] = {
 599         TEGRA_PIN_PJ0,
 600 };
 601
 602 static const unsigned pj2_pins[] = {
 603         TEGRA_PIN_PJ2,
 604 };
 605
 606 static const unsigned uart2_cts_n_pj5_pins[] = {
 607         TEGRA_PIN_UART2_CTS_N_PJ5,
 608 };
 609
 610 static const unsigned uart2_rts_n_pj6_pins[] = {
 611         TEGRA_PIN_UART2_RTS_N_PJ6,
 612 };
 613
 614 static const unsigned pj7_pins[] = {
 615         TEGRA_PIN_PJ7,
 616 };
 617
 618 static const unsigned pk0_pins[] = {
 619         TEGRA_PIN_PK0,
 620 };
 621
 622 static const unsigned pk1_pins[] = {
 623         TEGRA_PIN_PK1,
 624 };
 625
 626 static const unsigned pk2_pins[] = {
 627         TEGRA_PIN_PK2,
 628 };
 629
 630 static const unsigned pk3_pins[] = {
 631         TEGRA_PIN_PK3,
 632 };
 633
 634 static const unsigned pk4_pins[] = {
 635         TEGRA_PIN_PK4,
 636 };
 637
 638 static const unsigned spdif_out_pk5_pins[] = {
 639         TEGRA_PIN_SPDIF_OUT_PK5,
 640 };
 641
 642 static const unsigned spdif_in_pk6_pins[] = {
 643         TEGRA_PIN_SPDIF_IN_PK6,
 644 };
 645
 646 static const unsigned pk7_pins[] = {
 647         TEGRA_PIN_PK7,
 648 };
 649
 650 static const unsigned dap1_fs_pn0_pins[] = {
 651         TEGRA_PIN_DAP1_FS_PN0,
 652 };
 653
 654 static const unsigned dap1_din_pn1_pins[] = {
 655         TEGRA_PIN_DAP1_DIN_PN1,
 656 };
 657
 658 static const unsigned dap1_dout_pn2_pins[] = {
 659         TEGRA_PIN_DAP1_DOUT_PN2,
 660 };
 661
 662 static const unsigned dap1_sclk_pn3_pins[] = {
 663         TEGRA_PIN_DAP1_SCLK_PN3,
 664 };
 665
 666 static const unsigned usb_vbus_en0_pn4_pins[] = {
 667         TEGRA_PIN_USB_VBUS_EN0_PN4,
 668 };
 669
 670 static const unsigned usb_vbus_en1_pn5_pins[] = {
 671         TEGRA_PIN_USB_VBUS_EN1_PN5,
 672 };
 673
 674 static const unsigned hdmi_int_pn7_pins[] = {
 675         TEGRA_PIN_HDMI_INT_PN7,
 676 };
 677
 678 static const unsigned ulpi_data7_po0_pins[] = {
 679         TEGRA_PIN_ULPI_DATA7_PO0,
 680 };
 681
 682 static const unsigned ulpi_data0_po1_pins[] = {
 683         TEGRA_PIN_ULPI_DATA0_PO1,
 684 };
 685
 686 static const unsigned ulpi_data1_po2_pins[] = {
 687         TEGRA_PIN_ULPI_DATA1_PO2,
 688 };
 689
 690 static const unsigned ulpi_data2_po3_pins[] = {
 691         TEGRA_PIN_ULPI_DATA2_PO3,
 692 };
 693
 694 static const unsigned ulpi_data3_po4_pins[] = {
 695         TEGRA_PIN_ULPI_DATA3_PO4,
 696 };
 697
 698 static const unsigned ulpi_data4_po5_pins[] = {
 699         TEGRA_PIN_ULPI_DATA4_PO5,
 700 };
 701
 702 static const unsigned ulpi_data5_po6_pins[] = {
 703         TEGRA_PIN_ULPI_DATA5_PO6,
 704 };
 705
 706 static const unsigned ulpi_data6_po7_pins[] = {
 707         TEGRA_PIN_ULPI_DATA6_PO7,
 708 };
 709
 710 static const unsigned dap3_fs_pp0_pins[] = {
 711         TEGRA_PIN_DAP3_FS_PP0,
 712 };
 713
 714 static const unsigned dap3_din_pp1_pins[] = {
 715         TEGRA_PIN_DAP3_DIN_PP1,
 716 };
 717
 718 static const unsigned dap3_dout_pp2_pins[] = {
 719         TEGRA_PIN_DAP3_DOUT_PP2,
 720 };
 721
 722 static const unsigned dap3_sclk_pp3_pins[] = {
 723         TEGRA_PIN_DAP3_SCLK_PP3,
 724 };
 725
 726 static const unsigned dap4_fs_pp4_pins[] = {
 727         TEGRA_PIN_DAP4_FS_PP4,
 728 };
 729
 730 static const unsigned dap4_din_pp5_pins[] = {
 731         TEGRA_PIN_DAP4_DIN_PP5,
 732 };
 733
 734 static const unsigned dap4_dout_pp6_pins[] = {
 735         TEGRA_PIN_DAP4_DOUT_PP6,
 736 };
 737
 738 static const unsigned dap4_sclk_pp7_pins[] = {
 739         TEGRA_PIN_DAP4_SCLK_PP7,
 740 };
 741
 742 static const unsigned kb_col0_pq0_pins[] = {
 743         TEGRA_PIN_KB_COL0_PQ0,
 744 };
 745
 746 static const unsigned kb_col1_pq1_pins[] = {
 747         TEGRA_PIN_KB_COL1_PQ1,
 748 };
 749
 750 static const unsigned kb_col2_pq2_pins[] = {
 751         TEGRA_PIN_KB_COL2_PQ2,
 752 };
 753
 754 static const unsigned kb_col3_pq3_pins[] = {
 755         TEGRA_PIN_KB_COL3_PQ3,
 756 };
 757
 758 static const unsigned kb_col4_pq4_pins[] = {
 759         TEGRA_PIN_KB_COL4_PQ4,
 760 };
 761
 762 static const unsigned kb_col5_pq5_pins[] = {
 763         TEGRA_PIN_KB_COL5_PQ5,
 764 };
 765
 766 static const unsigned kb_col6_pq6_pins[] = {
 767         TEGRA_PIN_KB_COL6_PQ6,
 768 };
 769
 770 static const unsigned kb_col7_pq7_pins[] = {
 771         TEGRA_PIN_KB_COL7_PQ7,
 772 };
 773
 774 static const unsigned kb_row0_pr0_pins[] = {
 775         TEGRA_PIN_KB_ROW0_PR0,
 776 };
 777
 778 static const unsigned kb_row1_pr1_pins[] = {
 779         TEGRA_PIN_KB_ROW1_PR1,
 780 };
 781
 782 static const unsigned kb_row2_pr2_pins[] = {
 783         TEGRA_PIN_KB_ROW2_PR2,
 784 };
 785
 786 static const unsigned kb_row3_pr3_pins[] = {
 787         TEGRA_PIN_KB_ROW3_PR3,
 788 };
 789
 790 static const unsigned kb_row4_pr4_pins[] = {
 791         TEGRA_PIN_KB_ROW4_PR4,
 792 };
 793
 794 static const unsigned kb_row5_pr5_pins[] = {
 795         TEGRA_PIN_KB_ROW5_PR5,
 796 };
 797
 798 static const unsigned kb_row6_pr6_pins[] = {
 799         TEGRA_PIN_KB_ROW6_PR6,
 800 };
 801
 802 static const unsigned kb_row7_pr7_pins[] = {
 803         TEGRA_PIN_KB_ROW7_PR7,
 804 };
 805
 806 static const unsigned kb_row8_ps0_pins[] = {
 807         TEGRA_PIN_KB_ROW8_PS0,
 808 };
 809
 810 static const unsigned kb_row9_ps1_pins[] = {
 811         TEGRA_PIN_KB_ROW9_PS1,
 812 };
 813
 814 static const unsigned kb_row10_ps2_pins[] = {
 815         TEGRA_PIN_KB_ROW10_PS2,
 816 };
 817
 818 static const unsigned kb_row11_ps3_pins[] = {
 819         TEGRA_PIN_KB_ROW11_PS3,
 820 };
 821
 822 static const unsigned kb_row12_ps4_pins[] = {
 823         TEGRA_PIN_KB_ROW12_PS4,
 824 };
 825
 826 static const unsigned kb_row13_ps5_pins[] = {
 827         TEGRA_PIN_KB_ROW13_PS5,
 828 };
 829
 830 static const unsigned kb_row14_ps6_pins[] = {
 831         TEGRA_PIN_KB_ROW14_PS6,
 832 };
 833
 834 static const unsigned kb_row15_ps7_pins[] = {
 835         TEGRA_PIN_KB_ROW15_PS7,
 836 };
 837
 838 static const unsigned kb_row16_pt0_pins[] = {
 839         TEGRA_PIN_KB_ROW16_PT0,
 840 };
 841
 842 static const unsigned kb_row17_pt1_pins[] = {
 843         TEGRA_PIN_KB_ROW17_PT1,
 844 };
 845
 846 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 847         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 848 };
 849
 850 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 851         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 852 };
 853
 854 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 855         TEGRA_PIN_SDMMC4_CMD_PT7,
 856 };
 857
 858 static const unsigned pu0_pins[] = {
 859         TEGRA_PIN_PU0,
 860 };
 861
 862 static const unsigned pu1_pins[] = {
 863         TEGRA_PIN_PU1,
 864 };
 865
 866 static const unsigned pu2_pins[] = {
 867         TEGRA_PIN_PU2,
 868 };
 869
 870 static const unsigned pu3_pins[] = {
 871         TEGRA_PIN_PU3,
 872 };
 873
 874 static const unsigned pu4_pins[] = {
 875         TEGRA_PIN_PU4,
 876 };
 877
 878 static const unsigned pu5_pins[] = {
 879         TEGRA_PIN_PU5,
 880 };
 881
 882 static const unsigned pu6_pins[] = {
 883         TEGRA_PIN_PU6,
 884 };
 885
 886 static const unsigned pv0_pins[] = {
 887         TEGRA_PIN_PV0,
 888 };
 889
 890 static const unsigned pv1_pins[] = {
 891         TEGRA_PIN_PV1,
 892 };
 893
 894 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 895         TEGRA_PIN_SDMMC3_CD_N_PV2,
 896 };
 897
 898 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 899         TEGRA_PIN_SDMMC1_WP_N_PV3,
 900 };
 901
 902 static const unsigned ddc_scl_pv4_pins[] = {
 903         TEGRA_PIN_DDC_SCL_PV4,
 904 };
 905
 906 static const unsigned ddc_sda_pv5_pins[] = {
 907         TEGRA_PIN_DDC_SDA_PV5,
 908 };
 909
 910 static const unsigned gpio_w2_aud_pw2_pins[] = {
 911         TEGRA_PIN_GPIO_W2_AUD_PW2,
 912 };
 913
 914 static const unsigned gpio_w3_aud_pw3_pins[] = {
 915         TEGRA_PIN_GPIO_W3_AUD_PW3,
 916 };
 917
 918 static const unsigned dap_mclk1_pw4_pins[] = {
 919         TEGRA_PIN_DAP_MCLK1_PW4,
 920 };
 921
 922 static const unsigned clk2_out_pw5_pins[] = {
 923         TEGRA_PIN_CLK2_OUT_PW5,
 924 };
 925
 926 static const unsigned uart3_txd_pw6_pins[] = {
 927         TEGRA_PIN_UART3_TXD_PW6,
 928 };
 929
 930 static const unsigned uart3_rxd_pw7_pins[] = {
 931         TEGRA_PIN_UART3_RXD_PW7,
 932 };
 933
 934 static const unsigned dvfs_pwm_px0_pins[] = {
 935         TEGRA_PIN_DVFS_PWM_PX0,
 936 };
 937
 938 static const unsigned gpio_x1_aud_px1_pins[] = {
 939         TEGRA_PIN_GPIO_X1_AUD_PX1,
 940 };
 941
 942 static const unsigned dvfs_clk_px2_pins[] = {
 943         TEGRA_PIN_DVFS_CLK_PX2,
 944 };
 945
 946 static const unsigned gpio_x3_aud_px3_pins[] = {
 947         TEGRA_PIN_GPIO_X3_AUD_PX3,
 948 };
 949
 950 static const unsigned gpio_x4_aud_px4_pins[] = {
 951         TEGRA_PIN_GPIO_X4_AUD_PX4,
 952 };
 953
 954 static const unsigned gpio_x5_aud_px5_pins[] = {
 955         TEGRA_PIN_GPIO_X5_AUD_PX5,
 956 };
 957
 958 static const unsigned gpio_x6_aud_px6_pins[] = {
 959         TEGRA_PIN_GPIO_X6_AUD_PX6,
 960 };
 961
 962 static const unsigned gpio_x7_aud_px7_pins[] = {
 963         TEGRA_PIN_GPIO_X7_AUD_PX7,
 964 };
 965
 966 static const unsigned ulpi_clk_py0_pins[] = {
 967         TEGRA_PIN_ULPI_CLK_PY0,
 968 };
 969
 970 static const unsigned ulpi_dir_py1_pins[] = {
 971         TEGRA_PIN_ULPI_DIR_PY1,
 972 };
 973
 974 static const unsigned ulpi_nxt_py2_pins[] = {
 975         TEGRA_PIN_ULPI_NXT_PY2,
 976 };
 977
 978 static const unsigned ulpi_stp_py3_pins[] = {
 979         TEGRA_PIN_ULPI_STP_PY3,
 980 };
 981
 982 static const unsigned sdmmc1_dat3_py4_pins[] = {
 983         TEGRA_PIN_SDMMC1_DAT3_PY4,
 984 };
 985
 986 static const unsigned sdmmc1_dat2_py5_pins[] = {
 987         TEGRA_PIN_SDMMC1_DAT2_PY5,
 988 };
 989
 990 static const unsigned sdmmc1_dat1_py6_pins[] = {
 991         TEGRA_PIN_SDMMC1_DAT1_PY6,
 992 };
 993
 994 static const unsigned sdmmc1_dat0_py7_pins[] = {
 995         TEGRA_PIN_SDMMC1_DAT0_PY7,
 996 };
 997
 998 static const unsigned sdmmc1_clk_pz0_pins[] = {
 999         TEGRA_PIN_SDMMC1_CLK_PZ0,
1000 };
1001
1002 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1003         TEGRA_PIN_SDMMC1_CMD_PZ1,
1004 };
1005
1006 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1007         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1008 };
1009
1010 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1011         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1012 };
1013
1014 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1015         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1016 };
1017
1018 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1019         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1020 };
1021
1022 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1023         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1024 };
1025
1026 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1027         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1028 };
1029
1030 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1031         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1032 };
1033
1034 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1035         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1036 };
1037
1038 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1039         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1040 };
1041
1042 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1043         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1044 };
1045
1046 static const unsigned pbb0_pins[] = {
1047         TEGRA_PIN_PBB0,
1048 };
1049
1050 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1051         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1052 };
1053
1054 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1055         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1056 };
1057
1058 static const unsigned pbb3_pins[] = {
1059         TEGRA_PIN_PBB3,
1060 };
1061
1062 static const unsigned pbb4_pins[] = {
1063         TEGRA_PIN_PBB4,
1064 };
1065
1066 static const unsigned pbb5_pins[] = {
1067         TEGRA_PIN_PBB5,
1068 };
1069
1070 static const unsigned pbb6_pins[] = {
1071         TEGRA_PIN_PBB6,
1072 };
1073
1074 static const unsigned pbb7_pins[] = {
1075         TEGRA_PIN_PBB7,
1076 };
1077
1078 static const unsigned cam_mclk_pcc0_pins[] = {
1079         TEGRA_PIN_CAM_MCLK_PCC0,
1080 };
1081
1082 static const unsigned pcc1_pins[] = {
1083         TEGRA_PIN_PCC1,
1084 };
1085
1086 static const unsigned pcc2_pins[] = {
1087         TEGRA_PIN_PCC2,
1088 };
1089
1090 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1091         TEGRA_PIN_SDMMC4_CLK_PCC4,
1092 };
1093
1094 static const unsigned clk2_req_pcc5_pins[] = {
1095         TEGRA_PIN_CLK2_REQ_PCC5,
1096 };
1097
1098 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1099         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1100 };
1101
1102 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1103         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1104 };
1105
1106 static const unsigned pex_wake_n_pdd3_pins[] = {
1107         TEGRA_PIN_PEX_WAKE_N_PDD3,
1108 };
1109
1110 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1111         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1112 };
1113
1114 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1115         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1116 };
1117
1118 static const unsigned clk3_out_pee0_pins[] = {
1119         TEGRA_PIN_CLK3_OUT_PEE0,
1120 };
1121
1122 static const unsigned clk3_req_pee1_pins[] = {
1123         TEGRA_PIN_CLK3_REQ_PEE1,
1124 };
1125
1126 static const unsigned dap_mclk1_req_pee2_pins[] = {
1127         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1128 };
1129
1130 static const unsigned hdmi_cec_pee3_pins[] = {
1131         TEGRA_PIN_HDMI_CEC_PEE3,
1132 };
1133
1134 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1135         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1136 };
1137
1138 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1139         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1140 };
1141 static const unsigned dp_hpd_pff0_pins[] = {
1142         TEGRA_PIN_DP_HPD_PFF0,
1143 };
1144
1145 static const unsigned usb_vbus_en2_pff1_pins[] = {
1146         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1147 };
1148
1149 static const unsigned pff2_pins[] = {
1150         TEGRA_PIN_PFF2,
1151 };
1152
1153 static const unsigned core_pwr_req_pins[] = {
1154         TEGRA_PIN_CORE_PWR_REQ,
1155 };
1156
1157 static const unsigned cpu_pwr_req_pins[] = {
1158         TEGRA_PIN_CPU_PWR_REQ,
1159 };
1160
1161 static const unsigned owr_pins[] = {
1162         TEGRA_PIN_OWR,
1163 };
1164
1165 static const unsigned pwr_int_n_pins[] = {
1166         TEGRA_PIN_PWR_INT_N,
1167 };
1168
1169 static const unsigned reset_out_n_pins[] = {
1170         TEGRA_PIN_RESET_OUT_N,
1171 };
1172
1173 static const unsigned clk_32k_in_pins[] = {
1174         TEGRA_PIN_CLK_32K_IN,
1175 };
1176
1177 static const unsigned gmi_clk_lb_pins[] = {
1178         TEGRA_PIN_GMI_CLK_LB,
1179 };
1180
1181 static const unsigned jtag_rtck_pins[] = {
1182         TEGRA_PIN_JTAG_RTCK,
1183 };
1184
1185 static const unsigned drive_ao1_pins[] = {
1186         TEGRA_PIN_KB_ROW0_PR0,
1187         TEGRA_PIN_KB_ROW1_PR1,
1188         TEGRA_PIN_KB_ROW2_PR2,
1189         TEGRA_PIN_KB_ROW3_PR3,
1190         TEGRA_PIN_KB_ROW4_PR4,
1191         TEGRA_PIN_KB_ROW5_PR5,
1192         TEGRA_PIN_KB_ROW6_PR6,
1193         TEGRA_PIN_KB_ROW7_PR7,
1194         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1195         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1196 };
1197
1198 static const unsigned drive_ao2_pins[] = {
1199         TEGRA_PIN_CLK_32K_OUT_PA0,
1200         TEGRA_PIN_CLK_32K_IN,
1201         TEGRA_PIN_KB_COL0_PQ0,
1202         TEGRA_PIN_KB_COL1_PQ1,
1203         TEGRA_PIN_KB_COL2_PQ2,
1204         TEGRA_PIN_KB_COL3_PQ3,
1205         TEGRA_PIN_KB_COL4_PQ4,
1206         TEGRA_PIN_KB_COL5_PQ5,
1207         TEGRA_PIN_KB_COL6_PQ6,
1208         TEGRA_PIN_KB_COL7_PQ7,
1209         TEGRA_PIN_KB_ROW8_PS0,
1210         TEGRA_PIN_KB_ROW9_PS1,
1211         TEGRA_PIN_KB_ROW10_PS2,
1212         TEGRA_PIN_KB_ROW11_PS3,
1213         TEGRA_PIN_KB_ROW12_PS4,
1214         TEGRA_PIN_KB_ROW13_PS5,
1215         TEGRA_PIN_KB_ROW14_PS6,
1216         TEGRA_PIN_KB_ROW15_PS7,
1217         TEGRA_PIN_KB_ROW16_PT0,
1218         TEGRA_PIN_KB_ROW17_PT1,
1219         TEGRA_PIN_SDMMC3_CD_N_PV2,
1220         TEGRA_PIN_CORE_PWR_REQ,
1221         TEGRA_PIN_CPU_PWR_REQ,
1222         TEGRA_PIN_PWR_INT_N,
1223 };
1224
1225 static const unsigned drive_at1_pins[] = {
1226         TEGRA_PIN_PH0,
1227         TEGRA_PIN_PH1,
1228         TEGRA_PIN_PH2,
1229         TEGRA_PIN_PH3,
1230 };
1231
1232 static const unsigned drive_at2_pins[] = {
1233         TEGRA_PIN_PG0,
1234         TEGRA_PIN_PG1,
1235         TEGRA_PIN_PG2,
1236         TEGRA_PIN_PG3,
1237         TEGRA_PIN_PG4,
1238         TEGRA_PIN_PG5,
1239         TEGRA_PIN_PG6,
1240         TEGRA_PIN_PG7,
1241         TEGRA_PIN_PI0,
1242         TEGRA_PIN_PI1,
1243         TEGRA_PIN_PI3,
1244         TEGRA_PIN_PI4,
1245         TEGRA_PIN_PI7,
1246         TEGRA_PIN_PK0,
1247         TEGRA_PIN_PK2,
1248 };
1249
1250 static const unsigned drive_at3_pins[] = {
1251         TEGRA_PIN_PC7,
1252         TEGRA_PIN_PJ0,
1253 };
1254
1255 static const unsigned drive_at4_pins[] = {
1256         TEGRA_PIN_PB0,
1257         TEGRA_PIN_PB1,
1258         TEGRA_PIN_PJ0,
1259         TEGRA_PIN_PJ7,
1260         TEGRA_PIN_PK7,
1261 };
1262
1263 static const unsigned drive_at5_pins[] = {
1264         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1265         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1266 };
1267
1268 static const unsigned drive_cdev1_pins[] = {
1269         TEGRA_PIN_DAP_MCLK1_PW4,
1270         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1271 };
1272
1273 static const unsigned drive_cdev2_pins[] = {
1274         TEGRA_PIN_CLK2_OUT_PW5,
1275         TEGRA_PIN_CLK2_REQ_PCC5,
1276 };
1277
1278 static const unsigned drive_dap1_pins[] = {
1279         TEGRA_PIN_DAP1_FS_PN0,
1280         TEGRA_PIN_DAP1_DIN_PN1,
1281         TEGRA_PIN_DAP1_DOUT_PN2,
1282         TEGRA_PIN_DAP1_SCLK_PN3,
1283 };
1284
1285 static const unsigned drive_dap2_pins[] = {
1286         TEGRA_PIN_DAP2_FS_PA2,
1287         TEGRA_PIN_DAP2_SCLK_PA3,
1288         TEGRA_PIN_DAP2_DIN_PA4,
1289         TEGRA_PIN_DAP2_DOUT_PA5,
1290 };
1291
1292 static const unsigned drive_dap3_pins[] = {
1293         TEGRA_PIN_DAP3_FS_PP0,
1294         TEGRA_PIN_DAP3_DIN_PP1,
1295         TEGRA_PIN_DAP3_DOUT_PP2,
1296         TEGRA_PIN_DAP3_SCLK_PP3,
1297 };
1298
1299 static const unsigned drive_dap4_pins[] = {
1300         TEGRA_PIN_DAP4_FS_PP4,
1301         TEGRA_PIN_DAP4_DIN_PP5,
1302         TEGRA_PIN_DAP4_DOUT_PP6,
1303         TEGRA_PIN_DAP4_SCLK_PP7,
1304 };
1305
1306 static const unsigned drive_dbg_pins[] = {
1307         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1308         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1309         TEGRA_PIN_PU0,
1310         TEGRA_PIN_PU1,
1311         TEGRA_PIN_PU2,
1312         TEGRA_PIN_PU3,
1313         TEGRA_PIN_PU4,
1314         TEGRA_PIN_PU5,
1315         TEGRA_PIN_PU6,
1316 };
1317
1318 static const unsigned drive_sdio3_pins[] = {
1319         TEGRA_PIN_SDMMC3_CLK_PA6,
1320         TEGRA_PIN_SDMMC3_CMD_PA7,
1321         TEGRA_PIN_SDMMC3_DAT3_PB4,
1322         TEGRA_PIN_SDMMC3_DAT2_PB5,
1323         TEGRA_PIN_SDMMC3_DAT1_PB6,
1324         TEGRA_PIN_SDMMC3_DAT0_PB7,
1325         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1326         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1327 };
1328
1329 static const unsigned drive_spi_pins[] = {
1330         TEGRA_PIN_DVFS_PWM_PX0,
1331         TEGRA_PIN_GPIO_X1_AUD_PX1,
1332         TEGRA_PIN_DVFS_CLK_PX2,
1333         TEGRA_PIN_GPIO_X3_AUD_PX3,
1334         TEGRA_PIN_GPIO_X4_AUD_PX4,
1335         TEGRA_PIN_GPIO_X5_AUD_PX5,
1336         TEGRA_PIN_GPIO_X6_AUD_PX6,
1337         TEGRA_PIN_GPIO_X7_AUD_PX7,
1338         TEGRA_PIN_GPIO_W2_AUD_PW2,
1339         TEGRA_PIN_GPIO_W3_AUD_PW3,
1340 };
1341
1342 static const unsigned drive_uaa_pins[] = {
1343         TEGRA_PIN_ULPI_DATA0_PO1,
1344         TEGRA_PIN_ULPI_DATA1_PO2,
1345         TEGRA_PIN_ULPI_DATA2_PO3,
1346         TEGRA_PIN_ULPI_DATA3_PO4,
1347 };
1348
1349 static const unsigned drive_uab_pins[] = {
1350         TEGRA_PIN_ULPI_DATA7_PO0,
1351         TEGRA_PIN_ULPI_DATA4_PO5,
1352         TEGRA_PIN_ULPI_DATA5_PO6,
1353         TEGRA_PIN_ULPI_DATA6_PO7,
1354         TEGRA_PIN_PV0,
1355         TEGRA_PIN_PV1,
1356 };
1357
1358 static const unsigned drive_uart2_pins[] = {
1359         TEGRA_PIN_UART2_TXD_PC2,
1360         TEGRA_PIN_UART2_RXD_PC3,
1361         TEGRA_PIN_UART2_CTS_N_PJ5,
1362         TEGRA_PIN_UART2_RTS_N_PJ6,
1363 };
1364
1365 static const unsigned drive_uart3_pins[] = {
1366         TEGRA_PIN_UART3_CTS_N_PA1,
1367         TEGRA_PIN_UART3_RTS_N_PC0,
1368         TEGRA_PIN_UART3_TXD_PW6,
1369         TEGRA_PIN_UART3_RXD_PW7,
1370 };
1371
1372 static const unsigned drive_sdio1_pins[] = {
1373         TEGRA_PIN_SDMMC1_DAT3_PY4,
1374         TEGRA_PIN_SDMMC1_DAT2_PY5,
1375         TEGRA_PIN_SDMMC1_DAT1_PY6,
1376         TEGRA_PIN_SDMMC1_DAT0_PY7,
1377         TEGRA_PIN_SDMMC1_CLK_PZ0,
1378         TEGRA_PIN_SDMMC1_CMD_PZ1,
1379 };
1380
1381 static const unsigned drive_ddc_pins[] = {
1382         TEGRA_PIN_DDC_SCL_PV4,
1383         TEGRA_PIN_DDC_SDA_PV5,
1384 };
1385
1386 static const unsigned drive_gma_pins[] = {
1387         TEGRA_PIN_SDMMC4_CLK_PCC4,
1388         TEGRA_PIN_SDMMC4_CMD_PT7,
1389         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1390         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1391         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1392         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1393         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1394         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1395         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1396         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1397 };
1398
1399 static const unsigned drive_gme_pins[] = {
1400         TEGRA_PIN_PBB0,
1401         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1402         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1403         TEGRA_PIN_PBB3,
1404         TEGRA_PIN_PCC2,
1405 };
1406
1407 static const unsigned drive_gmf_pins[] = {
1408         TEGRA_PIN_PBB4,
1409         TEGRA_PIN_PBB5,
1410         TEGRA_PIN_PBB6,
1411         TEGRA_PIN_PBB7,
1412 };
1413
1414 static const unsigned drive_gmg_pins[] = {
1415         TEGRA_PIN_CAM_MCLK_PCC0,
1416 };
1417
1418 static const unsigned drive_gmh_pins[] = {
1419         TEGRA_PIN_PCC1,
1420 };
1421
1422 static const unsigned drive_owr_pins[] = {
1423         TEGRA_PIN_SDMMC3_CD_N_PV2,
1424         TEGRA_PIN_OWR,
1425 };
1426
1427 static const unsigned drive_uda_pins[] = {
1428         TEGRA_PIN_ULPI_CLK_PY0,
1429         TEGRA_PIN_ULPI_DIR_PY1,
1430         TEGRA_PIN_ULPI_NXT_PY2,
1431         TEGRA_PIN_ULPI_STP_PY3,
1432 };
1433
1434 static const unsigned drive_gpv_pins[] = {
1435         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1436         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1437         TEGRA_PIN_PEX_WAKE_N_PDD3,
1438         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1439         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1440         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1441         TEGRA_PIN_PFF2,
1442 };
1443
1444 static const unsigned drive_cec_pins[] = {
1445         TEGRA_PIN_HDMI_CEC_PEE3,
1446 };
1447
1448 static const unsigned drive_dev3_pins[] = {
1449         TEGRA_PIN_CLK3_OUT_PEE0,
1450         TEGRA_PIN_CLK3_REQ_PEE1,
1451 };
1452
1453 static const unsigned drive_at6_pins[] = {
1454         TEGRA_PIN_PK1,
1455         TEGRA_PIN_PK3,
1456         TEGRA_PIN_PK4,
1457         TEGRA_PIN_PI2,
1458         TEGRA_PIN_PI5,
1459         TEGRA_PIN_PI6,
1460         TEGRA_PIN_PH4,
1461         TEGRA_PIN_PH5,
1462         TEGRA_PIN_PH6,
1463         TEGRA_PIN_PH7,
1464 };
1465
1466 static const unsigned drive_dap5_pins[] = {
1467         TEGRA_PIN_SPDIF_IN_PK6,
1468         TEGRA_PIN_SPDIF_OUT_PK5,
1469         TEGRA_PIN_DP_HPD_PFF0,
1470 };
1471
1472 static const unsigned drive_usb_vbus_en_pins[] = {
1473         TEGRA_PIN_USB_VBUS_EN0_PN4,
1474         TEGRA_PIN_USB_VBUS_EN1_PN5,
1475 };
1476
1477 static const unsigned drive_ao3_pins[] = {
1478         TEGRA_PIN_RESET_OUT_N,
1479 };
1480
1481 static const unsigned drive_ao0_pins[] = {
1482         TEGRA_PIN_JTAG_RTCK,
1483 };
1484
1485 static const unsigned drive_hv0_pins[] = {
1486         TEGRA_PIN_HDMI_INT_PN7,
1487 };
1488
1489 static const unsigned drive_sdio4_pins[] = {
1490         TEGRA_PIN_SDMMC1_WP_N_PV3,
1491 };
1492
1493 static const unsigned drive_ao4_pins[] = {
1494         TEGRA_PIN_JTAG_RTCK,
1495 };
1496
1497 enum tegra_mux {
1498         TEGRA_MUX_BLINK,
1499         TEGRA_MUX_CEC,
1500         TEGRA_MUX_CLDVFS,
1501         TEGRA_MUX_CLK12,
1502         TEGRA_MUX_CPU,
1503         TEGRA_MUX_DAP,
1504         TEGRA_MUX_DAP1,
1505         TEGRA_MUX_DAP2,
1506         TEGRA_MUX_DEV3,
1507         TEGRA_MUX_DISPLAYA,
1508         TEGRA_MUX_DISPLAYA_ALT,
1509         TEGRA_MUX_DISPLAYB,
1510         TEGRA_MUX_DTV,
1511         TEGRA_MUX_EXTPERIPH1,
1512         TEGRA_MUX_EXTPERIPH2,
1513         TEGRA_MUX_EXTPERIPH3,
1514         TEGRA_MUX_GMI,
1515         TEGRA_MUX_GMI_ALT,
1516         TEGRA_MUX_HDA,
1517         TEGRA_MUX_HSI,
1518         TEGRA_MUX_I2C1,
1519         TEGRA_MUX_I2C2,
1520         TEGRA_MUX_I2C3,
1521         TEGRA_MUX_I2C4,
1522         TEGRA_MUX_I2CPWR,
1523         TEGRA_MUX_I2S0,
1524         TEGRA_MUX_I2S1,
1525         TEGRA_MUX_I2S2,
1526         TEGRA_MUX_I2S3,
1527         TEGRA_MUX_I2S4,
1528         TEGRA_MUX_IRDA,
1529         TEGRA_MUX_KBC,
1530         TEGRA_MUX_OWR,
1531         TEGRA_MUX_PMI,
1532         TEGRA_MUX_PWM0,
1533         TEGRA_MUX_PWM1,
1534         TEGRA_MUX_PWM2,
1535         TEGRA_MUX_PWM3,
1536         TEGRA_MUX_PWRON,
1537         TEGRA_MUX_RESET_OUT_N,
1538         TEGRA_MUX_RSVD1,
1539         TEGRA_MUX_RSVD2,
1540         TEGRA_MUX_RSVD3,
1541         TEGRA_MUX_RSVD4,
1542         TEGRA_MUX_SDMMC1,
1543         TEGRA_MUX_SDMMC2,
1544         TEGRA_MUX_SDMMC3,
1545         TEGRA_MUX_SDMMC4,
1546         TEGRA_MUX_SOC,
1547         TEGRA_MUX_SPDIF,
1548         TEGRA_MUX_SPI1,
1549         TEGRA_MUX_SPI2,
1550         TEGRA_MUX_SPI3,
1551         TEGRA_MUX_SPI4,
1552         TEGRA_MUX_SPI5,
1553         TEGRA_MUX_SPI6,
1554         TEGRA_MUX_TRACE,
1555         TEGRA_MUX_UARTA,
1556         TEGRA_MUX_UARTB,
1557         TEGRA_MUX_UARTC,
1558         TEGRA_MUX_UARTD,
1559         TEGRA_MUX_ULPI,
1560         TEGRA_MUX_USB,
1561         TEGRA_MUX_VGP1,
1562         TEGRA_MUX_VGP2,
1563         TEGRA_MUX_VGP3,
1564         TEGRA_MUX_VGP4,
1565         TEGRA_MUX_VGP5,
1566         TEGRA_MUX_VGP6,
1567         TEGRA_MUX_VI,
1568         TEGRA_MUX_VI_ALT1,
1569         TEGRA_MUX_VI_ALT3,
1570         TEGRA_MUX_VIMCLK2,
1571         TEGRA_MUX_VIMCLK2_ALT,
1572         TEGRA_MUX_SATA,
1573         TEGRA_MUX_CCLA,
1574         TEGRA_MUX_PE0,
1575         TEGRA_MUX_PE,
1576         TEGRA_MUX_PE1,
1577         TEGRA_MUX_DP,
1578         TEGRA_MUX_RTCK,
1579         TEGRA_MUX_SYS,
1580         TEGRA_MUX_CLK,
1581         TEGRA_MUX_TMDS,
1582 };
1583
1584 static const char * const blink_groups[] = {
1585         "clk_32k_out_pa0",
1586 };
1587
1588 static const char * const cec_groups[] = {
1589         "hdmi_cec_pee3",
1590 };
1591
1592 static const char * const cldvfs_groups[] = {
1593         "ph2",
1594         "ph3",
1595         "kb_row7_pr7",
1596         "kb_row8_ps0",
1597         "dvfs_pwm_px0",
1598         "dvfs_clk_px2",
1599 };
1600
1601 static const char * const clk12_groups[] = {
1602         "sdmmc1_wp_n_pv3",
1603         "sdmmc1_clk_pz0",
1604 };
1605
1606 static const char * const cpu_groups[] = {
1607         "cpu_pwr_req",
1608 };
1609
1610 static const char * const dap_groups[] = {
1611         "dap_mclk1_pee2",
1612         "clk2_req_pcc5",
1613 };
1614
1615 static const char * const dap1_groups[] = {
1616         "dap_mclk1_pee2",
1617 };
1618
1619 static const char * const dap2_groups[] = {
1620         "dap_mclk1_pw4",
1621         "gpio_x4_aud_px4",
1622 };
1623
1624 static const char * const dev3_groups[] = {
1625         "clk3_req_pee1",
1626 };
1627
1628 static const char * const displaya_groups[] = {
1629         "dap3_fs_pp0",
1630         "dap3_din_pp1",
1631         "dap3_dout_pp2",
1632         "ph1",
1633         "pi4",
1634         "pbb3",
1635         "pbb4",
1636         "pbb5",
1637         "kb_row3_pr3",
1638         "kb_row4_pr4",
1639         "kb_row5_pr5",
1640         "kb_row6_pr6",
1641         "kb_col3_pq3",
1642         "sdmmc3_dat2_pb5",
1643 };
1644
1645 static const char * const displaya_alt_groups[] = {
1646         "kb_row6_pr6",
1647 };
1648
1649 static const char * const displayb_groups[] = {
1650         "dap3_fs_pp0",
1651         "dap3_din_pp1",
1652         "dap3_sclk_pp3",
1653
1654         "pu3",
1655         "pu4",
1656         "pu5",
1657
1658         "pbb3",
1659         "pbb4",
1660         "pbb6",
1661
1662         "kb_row3_pr3",
1663         "kb_row4_pr4",
1664         "kb_row5_pr5",
1665         "kb_row6_pr6",
1666
1667         "sdmmc3_dat3_pb4",
1668 };
1669
1670 static const char * const dtv_groups[] = {
1671         "uart3_cts_n_pa1",
1672         "uart3_rts_n_pc0",
1673         "dap4_fs_pp4",
1674         "dap4_dout_pp6",
1675         "pi7",
1676         "ph0",
1677         "ph6",
1678         "ph7",
1679 };
1680
1681 static const char * const extperiph1_groups[] = {
1682         "dap_mclk1_pw4",
1683 };
1684
1685 static const char * const extperiph2_groups[] = {
1686         "clk2_out_pw5",
1687 };
1688
1689 static const char * const extperiph3_groups[] = {
1690         "clk3_out_pee0",
1691 };
1692
1693 static const char * const gmi_groups[] = {
1694         "uart2_cts_n_pj5",
1695         "uart2_rts_n_pj6",
1696         "uart3_txd_pw6",
1697         "uart3_rxd_pw7",
1698         "uart3_cts_n_pa1",
1699         "uart3_rts_n_pc0",
1700
1701         "pu0",
1702         "pu1",
1703         "pu2",
1704         "pu3",
1705         "pu4",
1706         "pu5",
1707         "pu6",
1708
1709         "dap4_fs_pp4",
1710         "dap4_din_pp5",
1711         "dap4_dout_pp6",
1712         "dap4_sclk_pp7",
1713
1714         "pc7",
1715
1716         "pg0",
1717         "pg1",
1718         "pg2",
1719         "pg3",
1720         "pg4",
1721         "pg5",
1722         "pg6",
1723         "pg7",
1724
1725         "ph0",
1726         "ph1",
1727         "ph2",
1728         "ph3",
1729         "ph4",
1730         "ph5",
1731         "ph6",
1732         "ph7",
1733
1734         "pi0",
1735         "pi1",
1736         "pi2",
1737         "pi3",
1738         "pi4",
1739         "pi5",
1740         "pi6",
1741         "pi7",
1742
1743         "pj0",
1744         "pj2",
1745
1746         "pk0",
1747         "pk1",
1748         "pk2",
1749         "pk3",
1750         "pk4",
1751
1752         "pj7",
1753         "pb0",
1754         "pb1",
1755         "pk7",
1756
1757         "gen2_i2c_scl_pt5",
1758         "gen2_i2c_sda_pt6",
1759
1760         "sdmmc4_dat0_paa0",
1761         "sdmmc4_dat1_paa1",
1762         "sdmmc4_dat2_paa2",
1763         "sdmmc4_dat3_paa3",
1764         "sdmmc4_dat4_paa4",
1765         "sdmmc4_dat6_paa6",
1766         "sdmmc4_dat7_paa7",
1767         "sdmmc4_clk_pcc4",
1768         "sdmmc4_cmd_pt7",
1769         "gmi_clk_lb",
1770
1771         "dap1_fs_pn0",
1772         "dap1_din_pn1",
1773         "dap1_dout_pn2",
1774         "dap1_sclk_pn3",
1775
1776         "dap2_fs_pa2",
1777         "dap2_din_pa4",
1778         "dap2_dout_pa5",
1779         "dap2_sclk_pa3",
1780
1781         "dvfs_pwm_px0",
1782         "dvfs_clk_px2",
1783         "gpio_x1_aud_px1",
1784         "gpio_x3_aud_px3",
1785         "gpio_x4_aud_px4",
1786         "gpio_x5_aud_px5",
1787         "gpio_x6_aud_px6",
1788 };
1789
1790 static const char * const gmi_alt_groups[] = {
1791         "pc7",
1792         "pk4",
1793         "pj7",
1794 };
1795
1796 static const char * const hda_groups[] = {
1797         "dap1_fs_pn0",
1798         "dap1_din_pn1",
1799         "dap1_dout_pn2",
1800         "dap1_sclk_pn3",
1801         "dap2_fs_pa2",
1802         "dap2_sclk_pa3",
1803         "dap2_din_pa4",
1804         "dap2_dout_pa5",
1805 };
1806
1807 static const char * const hsi_groups[] = {
1808         "ulpi_data0_po1",
1809         "ulpi_data1_po2",
1810         "ulpi_data2_po3",
1811         "ulpi_data3_po4",
1812         "ulpi_data4_po5",
1813         "ulpi_data5_po6",
1814         "ulpi_data6_po7",
1815         "ulpi_data7_po0",
1816 };
1817
1818 static const char * const i2c1_groups[] = {
1819         "gen1_i2c_scl_pc4",
1820         "gen1_i2c_sda_pc5",
1821         "gpio_w2_aud_pw2",
1822         "gpio_w3_aud_pw3",
1823 };
1824
1825 static const char * const i2c2_groups[] = {
1826         "gen2_i2c_scl_pt5",
1827         "gen2_i2c_sda_pt6",
1828 };
1829
1830 static const char * const i2c3_groups[] = {
1831         "spdif_in_pk6",
1832         "spdif_out_pk5",
1833         "cam_i2c_scl_pbb1",
1834         "cam_i2c_sda_pbb2",
1835 };
1836
1837 static const char * const i2c4_groups[] = {
1838         "ddc_scl_pv4",
1839         "ddc_sda_pv5",
1840 };
1841
1842 static const char * const i2cpwr_groups[] = {
1843         "pwr_i2c_scl_pz6",
1844         "pwr_i2c_sda_pz7",
1845 };
1846
1847 static const char * const i2s0_groups[] = {
1848         "dap1_fs_pn0",
1849         "dap1_din_pn1",
1850         "dap1_dout_pn2",
1851         "dap1_sclk_pn3",
1852 };
1853
1854 static const char * const i2s1_groups[] = {
1855         "dap2_fs_pa2",
1856         "dap2_sclk_pa3",
1857         "dap2_din_pa4",
1858         "dap2_dout_pa5",
1859 };
1860
1861 static const char * const i2s2_groups[] = {
1862         "dap3_fs_pp0",
1863         "dap3_din_pp1",
1864         "dap3_dout_pp2",
1865         "dap3_sclk_pp3",
1866 };
1867
1868 static const char * const i2s3_groups[] = {
1869         "dap4_fs_pp4",
1870         "dap4_din_pp5",
1871         "dap4_dout_pp6",
1872         "dap4_sclk_pp7",
1873 };
1874
1875 static const char * const i2s4_groups[] = {
1876         "pcc1",
1877         "pbb6",
1878         "pbb7",
1879         "pcc2",
1880 };
1881
1882 static const char * const irda_groups[] = {
1883         "uart2_rxd_pc3",
1884         "uart2_txd_pc2",
1885         "kb_row11_ps3",
1886         "kb_row12_ps4",
1887 };
1888
1889 static const char * const kbc_groups[] = {
1890         "kb_row0_pr0",
1891         "kb_row1_pr1",
1892         "kb_row2_pr2",
1893         "kb_row3_pr3",
1894         "kb_row4_pr4",
1895         "kb_row5_pr5",
1896         "kb_row6_pr6",
1897         "kb_row7_pr7",
1898         "kb_row8_ps0",
1899         "kb_row9_ps1",
1900         "kb_row10_ps2",
1901         "kb_row11_ps3",
1902         "kb_row12_ps4",
1903         "kb_row13_ps5",
1904         "kb_row14_ps6",
1905         "kb_row15_ps7",
1906         "kb_row16_pt0",
1907         "kb_row17_pt1",
1908
1909         "kb_col0_pq0",
1910         "kb_col1_pq1",
1911         "kb_col2_pq2",
1912         "kb_col3_pq3",
1913         "kb_col4_pq4",
1914         "kb_col5_pq5",
1915         "kb_col6_pq6",
1916         "kb_col7_pq7",
1917 };
1918
1919 static const char * const owr_groups[] = {
1920         "pu0",
1921         "kb_col4_pq4",
1922         "owr",
1923         "sdmmc3_cd_n_pv2",
1924 };
1925
1926 static const char * const pmi_groups[] = {
1927         "pwr_int_n",
1928 };
1929
1930 static const char * const pwm0_groups[] = {
1931         "sdmmc1_dat2_py5",
1932         "uart3_rts_n_pc0",
1933         "pu3",
1934         "ph0",
1935         "sdmmc3_dat3_pb4",
1936 };
1937
1938 static const char * const pwm1_groups[] = {
1939         "sdmmc1_dat1_py6",
1940         "pu4",
1941         "ph1",
1942         "sdmmc3_dat2_pb5",
1943 };
1944
1945 static const char * const pwm2_groups[] = {
1946         "pu5",
1947         "ph2",
1948         "kb_col3_pq3",
1949         "sdmmc3_dat1_pb6",
1950 };
1951
1952 static const char * const pwm3_groups[] = {
1953         "pu6",
1954         "ph3",
1955         "sdmmc3_cmd_pa7",
1956 };
1957
1958 static const char * const pwron_groups[] = {
1959         "core_pwr_req",
1960 };
1961
1962 static const char * const reset_out_n_groups[] = {
1963         "reset_out_n",
1964 };
1965
1966 static const char * const rsvd1_groups[] = {
1967         "pv0",
1968         "pv1",
1969
1970         "hdmi_int_pn7",
1971         "pu1",
1972         "pu2",
1973         "pc7",
1974         "pi7",
1975         "pk0",
1976         "pj0",
1977         "pj2",
1978         "pk2",
1979         "pi3",
1980         "pi6",
1981
1982         "pg0",
1983         "pg1",
1984         "pg2",
1985         "pg3",
1986         "pg4",
1987         "pg5",
1988         "pg6",
1989         "pg7",
1990
1991         "pi0",
1992         "pi1",
1993
1994         "gpio_x7_aud_px7",
1995
1996         "reset_out_n",
1997 };
1998
1999 static const char * const rsvd2_groups[] = {
2000         "pv0",
2001         "pv1",
2002
2003         "sdmmc1_dat0_py7",
2004         "clk2_out_pw5",
2005         "clk2_req_pcc5",
2006         "hdmi_int_pn7",
2007         "ddc_scl_pv4",
2008         "ddc_sda_pv5",
2009
2010         "uart3_txd_pw6",
2011         "uart3_rxd_pw7",
2012
2013         "gen1_i2c_scl_pc4",
2014         "gen1_i2c_sda_pc5",
2015
2016         "clk2_out_pee0",
2017         "clk2_req_pee1",
2018         "pc7",
2019         "pi5",
2020         "pj0",
2021         "pj2",
2022
2023         "pk4",
2024         "pk2",
2025         "pi3",
2026         "pi6",
2027         "pg0",
2028         "pg1",
2029         "pg5",
2030         "pg6",
2031         "pg7",
2032
2033         "ph4",
2034         "ph5",
2035         "pj7",
2036         "pb0",
2037         "pb1",
2038         "pk7",
2039         "pi0",
2040         "pi1",
2041
2042         "gen2_i2c_scl_pt5",
2043         "gen2_i2c_sda_pt6",
2044         "sdmmc4_clk_pcc4",
2045         "sdmmc4_cmd_pt7",
2046         "sdmmc4_dat7_paa7",
2047         "pcc1",
2048         "pbb6",
2049         "pbb7",
2050         "pcc2",
2051         "jtag_rtck",
2052
2053         "pwr_i2c_scl_pz6",
2054         "pwr_i2c_sda_pz7",
2055
2056         "kb_row0_pr0",
2057         "kb_row1_pr1",
2058         "kb_row2_pr2",
2059         "kb_row7_pr7",
2060         "kb_row8_ps0",
2061         "kb_row9_ps1",
2062         "kb_row10_ps2",
2063         "kb_row11_ps3",
2064         "kb_row12_ps4",
2065         "kb_row13_ps5",
2066         "kb_row14_ps6",
2067
2068         "kb_col0_pq0",
2069         "kb_col1_pq1",
2070         "kb_col2_pq2",
2071         "kb_col5_pq5",
2072         "kb_col6_pq6",
2073         "kb_col7_pq7",
2074
2075         "core_pwr_req",
2076         "cpu_pwr_req",
2077         "pwr_int_n",
2078         "clk_32k_in",
2079         "owr",
2080
2081         "spdif_in_pk6",
2082         "spdif_out_pk5",
2083         "gpio_x1_aud_px1",
2084
2085         "sdmmc3_clk_pa6",
2086         "sdmmc3_dat0_pb7",
2087
2088         "pex_l0_rst_n_pdd1",
2089         "pex_l0_clkreq_n_pdd2",
2090         "pex_wake_n_pdd3",
2091         "pex_l1_rst_n_pdd5",
2092         "pex_l1_clkreq_n_pdd6",
2093         "hdmi_cec_pee3",
2094
2095         "gpio_w2_aud_pw2",
2096         "usb_vbus_en0_pn4",
2097         "usb_vbus_en1_pn5",
2098         "sdmmc3_clk_lb_out_pee4",
2099         "sdmmc3_clk_lb_in_pee5",
2100         "gmi_clk_lb",
2101         "reset_out_n",
2102         "kb_row16_pt0",
2103         "kb_row17_pt1",
2104         "dp_hpd_pff0",
2105         "usb_vbus_en2_pff1",
2106         "pff2",
2107 };
2108
2109 static const char * const rsvd3_groups[] = {
2110         "dap3_sclk_pp3",
2111         "pv0",
2112         "pv1",
2113         "sdmmc1_clk_pz0",
2114         "clk2_out_pw5",
2115         "clk2_req_pcc5",
2116         "hdmi_int_pn7",
2117
2118         "ddc_scl_pv4",
2119         "ddc_sda_pv5",
2120
2121         "pu6",
2122
2123         "gen1_i2c_scl_pc4",
2124         "gen1_i2c_sda_pc5",
2125
2126         "dap4_din_pp5",
2127         "dap4_sclk_pp7",
2128
2129         "clk3_out_pee0",
2130         "clk3_req_pee1",
2131
2132         "sdmmc4_dat5_paa5",
2133         "gpio_pcc1",
2134         "cam_i2c_scl_pbb1",
2135         "cam_i2c_sda_pbb2",
2136         "pbb5",
2137         "pbb7",
2138         "jtag_rtck",
2139         "pwr_i2c_scl_pz6",
2140         "pwr_i2c_sda_pz7",
2141
2142         "kb_row0_pr0",
2143         "kb_row1_pr1",
2144         "kb_row2_pr2",
2145         "kb_row4_pr4",
2146         "kb_row5_pr5",
2147         "kb_row9_ps1",
2148         "kb_row10_ps2",
2149         "kb_row11_ps3",
2150         "kb_row12_ps4",
2151         "kb_row15_ps7",
2152
2153         "clk_32k_out_pa0",
2154         "core_pwr_req",
2155         "cpu_pwr_req",
2156         "pwr_int_n",
2157         "clk_32k_in",
2158         "owr",
2159
2160         "dap_mclk1_pw4",
2161         "spdif_in_pk6",
2162         "spdif_out_pk5",
2163         "sdmmc3_clk_pa6",
2164         "sdmmc3_dat0_pb7",
2165
2166         "pex_l0_rst_n_pdd1",
2167         "pex_l0_clkreq_n_pdd2",
2168         "pex_wake_n_pdd3",
2169         "pex_l1_rst_n_pdd5",
2170         "pex_l1_clkreq_n_pdd6",
2171         "hdmi_cec_pee3",
2172
2173         "sdmmc3_cd_n_pv2",
2174         "usb_vbus_en0_pn4",
2175         "usb_vbus_en1_pn5",
2176         "sdmmc3_clk_lb_out_pee4",
2177         "sdmmc3_clk_lb_in_pee5",
2178         "reset_out_n",
2179         "kb_row16_pt0",
2180         "kb_row17_pt1",
2181         "dp_hpd_pff0",
2182         "usb_vbus_en2_pff1",
2183         "pff2",
2184 };
2185
2186 static const char * const rsvd4_groups[] = {
2187         "dap3_dout_pp2",
2188         "pv0",
2189         "pv1",
2190         "sdmmc1_clk_pz0",
2191
2192         "clk2_out_pw5",
2193         "clk2_req_pcc5",
2194         "hdmi_int_pn7",
2195         "ddc_scl_pv4",
2196         "ddc_sda_pv5",
2197
2198         "uart2_rts_n_pj6",
2199         "uart2_cts_n_pj5",
2200         "uart3_txd_pw6",
2201         "uart3_rxd_pw7",
2202
2203         "pu0",
2204         "pu1",
2205         "pu2",
2206
2207         "gen1_i2c_scl_pc4",
2208         "gen1_i2c_sda_pc5",
2209
2210         "dap4_fs_pp4",
2211         "dap4_dout_pp6",
2212         "dap4_din_pp5",
2213         "dap4_sclk_pp7",
2214
2215         "clk3_out_pee0",
2216         "clk3_req_pee1",
2217
2218         "pi5",
2219         "pk1",
2220         "pk2",
2221         "pg0",
2222         "pg1",
2223         "pg2",
2224         "pg3",
2225         "ph4",
2226         "ph5",
2227         "pb0",
2228         "pb1",
2229         "pk7",
2230         "pi0",
2231         "pi1",
2232         "pi2",
2233
2234         "gen2_i2c_scl_pt5",
2235         "gen2_i2c_sda_pt6",
2236
2237         "sdmmc4_cmd_pt7",
2238         "sdmmc4_dat0_paa0",
2239         "sdmmc4_dat1_paa1",
2240         "sdmmc4_dat2_paa2",
2241         "sdmmc4_dat3_paa3",
2242         "sdmmc4_dat4_paa4",
2243         "sdmmc4_dat5_paa5",
2244         "sdmmc4_dat6_paa6",
2245         "sdmmc4_dat7_paa7",
2246
2247         "jtag_rtck",
2248         "pwr_i2c_scl_pz6",
2249         "pwr_i2c_sda_pz7",
2250
2251         "kb_row0_pr0",
2252         "kb_row1_pr1",
2253         "kb_row2_pr2",
2254         "kb_row13_ps5",
2255         "kb_row14_ps6",
2256         "kb_row15_ps7",
2257
2258         "kb_col0_pq0",
2259         "kb_col1_pq1",
2260         "kb_col2_pq2",
2261         "kb_col5_pq5",
2262
2263         "clk_32k_out_pa0",
2264         "core_pwr_req",
2265         "cpu_pwr_req",
2266         "pwr_int_n",
2267         "clk_32k_in",
2268         "owr",
2269
2270         "dap1_fs_pn0",
2271         "dap1_din_pn1",
2272         "dap1_sclk_pn3",
2273         "dap_mclk1_req_pee2",
2274         "dap_mclk1_pw5",
2275
2276         "dap2_fs_pa2",
2277         "dap2_din_pa4",
2278         "dap2_dout_pa5",
2279         "dap2_sclk_pa3",
2280
2281         "dvfs_pwm_px0",
2282         "dvfs_clk_px2",
2283         "gpio_x1_aud_px1",
2284         "gpio_x3_aud_px3",
2285
2286         "gpio_x5_aud_px5",
2287         "gpio_x7_aud_px7",
2288
2289         "pex_l0_rst_n_pdd1",
2290         "pex_l0_clkreq_n_pdd2",
2291         "pex_wake_n_pdd3",
2292         "pex_l1_rst_n_pdd5",
2293         "pex_l1_clkreq_n_pdd6",
2294         "hdmi_cec_pee3",
2295
2296         "sdmmc3_cd_n_pv2",
2297         "usb_vbus_en0_pn4",
2298         "usb_vbus_en1_pn5",
2299         "sdmmc3_clk_lb_out_pee4",
2300         "sdmmc3_clk_lb_in_pee5",
2301         "gmi_clk_lb",
2302
2303         "dp_hpd_pff0",
2304         "usb_vbus_en2_pff1",
2305         "pff2",
2306 };
2307
2308 static const char * const sdmmc1_groups[] = {
2309         "sdmmc1_clk_pz0",
2310         "sdmmc1_cmd_pz1",
2311         "sdmmc1_dat3_py4",
2312         "sdmmc1_dat2_py5",
2313         "sdmmc1_dat1_py6",
2314         "sdmmc1_dat0_py7",
2315         "clk2_out_pw5",
2316         "clk2_req_pcc",
2317         "uart3_cts_n_pa1",
2318         "sdmmc1_wp_n_pv3",
2319 };
2320
2321 static const char * const sdmmc2_groups[] = {
2322         "pi5",
2323         "pk1",
2324         "pk3",
2325         "pk4",
2326         "pi6",
2327         "ph4",
2328         "ph5",
2329         "ph6",
2330         "ph7",
2331         "pi2",
2332         "cam_mclk_pcc0",
2333         "pcc1",
2334         "pbb0",
2335         "cam_i2c_scl_pbb1",
2336         "cam_i2c_sda_pbb2",
2337         "pbb3",
2338         "pbb4",
2339         "pbb5",
2340         "pbb6",
2341         "pbb7",
2342         "pcc2",
2343         "gmi_clk_lb",
2344 };
2345
2346 static const char * const sdmmc3_groups[] = {
2347         "pk0",
2348         "pcc2",
2349
2350         "kb_col4_pq4",
2351         "kb_col5_pq5",
2352
2353         "sdmmc3_clk_pa6",
2354         "sdmmc3_cmd_pa7",
2355         "sdmmc3_dat0_pb7",
2356         "sdmmc3_dat1_pb6",
2357         "sdmmc3_dat2_pb5",
2358         "sdmmc3_dat3_pb4",
2359
2360         "sdmmc3_cd_n_pv2",
2361         "sdmmc3_clk_lb_in_pee5",
2362         "sdmmc3_clk_lb_out_pee4",
2363 };
2364
2365 static const char * const sdmmc4_groups[] = {
2366         "sdmmc4_clk_pcc4",
2367         "sdmmc4_cmd_pt7",
2368         "sdmmc4_dat0_paa0",
2369         "sdmmc4_dat1_paa1",
2370         "sdmmc4_dat2_paa2",
2371         "sdmmc4_dat3_paa3",
2372         "sdmmc4_dat4_paa4",
2373         "sdmmc4_dat5_paa5",
2374         "sdmmc4_dat6_paa6",
2375         "sdmmc4_dat7_paa7",
2376 };
2377
2378 static const char * const soc_groups[] = {
2379         "pk0",
2380         "pj2",
2381         "kb_row15_ps7",
2382         "clk_32k_out_pa0",
2383 };
2384
2385 static const char * const spdif_groups[] = {
2386         "sdmmc1_cmd_pz1",
2387         "sdmmc1_dat3_py4",
2388         "uart2_rxd_pc3",
2389         "uart2_txd_pc2",
2390         "spdif_in_pk6",
2391         "spdif_out_pk5",
2392 };
2393
2394 static const char * const spi1_groups[] = {
2395         "ulpi_clk_py0",
2396         "ulpi_dir_py1",
2397         "ulpi_nxt_py2",
2398         "ulpi_stp_py3",
2399         "gpio_x3_aud_px3",
2400         "gpio_x4_aud_px4",
2401         "gpio_x5_aud_px5",
2402         "gpio_x6_aud_px6",
2403         "gpio_x7_aud_px7",
2404         "gpio_w3_aud_pw3",
2405 };
2406
2407 static const char * const spi2_groups[] = {
2408         "ulpi_data4_po5",
2409         "ulpi_data5_po6",
2410         "ulpi_data6_po7",
2411         "ulpi_data7_po0",
2412
2413         "kb_row13_ps5",
2414         "kb_row14_ps6",
2415         "kb_row15_ps7",
2416         "kb_col0_pq0",
2417         "kb_col1_pq1",
2418         "kb_col2_pq2",
2419         "kb_col6_pq6",
2420         "kb_col7_pq7",
2421         "gpio_x4_aud_px4",
2422         "gpio_x5_aud_px5",
2423         "gpio_x6_aud_px6",
2424         "gpio_x7_aud_px7",
2425         "gpio_w2_aud_pw2",
2426         "gpio_w3_aud_pw3",
2427 };
2428
2429 static const char * const spi3_groups[] = {
2430         "ulpi_data0_po1",
2431         "ulpi_data1_po2",
2432         "ulpi_data2_po3",
2433         "ulpi_data3_po4",
2434         "sdmmc4_dat0_paa0",
2435         "sdmmc4_dat1_paa1",
2436         "sdmmc4_dat2_paa2",
2437         "sdmmc4_dat3_paa3",
2438         "sdmmc4_dat4_paa4",
2439         "sdmmc4_dat5_paa5",
2440         "sdmmc4_dat6_paa6",
2441         "sdmmc3_clk_pa6",
2442         "sdmmc3_cmd_pa7",
2443         "sdmmc3_dat0_pb7",
2444         "sdmmc3_dat1_pb6",
2445         "sdmmc3_dat2_pb5",
2446         "sdmmc3_dat3_pb4",
2447 };
2448
2449 static const char * const spi4_groups[] = {
2450         "sdmmc1_cmd_pz1",
2451         "sdmmc1_dat3_py4",
2452         "sdmmc1_dat2_py5",
2453         "sdmmc1_dat1_py6",
2454         "sdmmc1_dat0_py7",
2455
2456         "uart2_rxd_pc3",
2457         "uart2_txd_pc2",
2458         "uart2_rts_n_pj6",
2459         "uart2_cts_n_pj5",
2460         "uart3_txd_pw6",
2461         "uart3_rxd_pw7",
2462
2463         "pi3",
2464         "pg4",
2465         "pg5",
2466         "pg6",
2467         "pg7",
2468         "ph3",
2469         "pi4",
2470         "sdmmc1_wp_n_pv3",
2471 };
2472
2473 static const char * const spi5_groups[] = {
2474         "ulpi_clk_py0",
2475         "ulpi_dir_py1",
2476         "ulpi_nxt_py2",
2477         "ulpi_stp_py3",
2478         "dap3_fs_pp0",
2479         "dap3_din_pp1",
2480         "dap3_dout_pp2",
2481         "dap3_sclk_pp3",
2482 };
2483
2484 static const char * const spi6_groups[] = {
2485         "dvfs_pwm_px0",
2486         "gpio_x1_aud_px1",
2487         "gpio_x3_aud_px3",
2488         "dvfs_clk_px2",
2489         "gpio_x6_aud_px6",
2490         "gpio_w2_aud_pw2",
2491         "gpio_w3_aud_pw3",
2492 };
2493
2494 static const char * const trace_groups[] = {
2495         "pi2",
2496         "pi4",
2497         "pi7",
2498         "ph0",
2499         "ph6",
2500         "ph7",
2501         "pg2",
2502         "pg3",
2503         "pk1",
2504         "pk3",
2505 };
2506
2507 static const char * const uarta_groups[] = {
2508         "ulpi_data0_po1",
2509         "ulpi_data1_po2",
2510         "ulpi_data2_po3",
2511         "ulpi_data3_po4",
2512         "ulpi_data4_po5",
2513         "ulpi_data5_po6",
2514         "ulpi_data6_po7",
2515         "ulpi_data7_po0",
2516
2517         "sdmmc1_cmd_pz1",
2518         "sdmmc1_dat3_py4",
2519         "sdmmc1_dat2_py5",
2520         "sdmmc1_dat1_py6",
2521         "sdmmc1_dat0_py7",
2522
2523
2524         "uart2_rxd_pc3",
2525         "uart2_txd_pc2",
2526         "uart2_rts_n_pj6",
2527         "uart2_cts_n_pj5",
2528
2529         "pu0",
2530         "pu1",
2531         "pu2",
2532         "pu3",
2533         "pu4",
2534         "pu5",
2535         "pu6",
2536
2537         "kb_row7_pr7",
2538         "kb_row8_ps0",
2539         "kb_row9_ps1",
2540         "kb_row10_ps2",
2541         "kb_col3_pq3",
2542         "kb_col4_pq4",
2543
2544         "sdmmc3_cmd_pa7",
2545         "sdmmc3_dat1_pb6",
2546         "sdmmc1_wp_n_pv3",
2547
2548 };
2549
2550 static const char * const uartb_groups[] = {
2551         "uart2_rts_n_pj6",
2552         "uart2_cts_n_pj5",
2553 };
2554
2555 static const char * const uartc_groups[] = {
2556         "uart3_txd_pw6",
2557         "uart3_rxd_pw7",
2558         "uart3_cts_n_pa1",
2559         "uart3_rts_n_pc0",
2560         "kb_row16_pt0",
2561         "kn_row17_pt1",
2562 };
2563
2564 static const char * const uartd_groups[] = {
2565         "ulpi_clk_py0",
2566         "ulpi_dir_py1",
2567         "ulpi_nxt_py2",
2568         "ulpi_stp_py3",
2569         "pj7",
2570         "pb0",
2571         "pb1",
2572         "pk7",
2573         "kb_col6_pq6",
2574         "kb_col7_pq7",
2575 };
2576
2577 static const char * const ulpi_groups[] = {
2578         "ulpi_data0_po1",
2579         "ulpi_data1_po2",
2580         "ulpi_data2_po3",
2581         "ulpi_data3_po4",
2582         "ulpi_data4_po5",
2583         "ulpi_data5_po6",
2584         "ulpi_data6_po7",
2585         "ulpi_data7_po0",
2586         "ulpi_clk_py0",
2587         "ulpi_dir_py1",
2588         "ulpi_nxt_py2",
2589         "ulpi_stp_py3",
2590 };
2591
2592 static const char * const usb_groups[] = {
2593         "pj0",
2594         "usb_vbus_en0_pn4",
2595         "usb_vbus_en1_pn5",
2596         "usb_vbus_en2_pff1",
2597 };
2598
2599 static const char * const vgp1_groups[] = {
2600         "cam_i2c_scl_pbb1",
2601 };
2602
2603 static const char * const vgp2_groups[] = {
2604         "cam_i2c_sda_pbb2",
2605 };
2606
2607 static const char * const vgp3_groups[] = {
2608         "pbb3",
2609 };
2610
2611 static const char * const vgp4_groups[] = {
2612         "pbb4",
2613 };
2614
2615 static const char * const vgp5_groups[] = {
2616         "pbb5",
2617 };
2618
2619 static const char * const vgp6_groups[] = {
2620         "pbb0",
2621 };
2622
2623 static const char * const vi_groups[] = {
2624         "cam_mclk_pcc0",
2625 };
2626
2627 static const char * const vi_alt1_groups[] = {
2628         "cam_mclk_pcc0",
2629 };
2630
2631 static const char * const vi_alt3_groups[] = {
2632         "cam_mclk_pcc0",
2633 };
2634
2635 static const char * const vimclk2_groups[] = {
2636         "pbb0",
2637 };
2638
2639 static const char * const vimclk2_alt_groups[] = {
2640         "pbb0",
2641 };
2642
2643 static const char * const sata_groups[] = {
2644         "dap_mclk1_req_pee2",
2645         "dap1_dout_pn2",
2646         "pff2",
2647 };
2648
2649 static const char * const ccla_groups[] = {
2650         "pk3",
2651 };
2652
2653 static const char * const rtck_groups[] = {
2654         "jtag_rtck",
2655 };
2656
2657 static const char * const sys_groups[] = {
2658         "kb_row3_pr3",
2659 };
2660
2661 static const char * const pe0_groups[] = {
2662         "pex_l0_rst_n_pdd1",
2663         "pex_l0_clkreq_n_pdd2",
2664 };
2665
2666 static const char * const pe_groups[] = {
2667         "pex_wake_n_pdd3",
2668 };
2669
2670 static const char * const pe1_groups[] = {
2671         "pex_l1_rst_n_pdd5",
2672         "pex_l1_clkreq_n_pdd6",
2673 };
2674
2675 static const char * const dp_groups[] = {
2676         "dp_hpd_pff0",
2677 };
2678
2679 static const char * const clk_groups[] = {
2680         "clk_32k_in",
2681 };
2682
2683 static const char * const tmds_groups[] = {
2684         "pg4",
2685         "ph1",
2686         "ph2",
2687 };
2688
2689 #define FUNCTION(fname)                                 \
2690         {                                               \
2691                 .name = #fname,                         \
2692                 .groups = fname##_groups,               \
2693                 .ngroups = ARRAY_SIZE(fname##_groups),  \
2694         }
2695
2696 static const struct tegra_function tegra124_functions[] = {
2697         FUNCTION(blink),
2698         FUNCTION(cec),
2699         FUNCTION(cldvfs),
2700         FUNCTION(clk12),
2701         FUNCTION(cpu),
2702         FUNCTION(dap),
2703         FUNCTION(dap1),
2704         FUNCTION(dap2),
2705         FUNCTION(dev3),
2706         FUNCTION(displaya),
2707         FUNCTION(displaya_alt),
2708         FUNCTION(displayb),
2709         FUNCTION(dtv),
2710         FUNCTION(extperiph1),
2711         FUNCTION(extperiph2),
2712         FUNCTION(extperiph3),
2713         FUNCTION(gmi),
2714         FUNCTION(gmi_alt),
2715         FUNCTION(hda),
2716         FUNCTION(hsi),
2717         FUNCTION(i2c1),
2718         FUNCTION(i2c2),
2719         FUNCTION(i2c3),
2720         FUNCTION(i2c4),
2721         FUNCTION(i2cpwr),
2722         FUNCTION(i2s0),
2723         FUNCTION(i2s1),
2724         FUNCTION(i2s2),
2725         FUNCTION(i2s3),
2726         FUNCTION(i2s4),
2727         FUNCTION(irda),
2728         FUNCTION(kbc),
2729         FUNCTION(owr),
2730         FUNCTION(pmi),
2731         FUNCTION(pwm0),
2732         FUNCTION(pwm1),
2733         FUNCTION(pwm2),
2734         FUNCTION(pwm3),
2735         FUNCTION(pwron),
2736         FUNCTION(reset_out_n),
2737         FUNCTION(rsvd1),
2738         FUNCTION(rsvd2),
2739         FUNCTION(rsvd3),
2740         FUNCTION(rsvd4),
2741         FUNCTION(sdmmc1),
2742         FUNCTION(sdmmc2),
2743         FUNCTION(sdmmc3),
2744         FUNCTION(sdmmc4),
2745         FUNCTION(soc),
2746         FUNCTION(spdif),
2747         FUNCTION(spi1),
2748         FUNCTION(spi2),
2749         FUNCTION(spi3),
2750         FUNCTION(spi4),
2751         FUNCTION(spi5),
2752         FUNCTION(spi6),
2753         FUNCTION(trace),
2754         FUNCTION(uarta),
2755         FUNCTION(uartb),
2756         FUNCTION(uartc),
2757         FUNCTION(uartd),
2758         FUNCTION(ulpi),
2759         FUNCTION(usb),
2760         FUNCTION(vgp1),
2761         FUNCTION(vgp2),
2762         FUNCTION(vgp3),
2763         FUNCTION(vgp4),
2764         FUNCTION(vgp5),
2765         FUNCTION(vgp6),
2766         FUNCTION(vi),
2767         FUNCTION(vi_alt1),
2768         FUNCTION(vi_alt3),
2769         FUNCTION(vimclk2),
2770         FUNCTION(vimclk2_alt),
2771         FUNCTION(sata),
2772         FUNCTION(ccla),
2773         FUNCTION(pe0),
2774         FUNCTION(pe),
2775         FUNCTION(pe1),
2776         FUNCTION(dp),
2777         FUNCTION(rtck),
2778         FUNCTION(sys),
2779         FUNCTION(clk),
2780         FUNCTION(tmds),
2781 };
2782
2783 #define DRV_PINGROUP_REG_A      0x868   /* bank 0 */
2784 #define PINGROUP_REG_A          0x3000  /* bank 1 */
2785
2786 #define PINGROUP_REG_Y(r)       ((r) - PINGROUP_REG_A)
2787 #define PINGROUP_REG_N(r)       -1
2788
2789 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel)  \
2790         {                                                               \
2791                 .name = #pg_name,                                       \
2792                 .pins = pg_name##_pins,                                 \
2793                 .npins = ARRAY_SIZE(pg_name##_pins),                    \
2794                 .funcs = {                                              \
2795                         TEGRA_MUX_ ## f0,                               \
2796                         TEGRA_MUX_ ## f1,                               \
2797                         TEGRA_MUX_ ## f2,                               \
2798                         TEGRA_MUX_ ## f3,                               \
2799                 },                                                      \
2800                 .func_safe = TEGRA_MUX_ ## f_safe,                      \
2801                 .mux_reg = PINGROUP_REG_Y(r),                           \
2802                 .mux_bank = 1,                                          \
2803                 .mux_bit = 0,                                           \
2804                 .pupd_reg = PINGROUP_REG_Y(r),                          \
2805                 .pupd_bank = 1,                                         \
2806                 .pupd_bit = 2,                                          \
2807                 .tri_reg = PINGROUP_REG_Y(r),                           \
2808                 .tri_bank = 1,                                          \
2809                 .tri_bit = 4,                                           \
2810                 .einput_reg = PINGROUP_REG_Y(r),                        \
2811                 .einput_bank = 1,                                       \
2812                 .einput_bit = 5,                                        \
2813                 .odrain_reg = PINGROUP_REG_##od(r),                     \
2814                 .odrain_bank = 1,                                       \
2815                 .odrain_bit = 6,                                        \
2816                 .lock_reg = PINGROUP_REG_Y(r),                          \
2817                 .lock_bank = 1,                                         \
2818                 .lock_bit = 7,                                          \
2819                 .ioreset_reg = PINGROUP_REG_##ior(r),                   \
2820                 .ioreset_bank = 1,                                      \
2821                 .ioreset_bit = 8,                                       \
2822                 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r),               \
2823                 .rcv_sel_bank = 1,                                      \
2824                 .rcv_sel_bit = 9,                                       \
2825                 .drv_reg = -1,                                          \
2826                 .drvtype_reg = -1,                                      \
2827         }
2828
2829 #define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
2830 #define DRV_PINGROUP_DVRTYPE_N(r) -1
2831
2832 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,              \
2833                      drvdn_b, drvdn_w, drvup_b, drvup_w,                \
2834                      slwr_b, slwr_w, slwf_b, slwf_w,                    \
2835                      drvtype)                                           \
2836         {                                                               \
2837                 .name = "drive_" #pg_name,                              \
2838                 .pins = drive_##pg_name##_pins,                         \
2839                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),            \
2840                 .mux_reg = -1,                                          \
2841                 .pupd_reg = -1,                                         \
2842                 .tri_reg = -1,                                          \
2843                 .einput_reg = -1,                                       \
2844                 .odrain_reg = -1,                                       \
2845                 .lock_reg = -1,                                         \
2846                 .ioreset_reg = -1,                                      \
2847                 .rcv_sel_reg = -1,                                      \
2848                 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r),                   \
2849                 .drv_bank = 0,                                          \
2850                 .hsm_bit = hsm_b,                                       \
2851                 .schmitt_bit = schmitt_b,                               \
2852                 .lpmd_bit = lpmd_b,                                     \
2853                 .drvdn_bit = drvdn_b,                                   \
2854                 .drvdn_width = drvdn_w,                                 \
2855                 .drvup_bit = drvup_b,                                   \
2856                 .drvup_width = drvup_w,                                 \
2857                 .slwr_bit = slwr_b,                                     \
2858                 .slwr_width = slwr_w,                                   \
2859                 .slwf_bit = slwf_b,                                     \
2860                 .slwf_width = slwf_w,                                   \
2861                 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r),       \
2862                 .drvtype_bank = 0,                                      \
2863                 .drvtype_bit = 6,                                       \
2864         }
2865
2866 static const struct tegra_pingroup tegra124_groups[] = {
2867        /*       pg_name,                f0,         f1,         f2,           f3,          safe,       r,      od, ior, rcv_sel */
2868        PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3000,  N,  N,  N),
2869        PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3004,  N,  N,  N),
2870        PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3008,  N,  N,  N),
2871        PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x300c,  N,  N,  N),
2872        PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3010,  N,  N,  N),
2873        PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3014,  N,  N,  N),
2874        PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3018,  N,  N,  N),
2875        PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x301c,  N,  N,  N),
2876        PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3020,  N,  N,  N),
2877        PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3024,  N,  N,  N),
2878        PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3028,  N,  N,  N),
2879        PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x302c,  N,  N,  N),
2880        PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,       0x3030,  N,  N,  N),
2881        PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,       0x3034,  N,  N,  N),
2882        PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     RSVD4,       I2S2,       0x3038,  N,  N,  N),
2883        PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       RSVD3,        DISPLAYB,    I2S2,       0x303c,  N,  N,  N),
2884        PINGROUP(pv0,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3040,  N,  N,  N),
2885        PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3044,  N,  N,  N),
2886        PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       RSVD3,      0x3048,  N,  N,  N),
2887        PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,     0x304c,  N,  N,  N),
2888        PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,     0x3050,  N,  N,  N),
2889        PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       SDMMC1,     0x3054,  N,  N,  N),
2890        PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       SDMMC1,     0x3058,  N,  N,  N),
2891        PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       SDMMC1,     0x305c,  N,  N,  N),
2892        PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       EXTPERIPH2, 0x3068,  N,  N,  N),
2893        PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       DAP,        0x306c,  N,  N,  N),
2894        PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3110,  N,  N,  Y),
2895        PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       I2C4,       0x3114,  N,  N,  Y),
2896        PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       I2C4,       0x3118,  N,  N,  Y),
2897        PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,       0x3164,  N,  N,  N),
2898        PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,       0x3168,  N,  N,  N),
2899        PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      GMI,          SPI4,        UARTA,      0x316c,  N,  N,  N),
2900        PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      GMI,          SPI4,        UARTA,      0x3170,  N,  N,  N),
2901        PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      GMI,          SPI4,        UARTC,      0x3174,  N,  N,  N),
2902        PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      GMI,          SPI4,        UARTC,      0x3178,  N,  N,  N),
2903        PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          GMI,         UARTC,      0x317c,  N,  N,  N),
2904        PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          GMI,         UARTC,      0x3180,  N,  N,  N),
2905        PINGROUP(pu0,                    OWR,        UARTA,      GMI,          RSVD4,       RSVD4,      0x3184,  N,  N,  N),
2906        PINGROUP(pu1,                    RSVD1,      UARTA,      GMI,          RSVD4,       RSVD4,      0x3188,  N,  N,  N),
2907        PINGROUP(pu2,                    RSVD1,      UARTA,      GMI,          RSVD4,       RSVD4,      0x318c,  N,  N,  N),
2908        PINGROUP(pu3,                    PWM0,       UARTA,      GMI,          DISPLAYB,    PWM0,       0x3190,  N,  N,  N),
2909        PINGROUP(pu4,                    PWM1,       UARTA,      GMI,          DISPLAYB,    PWM1,       0x3194,  N,  N,  N),
2910        PINGROUP(pu5,                    PWM2,       UARTA,      GMI,          DISPLAYB,    PWM2,       0x3198,  N,  N,  N),
2911        PINGROUP(pu6,                    PWM3,       UARTA,      RSVD3,        GMI,         RSVD3,      0x319c,  N,  N,  N),
2912        PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       I2C1,       0x31a0,  Y,  N,  N),
2913        PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       I2C1,       0x31a4,  Y,  N,  N),
2914        PINGROUP(dap4_fs_pp4,            I2S3,       GMI,        DTV,          RSVD4,       I2S3,       0x31a8,  N,  N,  N),
2915        PINGROUP(dap4_din_pp5,           I2S3,       GMI,        RSVD3,        RSVD4,       I2S3,       0x31ac,  N,  N,  N),
2916        PINGROUP(dap4_dout_pp6,          I2S3,       GMI,        DTV,          RSVD4,       I2S3,       0x31b0,  N,  N,  N),
2917        PINGROUP(dap4_sclk_pp7,          I2S3,       GMI,        RSVD3,        RSVD4,       I2S3,       0x31b4,  N,  N,  N),
2918        PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       RSVD3,      0x31b8,  N,  N,  N),
2919        PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x31bc,  N,  N,  N),
2920        PINGROUP(pc7,                    RSVD1,      RSVD2,      GMI,          GMI_ALT,     RSVD1,      0x31c0,  N,  N,  N),
2921        PINGROUP(pi5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x31c4,  N,  N,  N),
2922        PINGROUP(pi7,                    RSVD1,      TRACE,      GMI,          DTV,         RSVD1,      0x31c8,  N,  N,  N),
2923        PINGROUP(pk0,                    RSVD1,      SDMMC3,     GMI,          SOC,         RSVD1,      0x31cc,  N,  N,  N),
2924        PINGROUP(pk1,                    SDMMC2,     TRACE,      GMI,          RSVD4,       GMI,        0x31d0,  N,  N,  N),
2925        PINGROUP(pj0,                    RSVD1,      RSVD2,      GMI,          USB,         RSVD1,      0x31d4,  N,  N,  N),
2926        PINGROUP(pj2,                    RSVD1,      RSVD2,      GMI,          SOC,         RSVD1,      0x31d8,  N,  N,  N),
2927        PINGROUP(pk3,                    SDMMC2,     TRACE,      GMI,          CCLA,        GMI,        0x31dc,  N,  N,  N),
2928        PINGROUP(pk4,                    SDMMC2,     RSVD2,      GMI,          GMI_ALT,     GMI,        0x31e0,  N,  N,  N),
2929        PINGROUP(pk2,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31e4,  N,  N,  N),
2930        PINGROUP(pi3,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x31e8,  N,  N,  N),
2931        PINGROUP(pi6,                    RSVD1,      RSVD2,      GMI,          SDMMC2,      RSVD1,      0x31ec,  N,  N,  N),
2932        PINGROUP(pg0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31f0,  N,  N,  N),
2933        PINGROUP(pg1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31f4,  N,  N,  N),
2934        PINGROUP(pg2,                    RSVD1,      TRACE,      GMI,          RSVD4,       RSVD4,      0x31f8,  N,  N,  N),
2935        PINGROUP(pg3,                    RSVD1,      TRACE,      GMI,          RSVD4,       RSVD4,      0x31fc,  N,  N,  N),
2936        PINGROUP(pg4,                    RSVD1,      TMDS,       GMI,          SPI4,        RSVD1,      0x3200,  N,  N,  N),
2937        PINGROUP(pg5,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x3204,  N,  N,  N),
2938        PINGROUP(pg6,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x3208,  N,  N,  N),
2939        PINGROUP(pg7,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x320c,  N,  N,  N),
2940        PINGROUP(ph0,                    PWM0,       TRACE,      GMI,          DTV,         GMI,        0x3210,  N,  N,  N),
2941        PINGROUP(ph1,                    PWM1,       TMDS,       GMI,          DISPLAYA,    GMI,        0x3214,  N,  N,  N),
2942        PINGROUP(ph2,                    PWM2,       TMDS,       GMI,          CLDVFS,      GMI,        0x3218,  N,  N,  N),
2943        PINGROUP(ph3,                    PWM3,       SPI4,       GMI,          CLDVFS,      GMI,        0x321c,  N,  N,  N),
2944        PINGROUP(ph4,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x3220,  N,  N,  N),
2945        PINGROUP(ph5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x3224,  N,  N,  N),
2946        PINGROUP(ph6,                    SDMMC2,     TRACE,      GMI,          DTV,         GMI,        0x3228,  N,  N,  N),
2947        PINGROUP(ph7,                    SDMMC2,     TRACE,      GMI,          DTV,         GMI,        0x322c,  N,  N,  N),
2948        PINGROUP(pj7,                    UARTD,      RSVD2,      GMI,          GMI_ALT,     RSVD2,      0x3230,  N,  N,  N),
2949        PINGROUP(pb0,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x3234,  N,  N,  N),
2950        PINGROUP(pb1,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x3238,  N,  N,  N),
2951        PINGROUP(pk7,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x323c,  N,  N,  N),
2952        PINGROUP(pi0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x3240,  N,  N,  N),
2953        PINGROUP(pi1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD1,      0x3244,  N,  N,  N),
2954        PINGROUP(pi2,                    SDMMC2,     TRACE,      GMI,          RSVD4,       GMI,        0x3248,  N,  N,  N),
2955        PINGROUP(pi4,                    SPI4,       TRACE,      GMI,          DISPLAYA,    GMI,        0x324c,  N,  N,  N),
2956        PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD2,      0x3250,  Y,  N,  N),
2957        PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD2,      0x3254,  Y,  N,  N),
2958        PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD2,      0x3258,  N,  Y,  N),
2959        PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD2,      0x325c,  N,  Y,  N),
2960        PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3260,  N,  Y,  N),
2961        PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3264,  N,  Y,  N),
2962        PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3268,  N,  Y,  N),
2963        PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x326c,  N,  Y,  N),
2964        PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3270,  N,  Y,  N),
2965        PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       RSVD3,        RSVD4,       SDMMC4,     0x3274,  N,  Y,  N),
2966        PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3278,  N,  Y,  N),
2967        PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD1,      GMI,          RSVD4,       SDMMC4,     0x327c,  N,  Y,  N),
2968        PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      SDMMC2,      VI,         0x3284,  N,  N,  N),
2969        PINGROUP(pcc1,                   I2S4,       RSVD1,      RSVD3,        SDMMC2,      I2S4,       0x3288,  N,  N,  N),
2970        PINGROUP(pbb0,                   VGP6,       VIMCLK2,    SDMMC2,       VIMCLK2_ALT, VGP6,       0x328c,  N,  N,  N),
2971        PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        SDMMC2,      VGP1,       0x3290,  Y,  N,  N),
2972        PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        SDMMC2,      VGP2,       0x3294,  Y,  N,  N),
2973        PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     SDMMC2,      VGP3,       0x3298,  N,  N,  N),
2974        PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     SDMMC2,      VGP4,       0x329c,  N,  N,  N),
2975        PINGROUP(pbb5,                   VGP5,       DISPLAYA,   RSVD3,        SDMMC2,      VGP5,       0x32a0,  N,  N,  N),
2976        PINGROUP(pbb6,                   I2S4,       RSVD2,      DISPLAYB,     SDMMC2,      I2S4,       0x32a4,  N,  N,  N),
2977        PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      I2S4,       0x32a8,  N,  N,  N),
2978        PINGROUP(pcc2,                   I2S4,       RSVD2,      SDMMC3,       SDMMC2,      I2S4,       0x32ac,  N,  N,  N),
2979        PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       RTCK,       0x32b0,  N,  N,  N),
2980        PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x32b4,  Y,  N,  N),
2981        PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x32b8,  Y,  N,  N),
2982        PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32bc,  N,  N,  N),
2983        PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32c0,  N,  N,  N),
2984        PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32c4,  N,  N,  N),
2985        PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   SYS,          DISPLAYB,    KBC,        0x32c8,  N,  N,  N),
2986        PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    RSVD3,      0x32cc,  N,  N,  N),
2987        PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    RSVD3,      0x32d0,  N,  N,  N),
2988        PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    KBC,        0x32d4,  N,  N,  N),
2989        PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,      0x32d8,  N,  N,  N),
2990        PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,      0x32dc,  N,  N,  N),
2991        PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       KBC,        0x32e0,  N,  N,  N),
2992        PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       KBC,        0x32e4,  N,  N,  N),
2993        PINGROUP(kb_row11_ps3,           KBC,        RSVD2,      RSVD3,        IRDA,        RSVD3,      0x32e8,  N,  N,  N),
2994        PINGROUP(kb_row12_ps4,           KBC,        RSVD2,      RSVD3,        IRDA,        RSVD3,      0x32ec,  N,  N,  N),
2995        PINGROUP(kb_row13_ps5,           KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32f0,  N,  N,  N),
2996        PINGROUP(kb_row14_ps6,           KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32f4,  N,  N,  N),
2997        PINGROUP(kb_row15_ps7,           KBC,        SOC,        RSVD3,        RSVD4,       KBC,        0x32f8,  N,  N,  N),
2998        PINGROUP(kb_col0_pq0,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32fc,  N,  N,  N),
2999        PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x3300,  N,  N,  N),
3000        PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x3304,  N,  N,  N),
3001        PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       KBC,        0x3308,  N,  N,  N),
3002        PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       KBC,        0x330c,  N,  N,  N),
3003        PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC3,       RSVD4,       RSVD4,      0x3310,  N,  N,  N),
3004        PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         UARTD,       RSVD2,      0x3314,  N,  N,  N),
3005        PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         UARTD,       RSVD2,      0x3318,  N,  N,  N),
3006        PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       RSVD3,      0x331c,  N,  N,  N),
3007        PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3324,  N,  N,  N),
3008        PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3328,  N,  N,  N),
3009        PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x332c,  N,  N,  N),
3010        PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3330,  N,  N,  N),
3011        PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3334,  N,  N,  Y),
3012        PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       RSVD4,      0x3338,  N,  N,  N),
3013        PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       RSVD4,      0x333c,  N,  N,  N),
3014        PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          SATA,        I2S0,       0x3340,  N,  N,  N),
3015        PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       I2S0,       0x3344,  N,  N,  N),
3016        PINGROUP(dap_mclk1_req_pee2,     DAP,        DAP1,       SATA,         RSVD4,       DAP,        0x3348,  N,  N,  N),
3017        PINGROUP(dap_mclk1_pw4,          EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       RSVD3,      0x334c,  N,  N,  N),
3018        PINGROUP(spdif_in_pk6,           SPDIF,      RSVD2,      RSVD3,        I2C3,        RSVD3,      0x3350,  N,  N,  N),
3019        PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        I2C3,        RSVD3,      0x3354,  N,  N,  N),
3020        PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3358,  N,  N,  N),
3021        PINGROUP(dap2_din_pa4,           I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x335c,  N,  N,  N),
3022        PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3360,  N,  N,  N),
3023        PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3364,  N,  N,  N),
3024        PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     GMI,          RSVD4,       SPI6,       0x3368,  N,  N,  N),
3025        PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      GMI,          RSVD4,       SPI6,       0x336c,  N,  N,  N),
3026        PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       GMI,          RSVD4,       SPI6,       0x3370,  N,  N,  N),
3027        PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     GMI,          RSVD4,       SPI6,       0x3374,  N,  N,  N),
3028        PINGROUP(gpio_x4_aud_px4,        GMI,        SPI1,       SPI2,         DAP2,        SPI1,       0x3378,  N,  N,  N),
3029        PINGROUP(gpio_x5_aud_px5,        GMI,        SPI1,       SPI2,         RSVD4,       SPI1,       0x337c,  N,  N,  N),
3030        PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         GMI,         SPI1,       0x3380,  N,  N,  N),
3031        PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       SPI1,       0x3384,  N,  N,  N),
3032        PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        SDMMC3,     0x3390,  N,  N,  N),
3033        PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        SDMMC3,     0x3394,  N,  N,  N),
3034        PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        SDMMC3,     0x3398,  N,  N,  N),
3035        PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        SDMMC3,     0x339c,  N,  N,  N),
3036        PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        SDMMC3,     0x33a0,  N,  N,  N),
3037        PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        SDMMC3,     0x33a4,  N,  N,  N),
3038        PINGROUP(pex_l0_rst_n_pdd1,      PE0,        RSVD2,      RSVD3,        RSVD4,       PE0,        0x33bc,  N,  N,  N),
3039        PINGROUP(pex_l0_clkreq_n_pdd2,   PE0,        RSVD2,      RSVD3,        RSVD4,       PE0,        0x33c0,  N,  N,  N),
3040        PINGROUP(pex_wake_n_pdd3,        PE,         RSVD2,      RSVD3,        RSVD4,       PE,         0x33c4,  N,  N,  N),
3041        PINGROUP(pex_l1_rst_n_pdd5,      PE1,        RSVD2,      RSVD3,        RSVD4,       PE1,        0x33cc,  N,  N,  N),
3042        PINGROUP(pex_l1_clkreq_n_pdd6,   PE1,        RSVD2,      RSVD3,        RSVD4,       PE1,        0x33d0,  N,  N,  N),
3043        PINGROUP(hdmi_cec_pee3,          CEC,        RSVD2,      RSVD3,        RSVD4,       CEC,        0x33e0,  Y,  N,  N),
3044        PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       SDMMC1,     0x33e4,  N,  N,  N),
3045        PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       SDMMC3,     0x33e8,  N,  N,  N),
3046        PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        RSVD2,      0x33ec,  N,  N,  N),
3047        PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        SPI1,       0x33f0,  N,  N,  N),
3048        PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x33f4,  Y,  N,  N),
3049        PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x33f8,  Y,  N,  N),
3050        PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       SDMMC3,     0x33fc,  N,  N,  N),
3051        PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       SDMMC3,     0x3400,  N,  N,  N),
3052        PINGROUP(gmi_clk_lb,             SDMMC2,     RSVD2,      GMI,          RSVD4,       SDMMC2,     0x3404,  N,  N,  N),
3053        PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, RSVD1,      0x3408,  N,  N,  N),
3054        PINGROUP(kb_row16_pt0,           KBC,        RSVD2,      RSVD3,        UARTC,       KBC,        0x340c,  N,  N,  N),
3055        PINGROUP(kb_row17_pt1,           KBC,        RSVD2,      RSVD3,        UARTC,       KBC,        0x3410,  N,  N,  N),
3056        PINGROUP(usb_vbus_en2_pff1,      USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x3414,  Y,  N,  N),
3057        PINGROUP(pff2,                   SATA,       RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3418,  Y,  N,  N),
3058        PINGROUP(dp_hpd_pff0,            DP,         RSVD2,      RSVD3,        RSVD4,       DP,         0x3430,  N,  N,  N),
3059
3060         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
3061        DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3062        DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3063        DRV_PINGROUP(at1,         0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3064        DRV_PINGROUP(at2,         0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3065        DRV_PINGROUP(at3,         0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3066        DRV_PINGROUP(at4,         0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3067        DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3068        DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3069        DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3070        DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3071        DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3072        DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3073        DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3074        DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3075        DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3076        DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3077        DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3078        DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3079        DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3080        DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3081        DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3082        DRV_PINGROUP(ddc,         0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3083        DRV_PINGROUP(gma,         0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
3084        DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3085        DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3086        DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3087        DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3088        DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3089        DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3090        DRV_PINGROUP(gpv,         0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3091        DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3092        DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3093        DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3094        DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3095        DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3096        DRV_PINGROUP(ao3,         0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
3097        DRV_PINGROUP(ao0,         0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3098        DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
3099        DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3100        DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3101 };
3102
3103 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
3104         .ngpios = NUM_GPIOS,
3105         .pins = tegra124_pins,
3106         .npins = ARRAY_SIZE(tegra124_pins),
3107         .functions = tegra124_functions,
3108         .nfunctions = ARRAY_SIZE(tegra124_functions),
3109         .groups = tegra124_groups,
3110         .ngroups = ARRAY_SIZE(tegra124_groups),
3111 };
3112
3113 static int tegra124_pinctrl_probe(struct platform_device *pdev)
3114 {
3115         return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
3116 }
3117
3118 static struct of_device_id tegra124_pinctrl_of_match[] = {
3119         { .compatible = "nvidia,tegra124-pinmux", },
3120         { },
3121 };
3122 MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
3123
3124 static struct platform_driver tegra124_pinctrl_driver = {
3125         .driver = {
3126                 .name = "tegra124-pinctrl",
3127                 .owner = THIS_MODULE,
3128                 .of_match_table = tegra124_pinctrl_of_match,
3129         },
3130         .probe = tegra124_pinctrl_probe,
3131         .remove = tegra_pinctrl_remove,
3132 };
3133 module_platform_driver(tegra124_pinctrl_driver);
3134
3135 MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
3136 MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
3137 MODULE_LICENSE("GPL v2");