drivers/clocksource/moxart_timer.c

   1 /*
   2  * MOXA ART SoCs timer handling.
   3  *
   4  * Copyright (C) 2013 Jonas Jensen
   5  *
   6  * Jonas Jensen <jonas.jensen@gmail.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/io.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/bitops.h>
  24
  25 #define TIMER1_BASE             0x00
  26 #define TIMER2_BASE             0x10
  27 #define TIMER3_BASE             0x20
  28
  29 #define REG_COUNT               0x0 /* writable */
  30 #define REG_LOAD                0x4
  31 #define REG_MATCH1              0x8
  32 #define REG_MATCH2              0xC
  33
  34 #define TIMER_CR                0x30
  35 #define TIMER_INTR_STATE        0x34
  36 #define TIMER_INTR_MASK         0x38
  37
  38 /*
  39  * TIMER_CR flags:
  40  *
  41  * TIMEREG_CR_*_CLOCK   0: PCLK, 1: EXT1CLK
  42  * TIMEREG_CR_*_INT     overflow interrupt enable bit
  43  */
  44 #define TIMEREG_CR_1_ENABLE     BIT(0)
  45 #define TIMEREG_CR_1_CLOCK      BIT(1)
  46 #define TIMEREG_CR_1_INT        BIT(2)
  47 #define TIMEREG_CR_2_ENABLE     BIT(3)
  48 #define TIMEREG_CR_2_CLOCK      BIT(4)
  49 #define TIMEREG_CR_2_INT        BIT(5)
  50 #define TIMEREG_CR_3_ENABLE     BIT(6)
  51 #define TIMEREG_CR_3_CLOCK      BIT(7)
  52 #define TIMEREG_CR_3_INT        BIT(8)
  53 #define TIMEREG_CR_COUNT_UP     BIT(9)
  54
  55 #define TIMER1_ENABLE           (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
  56 #define TIMER1_DISABLE          (TIMEREG_CR_2_ENABLE)
  57
  58 static void __iomem *base;
  59 static unsigned int clock_count_per_tick;
  60
  61 static void moxart_clkevt_mode(enum clock_event_mode mode,
  62                                struct clock_event_device *clk)
  63 {
  64         switch (mode) {
  65         case CLOCK_EVT_MODE_RESUME:
  66         case CLOCK_EVT_MODE_ONESHOT:
  67                 writel(TIMER1_DISABLE, base + TIMER_CR);
  68                 writel(~0, base + TIMER1_BASE + REG_LOAD);
  69                 break;
  70         case CLOCK_EVT_MODE_PERIODIC:
  71                 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
  72                 writel(TIMER1_ENABLE, base + TIMER_CR);
  73                 break;
  74         case CLOCK_EVT_MODE_UNUSED:
  75         case CLOCK_EVT_MODE_SHUTDOWN:
  76         default:
  77                 writel(TIMER1_DISABLE, base + TIMER_CR);
  78                 break;
  79         }
  80 }
  81
  82 static int moxart_clkevt_next_event(unsigned long cycles,
  83                                     struct clock_event_device *unused)
  84 {
  85         u32 u;
  86
  87         writel(TIMER1_DISABLE, base + TIMER_CR);
  88
  89         u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
  90         writel(u, base + TIMER1_BASE + REG_MATCH1);
  91
  92         writel(TIMER1_ENABLE, base + TIMER_CR);
  93
  94         return 0;
  95 }
  96
  97 static struct clock_event_device moxart_clockevent = {
  98         .name           = "moxart_timer",
  99         .rating         = 200,
 100         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 101         .set_mode       = moxart_clkevt_mode,
 102         .set_next_event = moxart_clkevt_next_event,
 103 };
 104
 105 static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
 106 {
 107         struct clock_event_device *evt = dev_id;
 108         evt->event_handler(evt);
 109         return IRQ_HANDLED;
 110 }
 111
 112 static struct irqaction moxart_timer_irq = {
 113         .name           = "moxart-timer",
 114         .flags          = IRQF_TIMER,
 115         .handler        = moxart_timer_interrupt,
 116         .dev_id         = &moxart_clockevent,
 117 };
 118
 119 static void __init moxart_timer_init(struct device_node *node)
 120 {
 121         int ret, irq;
 122         unsigned long pclk;
 123         struct clk *clk;
 124
 125         base = of_iomap(node, 0);
 126         if (!base)
 127                 panic("%s: of_iomap failed\n", node->full_name);
 128
 129         irq = irq_of_parse_and_map(node, 0);
 130         if (irq <= 0)
 131                 panic("%s: irq_of_parse_and_map failed\n", node->full_name);
 132
 133         ret = setup_irq(irq, &moxart_timer_irq);
 134         if (ret)
 135                 panic("%s: setup_irq failed\n", node->full_name);
 136
 137         clk = of_clk_get(node, 0);
 138         if (IS_ERR(clk))
 139                 panic("%s: of_clk_get failed\n", node->full_name);
 140
 141         pclk = clk_get_rate(clk);
 142
 143         if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,
 144                                   "moxart_timer", pclk, 200, 32,
 145                                   clocksource_mmio_readl_down))
 146                 panic("%s: clocksource_mmio_init failed\n", node->full_name);
 147
 148         clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
 149
 150         writel(~0, base + TIMER2_BASE + REG_LOAD);
 151         writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);
 152
 153         moxart_clockevent.cpumask = cpumask_of(0);
 154         moxart_clockevent.irq = irq;
 155
 156         /*
 157          * documentation is not publicly available:
 158          * min_delta / max_delta obtained by trial-and-error,
 159          * max_delta 0xfffffffe should be ok because count
 160          * register size is u32
 161          */
 162         clockevents_config_and_register(&moxart_clockevent, pclk,
 163                                         0x4, 0xfffffffe);
 164 }
 165 CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);