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staging: wfx: fix rate control handling
[linux/fpc-iii.git] / drivers / rtc / rtc-mxc.c
blob902d57dcd0d48ba46162d4b0e8adb8e39f2d4fd8
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
4
5 #include <linux/io.h>
6 #include <linux/rtc.h>
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_wakeirq.h>
12 #include <linux/clk.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15
16 #define RTC_INPUT_CLK_32768HZ (0x00 << 5)
17 #define RTC_INPUT_CLK_32000HZ (0x01 << 5)
18 #define RTC_INPUT_CLK_38400HZ (0x02 << 5)
19
20 #define RTC_SW_BIT (1 << 0)
21 #define RTC_ALM_BIT (1 << 2)
22 #define RTC_1HZ_BIT (1 << 4)
23 #define RTC_2HZ_BIT (1 << 7)
24 #define RTC_SAM0_BIT (1 << 8)
25 #define RTC_SAM1_BIT (1 << 9)
26 #define RTC_SAM2_BIT (1 << 10)
27 #define RTC_SAM3_BIT (1 << 11)
28 #define RTC_SAM4_BIT (1 << 12)
29 #define RTC_SAM5_BIT (1 << 13)
30 #define RTC_SAM6_BIT (1 << 14)
31 #define RTC_SAM7_BIT (1 << 15)
32 #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
33 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
34 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
35
36 #define RTC_ENABLE_BIT (1 << 7)
37
38 #define MAX_PIE_NUM 9
39 #define MAX_PIE_FREQ 512
40
41 #define MXC_RTC_TIME 0
42 #define MXC_RTC_ALARM 1
43
44 #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
45 #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
46 #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
47 #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
48 #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
49 #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
50 #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
51 #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
52 #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
53 #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
54 #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
55 #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
56 #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
57
58 enum imx_rtc_type {
59 IMX1_RTC,
60 IMX21_RTC,
61 };
62
63 struct rtc_plat_data {
64 struct rtc_device *rtc;
65 void __iomem *ioaddr;
66 int irq;
67 struct clk *clk_ref;
68 struct clk *clk_ipg;
69 struct rtc_time g_rtc_alarm;
70 enum imx_rtc_type devtype;
71 };
72
73 static const struct platform_device_id imx_rtc_devtype[] = {
74 {
75 .name = "imx1-rtc",
76 .driver_data = IMX1_RTC,
77 }, {
78 .name = "imx21-rtc",
79 .driver_data = IMX21_RTC,
80 }, {
81 /* sentinel */
82 }
83 };
84 MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
85
86 #ifdef CONFIG_OF
87 static const struct of_device_id imx_rtc_dt_ids[] = {
88 { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
89 { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
90 {}
91 };
92 MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
93 #endif
94
95 static inline int is_imx1_rtc(struct rtc_plat_data *data)
96 {
97 return data->devtype == IMX1_RTC;
98 }
99
100 /*
101 * This function is used to obtain the RTC time or the alarm value in
102 * second.
103 */
104 static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
105 {
106 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
107 void __iomem *ioaddr = pdata->ioaddr;
108 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
109
110 switch (time_alarm) {
111 case MXC_RTC_TIME:
112 day = readw(ioaddr + RTC_DAYR);
113 hr_min = readw(ioaddr + RTC_HOURMIN);
114 sec = readw(ioaddr + RTC_SECOND);
115 break;
116 case MXC_RTC_ALARM:
117 day = readw(ioaddr + RTC_DAYALARM);
118 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
119 sec = readw(ioaddr + RTC_ALRM_SEC);
120 break;
121 }
122
123 hr = hr_min >> 8;
124 min = hr_min & 0xff;
125
126 return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
127 }
128
129 /*
130 * This function sets the RTC alarm value or the time value.
131 */
132 static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
133 {
134 u32 tod, day, hr, min, sec, temp;
135 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
136 void __iomem *ioaddr = pdata->ioaddr;
137
138 day = div_s64_rem(time, 86400, &tod);
139
140 /* time is within a day now */
141 hr = tod / 3600;
142 tod -= hr * 3600;
143
144 /* time is within an hour now */
145 min = tod / 60;
146 sec = tod - min * 60;
147
148 temp = (hr << 8) + min;
149
150 switch (time_alarm) {
151 case MXC_RTC_TIME:
152 writew(day, ioaddr + RTC_DAYR);
153 writew(sec, ioaddr + RTC_SECOND);
154 writew(temp, ioaddr + RTC_HOURMIN);
155 break;
156 case MXC_RTC_ALARM:
157 writew(day, ioaddr + RTC_DAYALARM);
158 writew(sec, ioaddr + RTC_ALRM_SEC);
159 writew(temp, ioaddr + RTC_ALRM_HM);
160 break;
161 }
162 }
163
164 /*
165 * This function updates the RTC alarm registers and then clears all the
166 * interrupt status bits.
167 */
168 static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
169 {
170 time64_t time;
171 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
172 void __iomem *ioaddr = pdata->ioaddr;
173
174 time = rtc_tm_to_time64(alrm);
175
176 /* clear all the interrupt status bits */
177 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
178 set_alarm_or_time(dev, MXC_RTC_ALARM, time);
179 }
180
181 static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
182 unsigned int enabled)
183 {
184 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
185 void __iomem *ioaddr = pdata->ioaddr;
186 u32 reg;
187 unsigned long flags;
188
189 spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
190 reg = readw(ioaddr + RTC_RTCIENR);
191
192 if (enabled)
193 reg |= bit;
194 else
195 reg &= ~bit;
196
197 writew(reg, ioaddr + RTC_RTCIENR);
198 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
199 }
200
201 /* This function is the RTC interrupt service routine. */
202 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
203 {
204 struct platform_device *pdev = dev_id;
205 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
206 void __iomem *ioaddr = pdata->ioaddr;
207 unsigned long flags;
208 u32 status;
209 u32 events = 0;
210
211 spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
212 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
213 /* clear interrupt sources */
214 writew(status, ioaddr + RTC_RTCISR);
215
216 /* update irq data & counter */
217 if (status & RTC_ALM_BIT) {
218 events |= (RTC_AF | RTC_IRQF);
219 /* RTC alarm should be one-shot */
220 mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
221 }
222
223 if (status & PIT_ALL_ON)
224 events |= (RTC_PF | RTC_IRQF);
225
226 rtc_update_irq(pdata->rtc, 1, events);
227 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
228
229 return IRQ_HANDLED;
230 }
231
232 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
233 {
234 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
235 return 0;
236 }
237
238 /*
239 * This function reads the current RTC time into tm in Gregorian date.
240 */
241 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
242 {
243 time64_t val;
244
245 /* Avoid roll-over from reading the different registers */
246 do {
247 val = get_alarm_or_time(dev, MXC_RTC_TIME);
248 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
249
250 rtc_time64_to_tm(val, tm);
251
252 return 0;
253 }
254
255 /*
256 * This function sets the internal RTC time based on tm in Gregorian date.
257 */
258 static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
259 {
260 time64_t time = rtc_tm_to_time64(tm);
261
262 /* Avoid roll-over from reading the different registers */
263 do {
264 set_alarm_or_time(dev, MXC_RTC_TIME, time);
265 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
266
267 return 0;
268 }
269
270 /*
271 * This function reads the current alarm value into the passed in 'alrm'
272 * argument. It updates the alrm's pending field value based on the whether
273 * an alarm interrupt occurs or not.
274 */
275 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
276 {
277 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
278 void __iomem *ioaddr = pdata->ioaddr;
279
280 rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
281 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
282
283 return 0;
284 }
285
286 /*
287 * This function sets the RTC alarm based on passed in alrm.
288 */
289 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
290 {
291 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
292
293 rtc_update_alarm(dev, &alrm->time);
294
295 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
296 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
297
298 return 0;
299 }
300
301 /* RTC layer */
302 static const struct rtc_class_ops mxc_rtc_ops = {
303 .read_time = mxc_rtc_read_time,
304 .set_time = mxc_rtc_set_time,
305 .read_alarm = mxc_rtc_read_alarm,
306 .set_alarm = mxc_rtc_set_alarm,
307 .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
308 };
309
310 static int mxc_rtc_probe(struct platform_device *pdev)
311 {
312 struct rtc_device *rtc;
313 struct rtc_plat_data *pdata = NULL;
314 u32 reg;
315 unsigned long rate;
316 int ret;
317 const struct of_device_id *of_id;
318
319 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
320 if (!pdata)
321 return -ENOMEM;
322
323 of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
324 if (of_id)
325 pdata->devtype = (enum imx_rtc_type)of_id->data;
326 else
327 pdata->devtype = pdev->id_entry->driver_data;
328
329 pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
330 if (IS_ERR(pdata->ioaddr))
331 return PTR_ERR(pdata->ioaddr);
332
333 rtc = devm_rtc_allocate_device(&pdev->dev);
334 if (IS_ERR(rtc))
335 return PTR_ERR(rtc);
336
337 pdata->rtc = rtc;
338 rtc->ops = &mxc_rtc_ops;
339 if (is_imx1_rtc(pdata)) {
340 struct rtc_time tm;
341
342 /* 9bit days + hours minutes seconds */
343 rtc->range_max = (1 << 9) * 86400 - 1;
344
345 /*
346 * Set the start date as beginning of the current year. This can
347 * be overridden using device tree.
348 */
349 rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
350 rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0);
351 rtc->set_start_time = true;
352 } else {
353 /* 16bit days + hours minutes seconds */
354 rtc->range_max = (1 << 16) * 86400ULL - 1;
355 }
356
357 pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
358 if (IS_ERR(pdata->clk_ipg)) {
359 dev_err(&pdev->dev, "unable to get ipg clock!\n");
360 return PTR_ERR(pdata->clk_ipg);
361 }
362
363 ret = clk_prepare_enable(pdata->clk_ipg);
364 if (ret)
365 return ret;
366
367 pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
368 if (IS_ERR(pdata->clk_ref)) {
369 dev_err(&pdev->dev, "unable to get ref clock!\n");
370 ret = PTR_ERR(pdata->clk_ref);
371 goto exit_put_clk_ipg;
372 }
373
374 ret = clk_prepare_enable(pdata->clk_ref);
375 if (ret)
376 goto exit_put_clk_ipg;
377
378 rate = clk_get_rate(pdata->clk_ref);
379
380 if (rate == 32768)
381 reg = RTC_INPUT_CLK_32768HZ;
382 else if (rate == 32000)
383 reg = RTC_INPUT_CLK_32000HZ;
384 else if (rate == 38400)
385 reg = RTC_INPUT_CLK_38400HZ;
386 else {
387 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
388 ret = -EINVAL;
389 goto exit_put_clk_ref;
390 }
391
392 reg |= RTC_ENABLE_BIT;
393 writew(reg, (pdata->ioaddr + RTC_RTCCTL));
394 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
395 dev_err(&pdev->dev, "hardware module can't be enabled!\n");
396 ret = -EIO;
397 goto exit_put_clk_ref;
398 }
399
400 platform_set_drvdata(pdev, pdata);
401
402 /* Configure and enable the RTC */
403 pdata->irq = platform_get_irq(pdev, 0);
404
405 if (pdata->irq >= 0 &&
406 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
407 IRQF_SHARED, pdev->name, pdev) < 0) {
408 dev_warn(&pdev->dev, "interrupt not available.\n");
409 pdata->irq = -1;
410 }
411
412 if (pdata->irq >= 0) {
413 device_init_wakeup(&pdev->dev, 1);
414 ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
415 if (ret)
416 dev_err(&pdev->dev, "failed to enable irq wake\n");
417 }
418
419 ret = rtc_register_device(rtc);
420 if (ret)
421 goto exit_put_clk_ref;
422
423 return 0;
424
425 exit_put_clk_ref:
426 clk_disable_unprepare(pdata->clk_ref);
427 exit_put_clk_ipg:
428 clk_disable_unprepare(pdata->clk_ipg);
429
430 return ret;
431 }
432
433 static int mxc_rtc_remove(struct platform_device *pdev)
434 {
435 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
436
437 clk_disable_unprepare(pdata->clk_ref);
438 clk_disable_unprepare(pdata->clk_ipg);
439
440 return 0;
441 }
442
443 static struct platform_driver mxc_rtc_driver = {
444 .driver = {
445 .name = "mxc_rtc",
446 .of_match_table = of_match_ptr(imx_rtc_dt_ids),
447 },
448 .id_table = imx_rtc_devtype,
449 .probe = mxc_rtc_probe,
450 .remove = mxc_rtc_remove,
451 };
452
453 module_platform_driver(mxc_rtc_driver)
454
455 MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
456 MODULE_DESCRIPTION("RTC driver for Freescale MXC");
457 MODULE_LICENSE("GPL");
458
Linux with added FPC-III support