include/asm-ppc64/dma.h

   1 /*
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  * Changes for ppc sound by Christoph Nadig
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 #ifndef _ASM_DMA_H
  15 #define _ASM_DMA_H
  16
  17 #include <linux/config.h>
  18 #include <asm/io.h>
  19 #include <linux/spinlock.h>
  20 #include <asm/system.h>
  21
  22 #ifndef MAX_DMA_CHANNELS
  23 #define MAX_DMA_CHANNELS        8
  24 #endif
  25
  26 /* The maximum address that we can perform a DMA transfer to on this platform */
  27 /* Doesn't really apply... */
  28 #define MAX_DMA_ADDRESS  (~0UL)
  29
  30 #if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
  31
  32 #define dma_outb        outb
  33 #define dma_inb         inb
  34
  35 /*
  36  * NOTES about DMA transfers:
  37  *
  38  *  controller 1: channels 0-3, byte operations, ports 00-1F
  39  *  controller 2: channels 4-7, word operations, ports C0-DF
  40  *
  41  *  - ALL registers are 8 bits only, regardless of transfer size
  42  *  - channel 4 is not used - cascades 1 into 2.
  43  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  44  *  - channels 5-7 are word - addresses/counts are for physical words
  45  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  46  *  - transfer count loaded to registers is 1 less than actual count
  47  *  - controller 2 offsets are all even (2x offsets for controller 1)
  48  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  49  *  - page registers for 0-3 use bit 0, represent 64K pages
  50  *
  51  * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  52  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  53  * Note that addresses loaded into registers must be _physical_ addresses,
  54  * not logical addresses (which may differ if paging is active).
  55  *
  56  *  Address mapping for channels 0-3:
  57  *
  58  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  59  *    |  ...  |   |  ... |   |  ... |
  60  *    |  ...  |   |  ... |   |  ... |
  61  *    |  ...  |   |  ... |   |  ... |
  62  *   P7  ...  P0  A7 ... A0  A7 ... A0
  63  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  64  *
  65  *  Address mapping for channels 5-7:
  66  *
  67  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  68  *    |  ...  |   \   \   ... \  \  \  ... \  \
  69  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  70  *    |  ...  |     \   \   ... \  \  \  ... \
  71  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  72  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  73  *
  74  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  75  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  76  * the hardware level, so odd-byte transfers aren't possible).
  77  *
  78  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  79  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  80  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  81  *
  82  */
  83
  84 /* 8237 DMA controllers */
  85 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  86 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  87
  88 /* DMA controller registers */
  89 #define DMA1_CMD_REG            0x08    /* command register (w) */
  90 #define DMA1_STAT_REG           0x08    /* status register (r) */
  91 #define DMA1_REQ_REG            0x09    /* request register (w) */
  92 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  93 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  94 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  95 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  96 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  97 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  98 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
  99
 100 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 101 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 102 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 103 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 104 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 105 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 106 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 107 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 108 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 109 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 110
 111 #define DMA_ADDR_0              0x00    /* DMA address registers */
 112 #define DMA_ADDR_1              0x02
 113 #define DMA_ADDR_2              0x04
 114 #define DMA_ADDR_3              0x06
 115 #define DMA_ADDR_4              0xC0
 116 #define DMA_ADDR_5              0xC4
 117 #define DMA_ADDR_6              0xC8
 118 #define DMA_ADDR_7              0xCC
 119
 120 #define DMA_CNT_0               0x01    /* DMA count registers */
 121 #define DMA_CNT_1               0x03
 122 #define DMA_CNT_2               0x05
 123 #define DMA_CNT_3               0x07
 124 #define DMA_CNT_4               0xC2
 125 #define DMA_CNT_5               0xC6
 126 #define DMA_CNT_6               0xCA
 127 #define DMA_CNT_7               0xCE
 128
 129 #define DMA_LO_PAGE_0              0x87    /* DMA page registers */
 130 #define DMA_LO_PAGE_1              0x83
 131 #define DMA_LO_PAGE_2              0x81
 132 #define DMA_LO_PAGE_3              0x82
 133 #define DMA_LO_PAGE_5              0x8B
 134 #define DMA_LO_PAGE_6              0x89
 135 #define DMA_LO_PAGE_7              0x8A
 136
 137 #define DMA_HI_PAGE_0              0x487    /* DMA page registers */
 138 #define DMA_HI_PAGE_1              0x483
 139 #define DMA_HI_PAGE_2              0x481
 140 #define DMA_HI_PAGE_3              0x482
 141 #define DMA_HI_PAGE_5              0x48B
 142 #define DMA_HI_PAGE_6              0x489
 143 #define DMA_HI_PAGE_7              0x48A
 144
 145 #define DMA1_EXT_REG               0x40B
 146 #define DMA2_EXT_REG               0x4D6
 147
 148 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 149 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 150 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 151
 152 #define DMA_AUTOINIT     0x10
 153
 154 extern spinlock_t  dma_spin_lock;
 155
 156 static __inline__ unsigned long claim_dma_lock(void)
 157 {
 158         unsigned long flags;
 159         spin_lock_irqsave(&dma_spin_lock, flags);
 160         return flags;
 161 }
 162
 163 static __inline__ void release_dma_lock(unsigned long flags)
 164 {
 165         spin_unlock_irqrestore(&dma_spin_lock, flags);
 166 }
 167
 168 /* enable/disable a specific DMA channel */
 169 static __inline__ void enable_dma(unsigned int dmanr)
 170 {
 171         unsigned char ucDmaCmd=0x00;
 172
 173         if (dmanr != 4)
 174         {
 175                 dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
 176                 dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
 177         }
 178         if (dmanr<=3)
 179         {
 180                 dma_outb(dmanr,  DMA1_MASK_REG);
 181                 dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
 182         } else
 183         {
 184                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 185         }
 186 }
 187
 188 static __inline__ void disable_dma(unsigned int dmanr)
 189 {
 190         if (dmanr<=3)
 191                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 192         else
 193                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 194 }
 195
 196 /* Clear the 'DMA Pointer Flip Flop'.
 197  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 198  * Use this once to initialize the FF to a known state.
 199  * After that, keep track of it. :-)
 200  * --- In order to do that, the DMA routines below should ---
 201  * --- only be used while interrupts are disabled! ---
 202  */
 203 static __inline__ void clear_dma_ff(unsigned int dmanr)
 204 {
 205         if (dmanr<=3)
 206                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 207         else
 208                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 209 }
 210
 211 /* set mode (above) for a specific DMA channel */
 212 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 213 {
 214         if (dmanr<=3)
 215                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 216         else
 217                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 218 }
 219
 220 /* Set only the page register bits of the transfer address.
 221  * This is used for successive transfers when we know the contents of
 222  * the lower 16 bits of the DMA current address register, but a 64k boundary
 223  * may have been crossed.
 224  */
 225 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 226 {
 227         switch(dmanr) {
 228                 case 0:
 229                         dma_outb(pagenr, DMA_LO_PAGE_0);
 230                         dma_outb(pagenr>>8, DMA_HI_PAGE_0);
 231                         break;
 232                 case 1:
 233                         dma_outb(pagenr, DMA_LO_PAGE_1);
 234                         dma_outb(pagenr>>8, DMA_HI_PAGE_1);
 235                         break;
 236                 case 2:
 237                         dma_outb(pagenr, DMA_LO_PAGE_2);
 238                         dma_outb(pagenr>>8, DMA_HI_PAGE_2);
 239                         break;
 240                 case 3:
 241                         dma_outb(pagenr, DMA_LO_PAGE_3);
 242                         dma_outb(pagenr>>8, DMA_HI_PAGE_3);
 243                         break;
 244                 case 5:
 245                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 246                         dma_outb(pagenr>>8, DMA_HI_PAGE_5);
 247                         break;
 248                 case 6:
 249                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 250                         dma_outb(pagenr>>8, DMA_HI_PAGE_6);
 251                         break;
 252                 case 7:
 253                         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 254                         dma_outb(pagenr>>8, DMA_HI_PAGE_7);
 255                   break;
 256         }
 257 }
 258
 259
 260 /* Set transfer address & page bits for specific DMA channel.
 261  * Assumes dma flipflop is clear.
 262  */
 263 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 264 {
 265         if (dmanr <= 3)  {
 266             dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 267             dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 268         }  else  {
 269             dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 270             dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 271         }
 272         set_dma_page(dmanr, phys>>16);
 273 }
 274
 275
 276 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 277  * a specific DMA channel.
 278  * You must ensure the parameters are valid.
 279  * NOTE: from a manual: "the number of transfers is one more
 280  * than the initial word count"! This is taken into account.
 281  * Assumes dma flip-flop is clear.
 282  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 283  */
 284 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 285 {
 286         count--;
 287         if (dmanr <= 3)  {
 288             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 289             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 290         } else {
 291             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 292             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 293         }
 294 }
 295
 296
 297 /* Get DMA residue count. After a DMA transfer, this
 298  * should return zero. Reading this while a DMA transfer is
 299  * still in progress will return unpredictable results.
 300  * If called before the channel has been used, it may return 1.
 301  * Otherwise, it returns the number of _bytes_ left to transfer.
 302  *
 303  * Assumes DMA flip-flop is clear.
 304  */
 305 static __inline__ int get_dma_residue(unsigned int dmanr)
 306 {
 307         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 308                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 309
 310         /* using short to get 16-bit wrap around */
 311         unsigned short count;
 312
 313         count = 1 + dma_inb(io_port);
 314         count += dma_inb(io_port) << 8;
 315
 316         return (dmanr <= 3)? count : (count<<1);
 317 }
 318
 319 /* These are in kernel/dma.c: */
 320 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 321 extern void free_dma(unsigned int dmanr);       /* release it again */
 322
 323 #ifdef CONFIG_PCI
 324 extern int isa_dma_bridge_buggy;
 325 #else
 326 #define isa_dma_bridge_buggy   (0)
 327 #endif
 328 #endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
 329 #endif /* _ASM_DMA_H */