include/asm-sparc/mxcc.h

   1 /* $Id: mxcc.h,v 1.7 1997/04/20 14:11:46 ecd Exp $
   2  * mxcc.h:  Definitions of the Viking MXCC registers
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_MXCC_H
   8 #define _SPARC_MXCC_H
   9
  10 /* These registers are accessed through ASI 0x2. */
  11 #define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
  12 #define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
  13 #define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
  14 #define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
  15 #define MXCC_STEST           0x1C00804  /* Internal self-test */
  16 #define MXCC_CREG            0x1C00A04  /* Control register */
  17 #define MXCC_SREG            0x1C00B00  /* Status register */
  18 #define MXCC_RREG            0x1C00C04  /* Reset register */
  19 #define MXCC_EREG            0x1C00E00  /* Error code register */
  20 #define MXCC_PREG            0x1C00F04  /* Address port register */
  21
  22 /* Some MXCC constants. */
  23 #define MXCC_STREAM_SIZE     0x20       /* Size in bytes of one stream r/w */
  24
  25 /* The MXCC Control Register:
  26  *
  27  * ----------------------------------------------------------------------
  28  * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
  29  * ----------------------------------------------------------------------
  30  *  31                              10    9    8-6   5   4    3   2  1-0
  31  *
  32  * RRC: Controls what you read from MXCC_RMCOUNT reg.
  33  *      0=Misses 1=References
  34  * PRE: Prefetch enable
  35  * MCE: Multiple Command Enable
  36  * PARE: Parity enable
  37  * ECE: External cache enable
  38  */
  39
  40 #define MXCC_CTL_RRC   0x00000200
  41 #define MXCC_CTL_PRE   0x00000020
  42 #define MXCC_CTL_MCE   0x00000010
  43 #define MXCC_CTL_PARE  0x00000008
  44 #define MXCC_CTL_ECE   0x00000004
  45
  46 /* The MXCC Error Register:
  47  *
  48  * --------------------------------------------------------
  49  * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
  50  * --------------------------------------------------------
  51  *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
  52  *
  53  * ME: Multiple Errors have occurred
  54  * CE: Cache consistency Error
  55  * PEW: Parity Error during a Write operation
  56  * PEE: Parity Error involving the External cache
  57  * ASE: ASynchronous Error
  58  * EIV: This register is toast
  59  * MOPC: MXCC Operation Code for instance causing error
  60  * ECODE: The Error CODE
  61  * PRIV: A privileged mode error? 0=no 1=yes
  62  * HPADDR: High PhysicalADDRess bits (35-32)
  63  */
  64
  65 #define MXCC_ERR_ME     0x80000000
  66 #define MXCC_ERR_CE     0x20000000
  67 #define MXCC_ERR_PEW    0x10000000
  68 #define MXCC_ERR_PEE    0x08000000
  69 #define MXCC_ERR_ASE    0x04000000
  70 #define MXCC_ERR_EIV    0x02000000
  71 #define MXCC_ERR_MOPC   0x01FF8000
  72 #define MXCC_ERR_ECODE  0x00007F80
  73 #define MXCC_ERR_PRIV   0x00000040
  74 #define MXCC_ERR_HPADDR 0x0000000f
  75
  76 /* The MXCC Port register:
  77  *
  78  * -----------------------------------------------------
  79  * |                | MID |                            |
  80  * -----------------------------------------------------
  81  *  31            21 20-18 17                         0
  82  *
  83  * MID: The moduleID of the cpu your read this from.
  84  */
  85
  86 #ifndef __ASSEMBLY__
  87
  88 extern __inline__ void mxcc_set_stream_src(unsigned long *paddr)
  89 {
  90         unsigned long data0 = paddr[0];
  91         unsigned long data1 = paddr[1];
  92
  93         __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
  94                               "or %%g0, %1, %%g3\n\t"
  95                               "stda %%g2, [%2] %3\n\t" : :
  96                               "r" (data0), "r" (data1),
  97                               "r" (MXCC_SRCSTREAM),
  98                               "i" (ASI_M_MXCC) : "g2", "g3");
  99 }
 100
 101 extern __inline__ void mxcc_set_stream_dst(unsigned long *paddr)
 102 {
 103         unsigned long data0 = paddr[0];
 104         unsigned long data1 = paddr[1];
 105
 106         __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
 107                               "or %%g0, %1, %%g3\n\t"
 108                               "stda %%g2, [%2] %3\n\t" : :
 109                               "r" (data0), "r" (data1),
 110                               "r" (MXCC_DESSTREAM),
 111                               "i" (ASI_M_MXCC) : "g2", "g3");
 112 }
 113
 114 extern __inline__ unsigned long mxcc_get_creg(void)
 115 {
 116         unsigned long mxcc_control;
 117
 118         __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
 119                              "set 0xffffffff, %%g3\n\t"
 120                              "stda %%g2, [%1] %2\n\t"
 121                              "lda [%3] %2, %0\n\t" :
 122                              "=r" (mxcc_control) :
 123                              "r" (MXCC_EREG), "i" (ASI_M_MXCC),
 124                              "r" (MXCC_CREG) : "g2", "g3");
 125         return mxcc_control;
 126 }
 127
 128 extern __inline__ void mxcc_set_creg(unsigned long mxcc_control)
 129 {
 130         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
 131                              "r" (mxcc_control), "r" (MXCC_CREG),
 132                              "i" (ASI_M_MXCC));
 133 }
 134
 135 #endif /* !__ASSEMBLY__ */
 136
 137 #endif /* !(_SPARC_MXCC_H) */