arch/arm/plat-omap/include/plat/clock.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
  14 #define __ARCH_ARM_OMAP_CLOCK_H
  15
  16 #include <linux/list.h>
  17
  18 struct module;
  19 struct clk;
  20 struct clockdomain;
  21
  22 struct clkops {
  23         int                     (*enable)(struct clk *);
  24         void                    (*disable)(struct clk *);
  25         void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
  26         void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
  27 };
  28
  29 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
  30                 defined(CONFIG_ARCH_OMAP4)
  31
  32 struct clksel_rate {
  33         u32                     val;
  34         u8                      div;
  35         u8                      flags;
  36 };
  37
  38 struct clksel {
  39         struct clk               *parent;
  40         const struct clksel_rate *rates;
  41 };
  42
  43 struct dpll_data {
  44         void __iomem            *mult_div1_reg;
  45         u32                     mult_mask;
  46         u32                     div1_mask;
  47         struct clk              *clk_bypass;
  48         struct clk              *clk_ref;
  49         void __iomem            *control_reg;
  50         u32                     enable_mask;
  51         unsigned int            rate_tolerance;
  52         unsigned long           last_rounded_rate;
  53         u16                     last_rounded_m;
  54         u8                      last_rounded_n;
  55         u8                      min_divider;
  56         u8                      max_divider;
  57         u32                     max_tolerance;
  58         u16                     max_multiplier;
  59 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  60         u8                      modes;
  61         void __iomem            *autoidle_reg;
  62         void __iomem            *idlest_reg;
  63         u32                     autoidle_mask;
  64         u32                     freqsel_mask;
  65         u32                     idlest_mask;
  66         u8                      auto_recal_bit;
  67         u8                      recal_en_bit;
  68         u8                      recal_st_bit;
  69 #  endif
  70 };
  71
  72 #endif
  73
  74 struct clk {
  75         struct list_head        node;
  76         const struct clkops     *ops;
  77         const char              *name;
  78         int                     id;
  79         struct clk              *parent;
  80         struct list_head        children;
  81         struct list_head        sibling;        /* node for children */
  82         unsigned long           rate;
  83         __u32                   flags;
  84         void __iomem            *enable_reg;
  85         unsigned long           (*recalc)(struct clk *);
  86         int                     (*set_rate)(struct clk *, unsigned long);
  87         long                    (*round_rate)(struct clk *, unsigned long);
  88         void                    (*init)(struct clk *);
  89         __u8                    enable_bit;
  90         __s8                    usecount;
  91 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
  92                 defined(CONFIG_ARCH_OMAP4)
  93         u8                      fixed_div;
  94         void __iomem            *clksel_reg;
  95         u32                     clksel_mask;
  96         const struct clksel     *clksel;
  97         struct dpll_data        *dpll_data;
  98         const char              *clkdm_name;
  99         struct clockdomain      *clkdm;
 100 #else
 101         __u8                    rate_offset;
 102         __u8                    src_offset;
 103 #endif
 104 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 105         struct dentry           *dent;  /* For visible tree hierarchy */
 106 #endif
 107 };
 108
 109 struct cpufreq_frequency_table;
 110
 111 struct clk_functions {
 112         int             (*clk_enable)(struct clk *clk);
 113         void            (*clk_disable)(struct clk *clk);
 114         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
 115         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
 116         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
 117         void            (*clk_allow_idle)(struct clk *clk);
 118         void            (*clk_deny_idle)(struct clk *clk);
 119         void            (*clk_disable_unused)(struct clk *clk);
 120 #ifdef CONFIG_CPU_FREQ
 121         void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 122         void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 123 #endif
 124 };
 125
 126 extern unsigned int mpurate;
 127
 128 extern int clk_init(struct clk_functions *custom_clocks);
 129 extern void clk_preinit(struct clk *clk);
 130 extern int clk_register(struct clk *clk);
 131 extern void clk_reparent(struct clk *child, struct clk *parent);
 132 extern void clk_unregister(struct clk *clk);
 133 extern void propagate_rate(struct clk *clk);
 134 extern void recalculate_root_clocks(void);
 135 extern unsigned long followparent_recalc(struct clk *clk);
 136 extern void clk_enable_init_clocks(void);
 137 #ifdef CONFIG_CPU_FREQ
 138 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 139 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 140 #endif
 141
 142 extern const struct clkops clkops_null;
 143
 144 /* Clock flags */
 145 /* bit 0 is free */
 146 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
 147 /* bits 2-4 are free */
 148 #define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
 149 #define CLOCK_IDLE_CONTROL      (1 << 7)
 150 #define CLOCK_NO_IDLE_PARENT    (1 << 8)
 151 #define DELAYED_APP             (1 << 9)        /* Delay application of clock */
 152 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 153 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 154 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
 155 #define CLOCK_IN_OMAP4430       (1 << 13)
 156 #define ALWAYS_ENABLED          (1 << 14)
 157 /* bits 13-31 are currently free */
 158
 159 /* Clksel_rate flags */
 160 #define DEFAULT_RATE            (1 << 0)
 161 #define RATE_IN_242X            (1 << 1)
 162 #define RATE_IN_243X            (1 << 2)
 163 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 164 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
 165 #define RATE_IN_4430            (1 << 5)
 166
 167 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 168
 169
 170 #endif