arch/arm/plat-omap/include/plat/sdrc.h

   1 #ifndef ____ASM_ARCH_SDRC_H
   2 #define ____ASM_ARCH_SDRC_H
   3
   4 /*
   5  * OMAP2/3 SDRC/SMS register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Tony Lindgren
  11  * Paul Walmsley
  12  * Richard Woodruff
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <mach/io.h>
  20
  21 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
  22
  23 #define SDRC_SYSCONFIG          0x010
  24 #define SDRC_CS_CFG             0x040
  25 #define SDRC_SHARING            0x044
  26 #define SDRC_ERR_TYPE           0x04C
  27 #define SDRC_DLLA_CTRL          0x060
  28 #define SDRC_DLLA_STATUS        0x064
  29 #define SDRC_DLLB_CTRL          0x068
  30 #define SDRC_DLLB_STATUS        0x06C
  31 #define SDRC_POWER              0x070
  32 #define SDRC_MCFG_0             0x080
  33 #define SDRC_MR_0               0x084
  34 #define SDRC_EMR2_0             0x08c
  35 #define SDRC_ACTIM_CTRL_A_0     0x09c
  36 #define SDRC_ACTIM_CTRL_B_0     0x0a0
  37 #define SDRC_RFR_CTRL_0         0x0a4
  38 #define SDRC_MANUAL_0           0x0a8
  39 #define SDRC_MCFG_1             0x0B0
  40 #define SDRC_MR_1               0x0B4
  41 #define SDRC_EMR2_1             0x0BC
  42 #define SDRC_ACTIM_CTRL_A_1     0x0C4
  43 #define SDRC_ACTIM_CTRL_B_1     0x0C8
  44 #define SDRC_RFR_CTRL_1         0x0D4
  45 #define SDRC_MANUAL_1           0x0D8
  46
  47 #define SDRC_POWER_AUTOCOUNT_SHIFT      8
  48 #define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
  49 #define SDRC_POWER_CLKCTRL_SHIFT        4
  50 #define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
  51 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
  52
  53 /*
  54  * These values represent the number of memory clock cycles between
  55  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
  56  * rows per device, and include a subtraction of a 50 cycle window in the
  57  * event that the autorefresh command is delayed due to other SDRC activity.
  58  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
  59  * counter reaches 0.
  60  *
  61  * These represent optimal values for common parts, it won't work for all.
  62  * As long as you scale down, most parameters are still work, they just
  63  * become sub-optimal. The RFR value goes in the opposite direction. If you
  64  * don't adjust it down as your clock period increases the refresh interval
  65  * will not be met. Setting all parameters for complete worst case may work,
  66  * but may cut memory performance by 2x. Due to errata the DLLs need to be
  67  * unlocked and their value needs run time calibration. A dynamic call is
  68  * need for that as no single right value exists acorss production samples.
  69  *
  70  * Only the FULL speed values are given. Current code is such that rate
  71  * changes must be made at DPLLoutx2. The actual value adjustment for low
  72  * frequency operation will be handled by omap_set_performance()
  73  *
  74  * By having the boot loader boot up in the fastest L4 speed available likely
  75  * will result in something which you can switch between.
  76  */
  77 #define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
  78 #define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
  79 #define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
  80 #define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
  81 #define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
  82
  83
  84 /*
  85  * SMS register access
  86  */
  87
  88 #define OMAP242X_SMS_REGADDR(reg)                                       \
  89                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
  90 #define OMAP243X_SMS_REGADDR(reg)                                       \
  91                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
  92 #define OMAP343X_SMS_REGADDR(reg)                                       \
  93                 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
  94
  95 /* SMS register offsets - read/write with sms_{read,write}_reg() */
  96
  97 #define SMS_SYSCONFIG                   0x010
  98 #define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
  99 #define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
 100 #define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
 101 /* REVISIT: fill in other SMS registers here */
 102
 103
 104 #ifndef __ASSEMBLER__
 105
 106 /**
 107  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
 108  * @rate: SDRC clock rate (in Hz)
 109  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
 110  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
 111  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
 112  * @mr: Value to program to SDRC_MR for this rate
 113  *
 114  * This structure holds a pre-computed set of register values for the
 115  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
 116  * intended to be pre-computed and specified in an array in the board-*.c
 117  * files.  The structure is keyed off the 'rate' field.
 118  */
 119 struct omap_sdrc_params {
 120         unsigned long rate;
 121         u32 actim_ctrla;
 122         u32 actim_ctrlb;
 123         u32 rfr_ctrl;
 124         u32 mr;
 125 };
 126
 127 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 128                             struct omap_sdrc_params *sdrc_cs1);
 129 int omap2_sdrc_get_params(unsigned long r,
 130                           struct omap_sdrc_params **sdrc_cs0,
 131                           struct omap_sdrc_params **sdrc_cs1);
 132 void omap2_sms_save_context(void);
 133 void omap2_sms_restore_context(void);
 134
 135 void omap2_sms_write_rot_control(u32 val, unsigned ctx);
 136 void omap2_sms_write_rot_size(u32 val, unsigned ctx);
 137 void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
 138
 139 #ifdef CONFIG_ARCH_OMAP2
 140
 141 struct memory_timings {
 142         u32 m_type;             /* ddr = 1, sdr = 0 */
 143         u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
 144         u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
 145         u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
 146         u32 base_cs;            /* base chip select to use for calculations */
 147 };
 148
 149 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
 150
 151 u32 omap2xxx_sdrc_dll_is_unlocked(void);
 152 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
 153
 154 #endif  /* CONFIG_ARCH_OMAP2 */
 155
 156 #endif  /* __ASSEMBLER__ */
 157
 158 #endif