drivers/edac/amd64_edac.h

   1 /*
   2  * AMD64 class Memory Controller kernel module
   3  *
   4  * Copyright (c) 2009 SoftwareBitMaker.
   5  * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
   6  *
   7  * This file may be distributed under the terms of the
   8  * GNU General Public License.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/ctype.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/slab.h>
  17 #include <linux/mmzone.h>
  18 #include <linux/edac.h>
  19 #include <asm/cpu_device_id.h>
  20 #include <asm/msr.h>
  21 #include "edac_core.h"
  22 #include "mce_amd.h"
  23
  24 #define amd64_debug(fmt, arg...) \
  25         edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
  26
  27 #define amd64_info(fmt, arg...) \
  28         edac_printk(KERN_INFO, "amd64", fmt, ##arg)
  29
  30 #define amd64_notice(fmt, arg...) \
  31         edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
  32
  33 #define amd64_warn(fmt, arg...) \
  34         edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
  35
  36 #define amd64_err(fmt, arg...) \
  37         edac_printk(KERN_ERR, "amd64", fmt, ##arg)
  38
  39 #define amd64_mc_warn(mci, fmt, arg...) \
  40         edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
  41
  42 #define amd64_mc_err(mci, fmt, arg...) \
  43         edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
  44
  45 /*
  46  * Throughout the comments in this code, the following terms are used:
  47  *
  48  *      SysAddr, DramAddr, and InputAddr
  49  *
  50  *  These terms come directly from the amd64 documentation
  51  * (AMD publication #26094).  They are defined as follows:
  52  *
  53  *     SysAddr:
  54  *         This is a physical address generated by a CPU core or a device
  55  *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
  56  *         a virtual to physical address translation by the CPU core's address
  57  *         translation mechanism (MMU).
  58  *
  59  *     DramAddr:
  60  *         A DramAddr is derived from a SysAddr by subtracting an offset that
  61  *         depends on which node the SysAddr maps to and whether the SysAddr
  62  *         is within a range affected by memory hoisting.  The DRAM Base
  63  *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
  64  *         determine which node a SysAddr maps to.
  65  *
  66  *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
  67  *         is within the range of addresses specified by this register, then
  68  *         a value x from the DHAR is subtracted from the SysAddr to produce a
  69  *         DramAddr.  Here, x represents the base address for the node that
  70  *         the SysAddr maps to plus an offset due to memory hoisting.  See
  71  *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
  72  *         sys_addr_to_dram_addr() below for more information.
  73  *
  74  *         If the SysAddr is not affected by the DHAR then a value y is
  75  *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
  76  *         base address for the node that the SysAddr maps to.  See section
  77  *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
  78  *         information.
  79  *
  80  *     InputAddr:
  81  *         A DramAddr is translated to an InputAddr before being passed to the
  82  *         memory controller for the node that the DramAddr is associated
  83  *         with.  The memory controller then maps the InputAddr to a csrow.
  84  *         If node interleaving is not in use, then the InputAddr has the same
  85  *         value as the DramAddr.  Otherwise, the InputAddr is produced by
  86  *         discarding the bits used for node interleaving from the DramAddr.
  87  *         See section 3.4.4 for more information.
  88  *
  89  *         The memory controller for a given node uses its DRAM CS Base and
  90  *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
  91  *         sections 3.5.4 and 3.5.5 for more information.
  92  */
  93
  94 #define EDAC_AMD64_VERSION              "3.4.0"
  95 #define EDAC_MOD_STR                    "amd64_edac"
  96
  97 /* Extended Model from CPUID, for CPU Revision numbers */
  98 #define K8_REV_D                        1
  99 #define K8_REV_E                        2
 100 #define K8_REV_F                        4
 101
 102 /* Hardware limit on ChipSelect rows per MC and processors per system */
 103 #define NUM_CHIPSELECTS                 8
 104 #define DRAM_RANGES                     8
 105
 106 #define ON true
 107 #define OFF false
 108
 109 /*
 110  * PCI-defined configuration space registers
 111  */
 112 #define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
 113 #define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
 114 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
 115 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
 116 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
 117 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
 118 #define PCI_DEVICE_ID_AMD_16H_NB_F1     0x1531
 119 #define PCI_DEVICE_ID_AMD_16H_NB_F2     0x1532
 120 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
 121 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
 122
 123 /*
 124  * Function 1 - Address Map
 125  */
 126 #define DRAM_BASE_LO                    0x40
 127 #define DRAM_LIMIT_LO                   0x44
 128
 129 /*
 130  * F15 M30h D18F1x2[1C:00]
 131  */
 132 #define DRAM_CONT_BASE                  0x200
 133 #define DRAM_CONT_LIMIT                 0x204
 134
 135 /*
 136  * F15 M30h D18F1x2[4C:40]
 137  */
 138 #define DRAM_CONT_HIGH_OFF              0x240
 139
 140 #define dram_rw(pvt, i)                 ((u8)(pvt->ranges[i].base.lo & 0x3))
 141 #define dram_intlv_sel(pvt, i)          ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
 142 #define dram_dst_node(pvt, i)           ((u8)(pvt->ranges[i].lim.lo & 0x7))
 143
 144 #define DHAR                            0xf0
 145 #define dhar_mem_hoist_valid(pvt)       ((pvt)->dhar & BIT(1))
 146 #define dhar_base(pvt)                  ((pvt)->dhar & 0xff000000)
 147 #define k8_dhar_offset(pvt)             (((pvt)->dhar & 0x0000ff00) << 16)
 148
 149                                         /* NOTE: Extra mask bit vs K8 */
 150 #define f10_dhar_offset(pvt)            (((pvt)->dhar & 0x0000ff80) << 16)
 151
 152 #define DCT_CFG_SEL                     0x10C
 153
 154 #define DRAM_LOCAL_NODE_BASE            0x120
 155 #define DRAM_LOCAL_NODE_LIM             0x124
 156
 157 #define DRAM_BASE_HI                    0x140
 158 #define DRAM_LIMIT_HI                   0x144
 159
 160
 161 /*
 162  * Function 2 - DRAM controller
 163  */
 164 #define DCSB0                           0x40
 165 #define DCSB1                           0x140
 166 #define DCSB_CS_ENABLE                  BIT(0)
 167
 168 #define DCSM0                           0x60
 169 #define DCSM1                           0x160
 170
 171 #define csrow_enabled(i, dct, pvt)      ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
 172
 173 #define DRAM_CONTROL                    0x78
 174
 175 #define DBAM0                           0x80
 176 #define DBAM1                           0x180
 177
 178 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
 179 #define DBAM_DIMM(i, reg)               ((((reg) >> (4*(i)))) & 0xF)
 180
 181 #define DBAM_MAX_VALUE                  11
 182
 183 #define DCLR0                           0x90
 184 #define DCLR1                           0x190
 185 #define REVE_WIDTH_128                  BIT(16)
 186 #define WIDTH_128                       BIT(11)
 187
 188 #define DCHR0                           0x94
 189 #define DCHR1                           0x194
 190 #define DDR3_MODE                       BIT(8)
 191
 192 #define DCT_SEL_LO                      0x110
 193 #define dct_high_range_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(0))
 194 #define dct_interleave_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(2))
 195
 196 #define dct_ganging_enabled(pvt)        ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
 197
 198 #define dct_data_intlv_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(5))
 199 #define dct_memory_cleared(pvt)         ((pvt)->dct_sel_lo & BIT(10))
 200
 201 #define SWAP_INTLV_REG                  0x10c
 202
 203 #define DCT_SEL_HI                      0x114
 204
 205 #define F15H_M60H_SCRCTRL               0x1C8
 206
 207 /*
 208  * Function 3 - Misc Control
 209  */
 210 #define NBCTL                           0x40
 211
 212 #define NBCFG                           0x44
 213 #define NBCFG_CHIPKILL                  BIT(23)
 214 #define NBCFG_ECC_ENABLE                BIT(22)
 215
 216 /* F3x48: NBSL */
 217 #define F10_NBSL_EXT_ERR_ECC            0x8
 218 #define NBSL_PP_OBS                     0x2
 219
 220 #define SCRCTRL                         0x58
 221
 222 #define F10_ONLINE_SPARE                0xB0
 223 #define online_spare_swap_done(pvt, c)  (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
 224 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
 225
 226 #define F10_NB_ARRAY_ADDR               0xB8
 227 #define F10_NB_ARRAY_DRAM               BIT(31)
 228
 229 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
 230 #define SET_NB_ARRAY_ADDR(section)      (((section) & 0x3) << 1)
 231
 232 #define F10_NB_ARRAY_DATA               0xBC
 233 #define F10_NB_ARR_ECC_WR_REQ           BIT(17)
 234 #define SET_NB_DRAM_INJECTION_WRITE(inj)  \
 235                                         (BIT(((inj.word) & 0xF) + 20) | \
 236                                         F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
 237 #define SET_NB_DRAM_INJECTION_READ(inj)  \
 238                                         (BIT(((inj.word) & 0xF) + 20) | \
 239                                         BIT(16) |  inj.bit_map)
 240
 241
 242 #define NBCAP                           0xE8
 243 #define NBCAP_CHIPKILL                  BIT(4)
 244 #define NBCAP_SECDED                    BIT(3)
 245 #define NBCAP_DCT_DUAL                  BIT(0)
 246
 247 #define EXT_NB_MCA_CFG                  0x180
 248
 249 /* MSRs */
 250 #define MSR_MCGCTL_NBE                  BIT(4)
 251
 252 enum amd_families {
 253         K8_CPUS = 0,
 254         F10_CPUS,
 255         F15_CPUS,
 256         F15_M30H_CPUS,
 257         F15_M60H_CPUS,
 258         F16_CPUS,
 259         F16_M30H_CPUS,
 260         NUM_FAMILIES,
 261 };
 262
 263 /* Error injection control structure */
 264 struct error_injection {
 265         u32      section;
 266         u32      word;
 267         u32      bit_map;
 268 };
 269
 270 /* low and high part of PCI config space regs */
 271 struct reg_pair {
 272         u32 lo, hi;
 273 };
 274
 275 /*
 276  * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 277  */
 278 struct dram_range {
 279         struct reg_pair base;
 280         struct reg_pair lim;
 281 };
 282
 283 /* A DCT chip selects collection */
 284 struct chip_select {
 285         u32 csbases[NUM_CHIPSELECTS];
 286         u8 b_cnt;
 287
 288         u32 csmasks[NUM_CHIPSELECTS];
 289         u8 m_cnt;
 290 };
 291
 292 struct amd64_pvt {
 293         struct low_ops *ops;
 294
 295         /* pci_device handles which we utilize */
 296         struct pci_dev *F1, *F2, *F3;
 297
 298         u16 mc_node_id;         /* MC index of this MC node */
 299         u8 fam;                 /* CPU family */
 300         u8 model;               /* ... model */
 301         u8 stepping;            /* ... stepping */
 302
 303         int ext_model;          /* extended model value of this node */
 304         int channel_count;
 305
 306         /* Raw registers */
 307         u32 dclr0;              /* DRAM Configuration Low DCT0 reg */
 308         u32 dclr1;              /* DRAM Configuration Low DCT1 reg */
 309         u32 dchr0;              /* DRAM Configuration High DCT0 reg */
 310         u32 dchr1;              /* DRAM Configuration High DCT1 reg */
 311         u32 nbcap;              /* North Bridge Capabilities */
 312         u32 nbcfg;              /* F10 North Bridge Configuration */
 313         u32 ext_nbcfg;          /* Extended F10 North Bridge Configuration */
 314         u32 dhar;               /* DRAM Hoist reg */
 315         u32 dbam0;              /* DRAM Base Address Mapping reg for DCT0 */
 316         u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 317
 318         /* one for each DCT */
 319         struct chip_select csels[2];
 320
 321         /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
 322         struct dram_range ranges[DRAM_RANGES];
 323
 324         u64 top_mem;            /* top of memory below 4GB */
 325         u64 top_mem2;           /* top of memory above 4GB */
 326
 327         u32 dct_sel_lo;         /* DRAM Controller Select Low */
 328         u32 dct_sel_hi;         /* DRAM Controller Select High */
 329         u32 online_spare;       /* On-Line spare Reg */
 330
 331         /* x4 or x8 syndromes in use */
 332         u8 ecc_sym_sz;
 333
 334         /* place to store error injection parameters prior to issue */
 335         struct error_injection injection;
 336
 337         /* cache the dram_type */
 338         enum mem_type dram_type;
 339 };
 340
 341 enum err_codes {
 342         DECODE_OK       =  0,
 343         ERR_NODE        = -1,
 344         ERR_CSROW       = -2,
 345         ERR_CHANNEL     = -3,
 346 };
 347
 348 struct err_info {
 349         int err_code;
 350         struct mem_ctl_info *src_mci;
 351         int csrow;
 352         int channel;
 353         u16 syndrome;
 354         u32 page;
 355         u32 offset;
 356 };
 357
 358 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
 359 {
 360         u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
 361
 362         if (boot_cpu_data.x86 == 0xf)
 363                 return addr;
 364
 365         return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
 366 }
 367
 368 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
 369 {
 370         u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
 371
 372         if (boot_cpu_data.x86 == 0xf)
 373                 return lim;
 374
 375         return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
 376 }
 377
 378 static inline u16 extract_syndrome(u64 status)
 379 {
 380         return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
 381 }
 382
 383 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
 384 {
 385         if (pvt->fam == 0x15 && pvt->model >= 0x30)
 386                 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
 387                         ((pvt->dct_sel_lo >> 6) & 0x3);
 388
 389         return  ((pvt)->dct_sel_lo >> 6) & 0x3;
 390 }
 391 /*
 392  * per-node ECC settings descriptor
 393  */
 394 struct ecc_settings {
 395         u32 old_nbctl;
 396         bool nbctl_valid;
 397
 398         struct flags {
 399                 unsigned long nb_mce_enable:1;
 400                 unsigned long nb_ecc_prev:1;
 401         } flags;
 402 };
 403
 404 #ifdef CONFIG_EDAC_DEBUG
 405 extern const struct attribute_group amd64_edac_dbg_group;
 406 #endif
 407
 408 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
 409 extern const struct attribute_group amd64_edac_inj_group;
 410 #endif
 411
 412 /*
 413  * Each of the PCI Device IDs types have their own set of hardware accessor
 414  * functions and per device encoding/decoding logic.
 415  */
 416 struct low_ops {
 417         int (*early_channel_count)      (struct amd64_pvt *pvt);
 418         void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci, u64 sys_addr,
 419                                          struct err_info *);
 420         int (*dbam_to_cs)               (struct amd64_pvt *pvt, u8 dct,
 421                                          unsigned cs_mode, int cs_mask_nr);
 422 };
 423
 424 struct amd64_family_type {
 425         const char *ctl_name;
 426         u16 f1_id, f2_id;
 427         struct low_ops ops;
 428 };
 429
 430 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
 431                                u32 *val, const char *func);
 432 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
 433                                 u32 val, const char *func);
 434
 435 #define amd64_read_pci_cfg(pdev, offset, val)   \
 436         __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
 437
 438 #define amd64_write_pci_cfg(pdev, offset, val)  \
 439         __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
 440
 441 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
 442                              u64 *hole_offset, u64 *hole_size);
 443
 444 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
 445
 446 /* Injection helpers */
 447 static inline void disable_caches(void *dummy)
 448 {
 449         write_cr0(read_cr0() | X86_CR0_CD);
 450         wbinvd();
 451 }
 452
 453 static inline void enable_caches(void *dummy)
 454 {
 455         write_cr0(read_cr0() & ~X86_CR0_CD);
 456 }
 457
 458 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
 459 {
 460         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 461                 u32 tmp;
 462                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
 463                 return (u8) tmp & 0xF;
 464         }
 465         return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
 466 }
 467
 468 static inline u8 dhar_valid(struct amd64_pvt *pvt)
 469 {
 470         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 471                 u32 tmp;
 472                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
 473                 return (tmp >> 1) & BIT(0);
 474         }
 475         return (pvt)->dhar & BIT(0);
 476 }
 477
 478 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
 479 {
 480         if (pvt->fam == 0x15 && pvt->model >= 0x30) {
 481                 u32 tmp;
 482                 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
 483                 return (tmp >> 11) & 0x1FFF;
 484         }
 485         return (pvt)->dct_sel_lo & 0xFFFFF800;
 486 }