drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup
[linux/fpc-iii.git] / arch / arm / mach-s3c64xx / setup-ide.c
blob689fb72e715cc9b8689d401deae52b8294701d4d
1 /* linux/arch/arm/mach-s3c64xx/setup-ide.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S3C64XX setup information for IDE
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/gpio.h>
15 #include <linux/io.h>
17 #include <mach/map.h>
18 #include <mach/regs-clock.h>
19 #include <plat/gpio-cfg.h>
20 #include <mach/gpio-samsung.h>
21 #include <linux/platform_data/ata-samsung_cf.h>
23 void s3c64xx_ide_setup_gpio(void)
25 u32 reg;
27 reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
29 /* Independent CF interface, CF chip select configuration */
30 writel(reg | MEM_SYS_CFG_INDEP_CF |
31 MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
33 s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
35 /* Set XhiDATA[15:0] pins as CF Data[15:0] */
36 s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
38 /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
39 s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
41 /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
42 s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
43 s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));