2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
59 #define LOOP_TIMEOUT 100000
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
78 * 512GB Pages are not supported due to a hardware bug
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list
);
86 static DEFINE_SPINLOCK(dev_data_list_lock
);
88 LIST_HEAD(ioapic_map
);
90 LIST_HEAD(acpihid_map
);
92 #define FLUSH_QUEUE_SIZE 256
94 struct flush_queue_entry
{
95 unsigned long iova_pfn
;
97 struct dma_ops_domain
*dma_dom
;
103 struct flush_queue_entry
*entries
;
106 static DEFINE_PER_CPU(struct flush_queue
, flush_queue
);
108 static atomic_t queue_timer_on
;
109 static struct timer_list queue_timer
;
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
115 const struct iommu_ops amd_iommu_ops
;
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
118 int amd_iommu_max_glx_val
= -1;
120 static const struct dma_map_ops amd_iommu_dma_ops
;
123 * This struct contains device specific data for the IOMMU
125 struct iommu_dev_data
{
126 struct list_head list
; /* For domain->dev_list */
127 struct list_head dev_data_list
; /* For global dev_data_list */
128 struct protection_domain
*domain
; /* Domain the device is bound to */
129 u16 devid
; /* PCI Device ID */
130 u16 alias
; /* Alias Device ID */
131 bool iommu_v2
; /* Device can make use of IOMMUv2 */
132 bool passthrough
; /* Device is identity mapped */
136 } ats
; /* ATS state */
137 bool pri_tlp
; /* PASID TLB required for
139 u32 errata
; /* Bitmap for errata to apply */
140 bool use_vapic
; /* Enable device to use vapic mode */
144 * general struct to manage commands send to an IOMMU
150 struct kmem_cache
*amd_iommu_irq_cache
;
152 static void update_domain(struct protection_domain
*domain
);
153 static int protection_domain_init(struct protection_domain
*domain
);
154 static void detach_device(struct device
*dev
);
157 * Data container for a dma_ops specific protection domain
159 struct dma_ops_domain
{
160 /* generic protection domain information */
161 struct protection_domain domain
;
164 struct iova_domain iovad
;
167 static struct iova_domain reserved_iova_ranges
;
168 static struct lock_class_key reserved_rbtree_key
;
170 /****************************************************************************
174 ****************************************************************************/
176 static inline int match_hid_uid(struct device
*dev
,
177 struct acpihid_map_entry
*entry
)
179 const char *hid
, *uid
;
181 hid
= acpi_device_hid(ACPI_COMPANION(dev
));
182 uid
= acpi_device_uid(ACPI_COMPANION(dev
));
188 return strcmp(hid
, entry
->hid
);
191 return strcmp(hid
, entry
->hid
);
193 return (strcmp(hid
, entry
->hid
) || strcmp(uid
, entry
->uid
));
196 static inline u16
get_pci_device_id(struct device
*dev
)
198 struct pci_dev
*pdev
= to_pci_dev(dev
);
200 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
203 static inline int get_acpihid_device_id(struct device
*dev
,
204 struct acpihid_map_entry
**entry
)
206 struct acpihid_map_entry
*p
;
208 list_for_each_entry(p
, &acpihid_map
, list
) {
209 if (!match_hid_uid(dev
, p
)) {
218 static inline int get_device_id(struct device
*dev
)
223 devid
= get_pci_device_id(dev
);
225 devid
= get_acpihid_device_id(dev
, NULL
);
230 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
232 return container_of(dom
, struct protection_domain
, domain
);
235 static struct dma_ops_domain
* to_dma_ops_domain(struct protection_domain
*domain
)
237 BUG_ON(domain
->flags
!= PD_DMA_OPS_MASK
);
238 return container_of(domain
, struct dma_ops_domain
, domain
);
241 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
243 struct iommu_dev_data
*dev_data
;
246 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
250 dev_data
->devid
= devid
;
252 spin_lock_irqsave(&dev_data_list_lock
, flags
);
253 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
254 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
259 static struct iommu_dev_data
*search_dev_data(u16 devid
)
261 struct iommu_dev_data
*dev_data
;
264 spin_lock_irqsave(&dev_data_list_lock
, flags
);
265 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
266 if (dev_data
->devid
== devid
)
273 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
278 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
280 *(u16
*)data
= alias
;
284 static u16
get_alias(struct device
*dev
)
286 struct pci_dev
*pdev
= to_pci_dev(dev
);
287 u16 devid
, ivrs_alias
, pci_alias
;
289 /* The callers make sure that get_device_id() does not fail here */
290 devid
= get_device_id(dev
);
291 ivrs_alias
= amd_iommu_alias_table
[devid
];
292 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
294 if (ivrs_alias
== pci_alias
)
300 * The IVRS is fairly reliable in telling us about aliases, but it
301 * can't know about every screwy device. If we don't have an IVRS
302 * reported alias, use the PCI reported alias. In that case we may
303 * still need to initialize the rlookup and dev_table entries if the
304 * alias is to a non-existent device.
306 if (ivrs_alias
== devid
) {
307 if (!amd_iommu_rlookup_table
[pci_alias
]) {
308 amd_iommu_rlookup_table
[pci_alias
] =
309 amd_iommu_rlookup_table
[devid
];
310 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
311 amd_iommu_dev_table
[devid
].data
,
312 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
318 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
319 "for device %s[%04x:%04x], kernel reported alias "
320 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
321 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
322 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
323 PCI_FUNC(pci_alias
));
326 * If we don't have a PCI DMA alias and the IVRS alias is on the same
327 * bus, then the IVRS table may know about a quirk that we don't.
329 if (pci_alias
== devid
&&
330 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
331 pci_add_dma_alias(pdev
, ivrs_alias
& 0xff);
332 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
333 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
340 static struct iommu_dev_data
*find_dev_data(u16 devid
)
342 struct iommu_dev_data
*dev_data
;
344 dev_data
= search_dev_data(devid
);
346 if (dev_data
== NULL
)
347 dev_data
= alloc_dev_data(devid
);
352 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
354 return dev
->archdata
.iommu
;
358 * Find or create an IOMMU group for a acpihid device.
360 static struct iommu_group
*acpihid_device_group(struct device
*dev
)
362 struct acpihid_map_entry
*p
, *entry
= NULL
;
365 devid
= get_acpihid_device_id(dev
, &entry
);
367 return ERR_PTR(devid
);
369 list_for_each_entry(p
, &acpihid_map
, list
) {
370 if ((devid
== p
->devid
) && p
->group
)
371 entry
->group
= p
->group
;
375 entry
->group
= generic_device_group(dev
);
377 iommu_group_ref_get(entry
->group
);
382 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
384 static const int caps
[] = {
387 PCI_EXT_CAP_ID_PASID
,
391 for (i
= 0; i
< 3; ++i
) {
392 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
400 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
402 struct iommu_dev_data
*dev_data
;
404 dev_data
= get_dev_data(&pdev
->dev
);
406 return dev_data
->errata
& (1 << erratum
) ? true : false;
410 * This function checks if the driver got a valid device from the caller to
411 * avoid dereferencing invalid pointers.
413 static bool check_device(struct device
*dev
)
417 if (!dev
|| !dev
->dma_mask
)
420 devid
= get_device_id(dev
);
424 /* Out of our scope? */
425 if (devid
> amd_iommu_last_bdf
)
428 if (amd_iommu_rlookup_table
[devid
] == NULL
)
434 static void init_iommu_group(struct device
*dev
)
436 struct iommu_group
*group
;
438 group
= iommu_group_get_for_dev(dev
);
442 iommu_group_put(group
);
445 static int iommu_init_device(struct device
*dev
)
447 struct iommu_dev_data
*dev_data
;
448 struct amd_iommu
*iommu
;
451 if (dev
->archdata
.iommu
)
454 devid
= get_device_id(dev
);
458 iommu
= amd_iommu_rlookup_table
[devid
];
460 dev_data
= find_dev_data(devid
);
464 dev_data
->alias
= get_alias(dev
);
466 if (dev_is_pci(dev
) && pci_iommuv2_capable(to_pci_dev(dev
))) {
467 struct amd_iommu
*iommu
;
469 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
470 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
473 dev
->archdata
.iommu
= dev_data
;
475 iommu_device_link(&iommu
->iommu
, dev
);
480 static void iommu_ignore_device(struct device
*dev
)
485 devid
= get_device_id(dev
);
489 alias
= get_alias(dev
);
491 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
492 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
494 amd_iommu_rlookup_table
[devid
] = NULL
;
495 amd_iommu_rlookup_table
[alias
] = NULL
;
498 static void iommu_uninit_device(struct device
*dev
)
500 struct iommu_dev_data
*dev_data
;
501 struct amd_iommu
*iommu
;
504 devid
= get_device_id(dev
);
508 iommu
= amd_iommu_rlookup_table
[devid
];
510 dev_data
= search_dev_data(devid
);
514 if (dev_data
->domain
)
517 iommu_device_unlink(&iommu
->iommu
, dev
);
519 iommu_group_remove_device(dev
);
525 * We keep dev_data around for unplugged devices and reuse it when the
526 * device is re-plugged - not doing so would introduce a ton of races.
530 /****************************************************************************
532 * Interrupt handling functions
534 ****************************************************************************/
536 static void dump_dte_entry(u16 devid
)
540 for (i
= 0; i
< 4; ++i
)
541 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
542 amd_iommu_dev_table
[devid
].data
[i
]);
545 static void dump_command(unsigned long phys_addr
)
547 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
550 for (i
= 0; i
< 4; ++i
)
551 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
554 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
556 int type
, devid
, domid
, flags
;
557 volatile u32
*event
= __evt
;
562 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
563 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
564 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
565 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
566 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
569 /* Did we hit the erratum? */
570 if (++count
== LOOP_TIMEOUT
) {
571 pr_err("AMD-Vi: No event written to event log\n");
578 printk(KERN_ERR
"AMD-Vi: Event logged [");
581 case EVENT_TYPE_ILL_DEV
:
582 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
583 "address=0x%016llx flags=0x%04x]\n",
584 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
586 dump_dte_entry(devid
);
588 case EVENT_TYPE_IO_FAULT
:
589 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
590 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
591 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
592 domid
, address
, flags
);
594 case EVENT_TYPE_DEV_TAB_ERR
:
595 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
600 case EVENT_TYPE_PAGE_TAB_ERR
:
601 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
602 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
603 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
604 domid
, address
, flags
);
606 case EVENT_TYPE_ILL_CMD
:
607 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
608 dump_command(address
);
610 case EVENT_TYPE_CMD_HARD_ERR
:
611 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
612 "flags=0x%04x]\n", address
, flags
);
614 case EVENT_TYPE_IOTLB_INV_TO
:
615 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
616 "address=0x%016llx]\n",
617 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
620 case EVENT_TYPE_INV_DEV_REQ
:
621 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
622 "address=0x%016llx flags=0x%04x]\n",
623 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
627 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
630 memset(__evt
, 0, 4 * sizeof(u32
));
633 static void iommu_poll_events(struct amd_iommu
*iommu
)
637 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
638 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
640 while (head
!= tail
) {
641 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
642 head
= (head
+ EVENT_ENTRY_SIZE
) % EVT_BUFFER_SIZE
;
645 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
648 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
650 struct amd_iommu_fault fault
;
652 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
653 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
657 fault
.address
= raw
[1];
658 fault
.pasid
= PPR_PASID(raw
[0]);
659 fault
.device_id
= PPR_DEVID(raw
[0]);
660 fault
.tag
= PPR_TAG(raw
[0]);
661 fault
.flags
= PPR_FLAGS(raw
[0]);
663 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
666 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
670 if (iommu
->ppr_log
== NULL
)
673 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
674 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
676 while (head
!= tail
) {
681 raw
= (u64
*)(iommu
->ppr_log
+ head
);
684 * Hardware bug: Interrupt may arrive before the entry is
685 * written to memory. If this happens we need to wait for the
688 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
689 if (PPR_REQ_TYPE(raw
[0]) != 0)
694 /* Avoid memcpy function-call overhead */
699 * To detect the hardware bug we need to clear the entry
702 raw
[0] = raw
[1] = 0UL;
704 /* Update head pointer of hardware ring-buffer */
705 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
706 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
708 /* Handle PPR entry */
709 iommu_handle_ppr_entry(iommu
, entry
);
711 /* Refresh ring-buffer information */
712 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
713 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
717 #ifdef CONFIG_IRQ_REMAP
718 static int (*iommu_ga_log_notifier
)(u32
);
720 int amd_iommu_register_ga_log_notifier(int (*notifier
)(u32
))
722 iommu_ga_log_notifier
= notifier
;
726 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier
);
728 static void iommu_poll_ga_log(struct amd_iommu
*iommu
)
730 u32 head
, tail
, cnt
= 0;
732 if (iommu
->ga_log
== NULL
)
735 head
= readl(iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
736 tail
= readl(iommu
->mmio_base
+ MMIO_GA_TAIL_OFFSET
);
738 while (head
!= tail
) {
742 raw
= (u64
*)(iommu
->ga_log
+ head
);
745 /* Avoid memcpy function-call overhead */
748 /* Update head pointer of hardware ring-buffer */
749 head
= (head
+ GA_ENTRY_SIZE
) % GA_LOG_SIZE
;
750 writel(head
, iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
752 /* Handle GA entry */
753 switch (GA_REQ_TYPE(log_entry
)) {
755 if (!iommu_ga_log_notifier
)
758 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
759 __func__
, GA_DEVID(log_entry
),
762 if (iommu_ga_log_notifier(GA_TAG(log_entry
)) != 0)
763 pr_err("AMD-Vi: GA log notifier failed.\n");
770 #endif /* CONFIG_IRQ_REMAP */
772 #define AMD_IOMMU_INT_MASK \
773 (MMIO_STATUS_EVT_INT_MASK | \
774 MMIO_STATUS_PPR_INT_MASK | \
775 MMIO_STATUS_GALOG_INT_MASK)
777 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
779 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
780 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
782 while (status
& AMD_IOMMU_INT_MASK
) {
783 /* Enable EVT and PPR and GA interrupts again */
784 writel(AMD_IOMMU_INT_MASK
,
785 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
787 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
788 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
789 iommu_poll_events(iommu
);
792 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
793 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
794 iommu_poll_ppr_log(iommu
);
797 #ifdef CONFIG_IRQ_REMAP
798 if (status
& MMIO_STATUS_GALOG_INT_MASK
) {
799 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
800 iommu_poll_ga_log(iommu
);
805 * Hardware bug: ERBT1312
806 * When re-enabling interrupt (by writing 1
807 * to clear the bit), the hardware might also try to set
808 * the interrupt bit in the event status register.
809 * In this scenario, the bit will be set, and disable
810 * subsequent interrupts.
812 * Workaround: The IOMMU driver should read back the
813 * status register and check if the interrupt bits are cleared.
814 * If not, driver will need to go through the interrupt handler
815 * again and re-clear the bits
817 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
822 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
824 return IRQ_WAKE_THREAD
;
827 /****************************************************************************
829 * IOMMU command queuing functions
831 ****************************************************************************/
833 static int wait_on_sem(volatile u64
*sem
)
837 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
842 if (i
== LOOP_TIMEOUT
) {
843 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
850 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
851 struct iommu_cmd
*cmd
,
856 target
= iommu
->cmd_buf
+ tail
;
857 tail
= (tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
859 /* Copy command to buffer */
860 memcpy(target
, cmd
, sizeof(*cmd
));
862 /* Tell the IOMMU about it */
863 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
866 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
868 WARN_ON(address
& 0x7ULL
);
870 memset(cmd
, 0, sizeof(*cmd
));
871 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
872 cmd
->data
[1] = upper_32_bits(__pa(address
));
874 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
877 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
879 memset(cmd
, 0, sizeof(*cmd
));
880 cmd
->data
[0] = devid
;
881 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
884 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
885 size_t size
, u16 domid
, int pde
)
890 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
895 * If we have to flush more than one page, flush all
896 * TLB entries for this domain
898 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
902 address
&= PAGE_MASK
;
904 memset(cmd
, 0, sizeof(*cmd
));
905 cmd
->data
[1] |= domid
;
906 cmd
->data
[2] = lower_32_bits(address
);
907 cmd
->data
[3] = upper_32_bits(address
);
908 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
909 if (s
) /* size bit - we flush more than one 4kb page */
910 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
911 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
912 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
915 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
916 u64 address
, size_t size
)
921 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
926 * If we have to flush more than one page, flush all
927 * TLB entries for this domain
929 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
933 address
&= PAGE_MASK
;
935 memset(cmd
, 0, sizeof(*cmd
));
936 cmd
->data
[0] = devid
;
937 cmd
->data
[0] |= (qdep
& 0xff) << 24;
938 cmd
->data
[1] = devid
;
939 cmd
->data
[2] = lower_32_bits(address
);
940 cmd
->data
[3] = upper_32_bits(address
);
941 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
943 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
946 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
947 u64 address
, bool size
)
949 memset(cmd
, 0, sizeof(*cmd
));
951 address
&= ~(0xfffULL
);
953 cmd
->data
[0] = pasid
;
954 cmd
->data
[1] = domid
;
955 cmd
->data
[2] = lower_32_bits(address
);
956 cmd
->data
[3] = upper_32_bits(address
);
957 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
958 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
960 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
961 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
964 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
965 int qdep
, u64 address
, bool size
)
967 memset(cmd
, 0, sizeof(*cmd
));
969 address
&= ~(0xfffULL
);
971 cmd
->data
[0] = devid
;
972 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
973 cmd
->data
[0] |= (qdep
& 0xff) << 24;
974 cmd
->data
[1] = devid
;
975 cmd
->data
[1] |= (pasid
& 0xff) << 16;
976 cmd
->data
[2] = lower_32_bits(address
);
977 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
978 cmd
->data
[3] = upper_32_bits(address
);
980 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
981 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
984 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
985 int status
, int tag
, bool gn
)
987 memset(cmd
, 0, sizeof(*cmd
));
989 cmd
->data
[0] = devid
;
991 cmd
->data
[1] = pasid
;
992 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
994 cmd
->data
[3] = tag
& 0x1ff;
995 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
997 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
1000 static void build_inv_all(struct iommu_cmd
*cmd
)
1002 memset(cmd
, 0, sizeof(*cmd
));
1003 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
1006 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
1008 memset(cmd
, 0, sizeof(*cmd
));
1009 cmd
->data
[0] = devid
;
1010 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
1014 * Writes the command to the IOMMUs command buffer and informs the
1015 * hardware about the new command.
1017 static int __iommu_queue_command_sync(struct amd_iommu
*iommu
,
1018 struct iommu_cmd
*cmd
,
1021 u32 left
, tail
, head
, next_tail
;
1025 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
1026 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
1027 next_tail
= (tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
1028 left
= (head
- next_tail
) % CMD_BUFFER_SIZE
;
1031 struct iommu_cmd sync_cmd
;
1036 build_completion_wait(&sync_cmd
, (u64
)&iommu
->cmd_sem
);
1037 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
1039 if ((ret
= wait_on_sem(&iommu
->cmd_sem
)) != 0)
1045 copy_cmd_to_buffer(iommu
, cmd
, tail
);
1047 /* We need to sync now to make sure all commands are processed */
1048 iommu
->need_sync
= sync
;
1053 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
1054 struct iommu_cmd
*cmd
,
1057 unsigned long flags
;
1060 spin_lock_irqsave(&iommu
->lock
, flags
);
1061 ret
= __iommu_queue_command_sync(iommu
, cmd
, sync
);
1062 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1067 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1069 return iommu_queue_command_sync(iommu
, cmd
, true);
1073 * This function queues a completion wait command into the command
1074 * buffer of an IOMMU
1076 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1078 struct iommu_cmd cmd
;
1079 unsigned long flags
;
1082 if (!iommu
->need_sync
)
1086 build_completion_wait(&cmd
, (u64
)&iommu
->cmd_sem
);
1088 spin_lock_irqsave(&iommu
->lock
, flags
);
1092 ret
= __iommu_queue_command_sync(iommu
, &cmd
, false);
1096 ret
= wait_on_sem(&iommu
->cmd_sem
);
1099 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1104 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1106 struct iommu_cmd cmd
;
1108 build_inv_dte(&cmd
, devid
);
1110 return iommu_queue_command(iommu
, &cmd
);
1113 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1117 for (devid
= 0; devid
<= 0xffff; ++devid
)
1118 iommu_flush_dte(iommu
, devid
);
1120 iommu_completion_wait(iommu
);
1124 * This function uses heavy locking and may disable irqs for some time. But
1125 * this is no issue because it is only called during resume.
1127 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1131 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1132 struct iommu_cmd cmd
;
1133 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1135 iommu_queue_command(iommu
, &cmd
);
1138 iommu_completion_wait(iommu
);
1141 static void iommu_flush_all(struct amd_iommu
*iommu
)
1143 struct iommu_cmd cmd
;
1145 build_inv_all(&cmd
);
1147 iommu_queue_command(iommu
, &cmd
);
1148 iommu_completion_wait(iommu
);
1151 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1153 struct iommu_cmd cmd
;
1155 build_inv_irt(&cmd
, devid
);
1157 iommu_queue_command(iommu
, &cmd
);
1160 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1164 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1165 iommu_flush_irt(iommu
, devid
);
1167 iommu_completion_wait(iommu
);
1170 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1172 if (iommu_feature(iommu
, FEATURE_IA
)) {
1173 iommu_flush_all(iommu
);
1175 iommu_flush_dte_all(iommu
);
1176 iommu_flush_irt_all(iommu
);
1177 iommu_flush_tlb_all(iommu
);
1182 * Command send function for flushing on-device TLB
1184 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1185 u64 address
, size_t size
)
1187 struct amd_iommu
*iommu
;
1188 struct iommu_cmd cmd
;
1191 qdep
= dev_data
->ats
.qdep
;
1192 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1194 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1196 return iommu_queue_command(iommu
, &cmd
);
1200 * Command send function for invalidating a device table entry
1202 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1204 struct amd_iommu
*iommu
;
1208 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1209 alias
= dev_data
->alias
;
1211 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1212 if (!ret
&& alias
!= dev_data
->devid
)
1213 ret
= iommu_flush_dte(iommu
, alias
);
1217 if (dev_data
->ats
.enabled
)
1218 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1224 * TLB invalidation function which is called from the mapping functions.
1225 * It invalidates a single PTE if the range to flush is within a single
1226 * page. Otherwise it flushes the whole TLB of the IOMMU.
1228 static void __domain_flush_pages(struct protection_domain
*domain
,
1229 u64 address
, size_t size
, int pde
)
1231 struct iommu_dev_data
*dev_data
;
1232 struct iommu_cmd cmd
;
1235 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1237 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1238 if (!domain
->dev_iommu
[i
])
1242 * Devices of this domain are behind this IOMMU
1243 * We need a TLB flush
1245 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1248 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1250 if (!dev_data
->ats
.enabled
)
1253 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1259 static void domain_flush_pages(struct protection_domain
*domain
,
1260 u64 address
, size_t size
)
1262 __domain_flush_pages(domain
, address
, size
, 0);
1265 /* Flush the whole IO/TLB for a given protection domain */
1266 static void domain_flush_tlb(struct protection_domain
*domain
)
1268 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1271 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1272 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1274 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1277 static void domain_flush_complete(struct protection_domain
*domain
)
1281 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1282 if (domain
&& !domain
->dev_iommu
[i
])
1286 * Devices of this domain are behind this IOMMU
1287 * We need to wait for completion of all commands.
1289 iommu_completion_wait(amd_iommus
[i
]);
1295 * This function flushes the DTEs for all devices in domain
1297 static void domain_flush_devices(struct protection_domain
*domain
)
1299 struct iommu_dev_data
*dev_data
;
1301 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1302 device_flush_dte(dev_data
);
1305 /****************************************************************************
1307 * The functions below are used the create the page table mappings for
1308 * unity mapped regions.
1310 ****************************************************************************/
1313 * This function is used to add another level to an IO page table. Adding
1314 * another level increases the size of the address space by 9 bits to a size up
1317 static bool increase_address_space(struct protection_domain
*domain
,
1322 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1323 /* address space already 64 bit large */
1326 pte
= (void *)get_zeroed_page(gfp
);
1330 *pte
= PM_LEVEL_PDE(domain
->mode
,
1331 virt_to_phys(domain
->pt_root
));
1332 domain
->pt_root
= pte
;
1334 domain
->updated
= true;
1339 static u64
*alloc_pte(struct protection_domain
*domain
,
1340 unsigned long address
,
1341 unsigned long page_size
,
1348 BUG_ON(!is_power_of_2(page_size
));
1350 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1351 increase_address_space(domain
, gfp
);
1353 level
= domain
->mode
- 1;
1354 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1355 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1356 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1358 while (level
> end_lvl
) {
1363 if (!IOMMU_PTE_PRESENT(__pte
)) {
1364 page
= (u64
*)get_zeroed_page(gfp
);
1368 __npte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1370 /* pte could have been changed somewhere. */
1371 if (cmpxchg64(pte
, __pte
, __npte
) != __pte
) {
1372 free_page((unsigned long)page
);
1377 /* No level skipping support yet */
1378 if (PM_PTE_LEVEL(*pte
) != level
)
1383 pte
= IOMMU_PTE_PAGE(*pte
);
1385 if (pte_page
&& level
== end_lvl
)
1388 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1395 * This function checks if there is a PTE for a given dma address. If
1396 * there is one, it returns the pointer to it.
1398 static u64
*fetch_pte(struct protection_domain
*domain
,
1399 unsigned long address
,
1400 unsigned long *page_size
)
1405 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1408 level
= domain
->mode
- 1;
1409 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1410 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1415 if (!IOMMU_PTE_PRESENT(*pte
))
1419 if (PM_PTE_LEVEL(*pte
) == 7 ||
1420 PM_PTE_LEVEL(*pte
) == 0)
1423 /* No level skipping support yet */
1424 if (PM_PTE_LEVEL(*pte
) != level
)
1429 /* Walk to the next level */
1430 pte
= IOMMU_PTE_PAGE(*pte
);
1431 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1432 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1435 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1436 unsigned long pte_mask
;
1439 * If we have a series of large PTEs, make
1440 * sure to return a pointer to the first one.
1442 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1443 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1444 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1451 * Generic mapping functions. It maps a physical address into a DMA
1452 * address space. It allocates the page table pages if necessary.
1453 * In the future it can be extended to a generic mapping function
1454 * supporting all features of AMD IOMMU page tables like level skipping
1455 * and full 64 bit address spaces.
1457 static int iommu_map_page(struct protection_domain
*dom
,
1458 unsigned long bus_addr
,
1459 unsigned long phys_addr
,
1460 unsigned long page_size
,
1467 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1468 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1470 if (!(prot
& IOMMU_PROT_MASK
))
1473 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1474 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, gfp
);
1479 for (i
= 0; i
< count
; ++i
)
1480 if (IOMMU_PTE_PRESENT(pte
[i
]))
1484 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1485 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1487 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1489 if (prot
& IOMMU_PROT_IR
)
1490 __pte
|= IOMMU_PTE_IR
;
1491 if (prot
& IOMMU_PROT_IW
)
1492 __pte
|= IOMMU_PTE_IW
;
1494 for (i
= 0; i
< count
; ++i
)
1502 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1503 unsigned long bus_addr
,
1504 unsigned long page_size
)
1506 unsigned long long unmapped
;
1507 unsigned long unmap_size
;
1510 BUG_ON(!is_power_of_2(page_size
));
1514 while (unmapped
< page_size
) {
1516 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1521 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1522 for (i
= 0; i
< count
; i
++)
1526 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1527 unmapped
+= unmap_size
;
1530 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1535 /****************************************************************************
1537 * The next functions belong to the address allocator for the dma_ops
1538 * interface functions.
1540 ****************************************************************************/
1543 static unsigned long dma_ops_alloc_iova(struct device
*dev
,
1544 struct dma_ops_domain
*dma_dom
,
1545 unsigned int pages
, u64 dma_mask
)
1547 unsigned long pfn
= 0;
1549 pages
= __roundup_pow_of_two(pages
);
1551 if (dma_mask
> DMA_BIT_MASK(32))
1552 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1553 IOVA_PFN(DMA_BIT_MASK(32)));
1556 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
, IOVA_PFN(dma_mask
));
1558 return (pfn
<< PAGE_SHIFT
);
1561 static void dma_ops_free_iova(struct dma_ops_domain
*dma_dom
,
1562 unsigned long address
,
1565 pages
= __roundup_pow_of_two(pages
);
1566 address
>>= PAGE_SHIFT
;
1568 free_iova_fast(&dma_dom
->iovad
, address
, pages
);
1571 /****************************************************************************
1573 * The next functions belong to the domain allocation. A domain is
1574 * allocated for every IOMMU as the default domain. If device isolation
1575 * is enabled, every device get its own domain. The most important thing
1576 * about domains is the page table mapping the DMA address space they
1579 ****************************************************************************/
1582 * This function adds a protection domain to the global protection domain list
1584 static void add_domain_to_list(struct protection_domain
*domain
)
1586 unsigned long flags
;
1588 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1589 list_add(&domain
->list
, &amd_iommu_pd_list
);
1590 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1594 * This function removes a protection domain to the global
1595 * protection domain list
1597 static void del_domain_from_list(struct protection_domain
*domain
)
1599 unsigned long flags
;
1601 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1602 list_del(&domain
->list
);
1603 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1606 static u16
domain_id_alloc(void)
1608 unsigned long flags
;
1611 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1612 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1614 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1615 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1618 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1623 static void domain_id_free(int id
)
1625 unsigned long flags
;
1627 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1628 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1629 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1630 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1633 #define DEFINE_FREE_PT_FN(LVL, FN) \
1634 static void free_pt_##LVL (unsigned long __pt) \
1642 for (i = 0; i < 512; ++i) { \
1643 /* PTE present? */ \
1644 if (!IOMMU_PTE_PRESENT(pt[i])) \
1648 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1649 PM_PTE_LEVEL(pt[i]) == 7) \
1652 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1655 free_page((unsigned long)pt); \
1658 DEFINE_FREE_PT_FN(l2
, free_page
)
1659 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1660 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1661 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1662 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1664 static void free_pagetable(struct protection_domain
*domain
)
1666 unsigned long root
= (unsigned long)domain
->pt_root
;
1668 switch (domain
->mode
) {
1669 case PAGE_MODE_NONE
:
1671 case PAGE_MODE_1_LEVEL
:
1674 case PAGE_MODE_2_LEVEL
:
1677 case PAGE_MODE_3_LEVEL
:
1680 case PAGE_MODE_4_LEVEL
:
1683 case PAGE_MODE_5_LEVEL
:
1686 case PAGE_MODE_6_LEVEL
:
1694 static void free_gcr3_tbl_level1(u64
*tbl
)
1699 for (i
= 0; i
< 512; ++i
) {
1700 if (!(tbl
[i
] & GCR3_VALID
))
1703 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1705 free_page((unsigned long)ptr
);
1709 static void free_gcr3_tbl_level2(u64
*tbl
)
1714 for (i
= 0; i
< 512; ++i
) {
1715 if (!(tbl
[i
] & GCR3_VALID
))
1718 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1720 free_gcr3_tbl_level1(ptr
);
1724 static void free_gcr3_table(struct protection_domain
*domain
)
1726 if (domain
->glx
== 2)
1727 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1728 else if (domain
->glx
== 1)
1729 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1731 BUG_ON(domain
->glx
!= 0);
1733 free_page((unsigned long)domain
->gcr3_tbl
);
1737 * Free a domain, only used if something went wrong in the
1738 * allocation path and we need to free an already allocated page table
1740 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1745 del_domain_from_list(&dom
->domain
);
1747 put_iova_domain(&dom
->iovad
);
1749 free_pagetable(&dom
->domain
);
1752 domain_id_free(dom
->domain
.id
);
1758 * Allocates a new protection domain usable for the dma_ops functions.
1759 * It also initializes the page table and the address allocator data
1760 * structures required for the dma_ops interface
1762 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1764 struct dma_ops_domain
*dma_dom
;
1766 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1770 if (protection_domain_init(&dma_dom
->domain
))
1773 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
1774 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1775 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1776 if (!dma_dom
->domain
.pt_root
)
1779 init_iova_domain(&dma_dom
->iovad
, PAGE_SIZE
,
1780 IOVA_START_PFN
, DMA_32BIT_PFN
);
1782 /* Initialize reserved ranges */
1783 copy_reserved_iova(&reserved_iova_ranges
, &dma_dom
->iovad
);
1785 add_domain_to_list(&dma_dom
->domain
);
1790 dma_ops_domain_free(dma_dom
);
1796 * little helper function to check whether a given protection domain is a
1799 static bool dma_ops_domain(struct protection_domain
*domain
)
1801 return domain
->flags
& PD_DMA_OPS_MASK
;
1804 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
1809 if (domain
->mode
!= PAGE_MODE_NONE
)
1810 pte_root
= virt_to_phys(domain
->pt_root
);
1812 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1813 << DEV_ENTRY_MODE_SHIFT
;
1814 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1816 flags
= amd_iommu_dev_table
[devid
].data
[1];
1819 flags
|= DTE_FLAG_IOTLB
;
1821 if (domain
->flags
& PD_IOMMUV2_MASK
) {
1822 u64 gcr3
= __pa(domain
->gcr3_tbl
);
1823 u64 glx
= domain
->glx
;
1826 pte_root
|= DTE_FLAG_GV
;
1827 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
1829 /* First mask out possible old values for GCR3 table */
1830 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
1833 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
1836 /* Encode GCR3 table into DTE */
1837 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
1840 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
1843 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
1847 flags
&= ~(0xffffUL
);
1848 flags
|= domain
->id
;
1850 amd_iommu_dev_table
[devid
].data
[1] = flags
;
1851 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
1854 static void clear_dte_entry(u16 devid
)
1856 /* remove entry from the device table seen by the hardware */
1857 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1858 amd_iommu_dev_table
[devid
].data
[1] &= DTE_FLAG_MASK
;
1860 amd_iommu_apply_erratum_63(devid
);
1863 static void do_attach(struct iommu_dev_data
*dev_data
,
1864 struct protection_domain
*domain
)
1866 struct amd_iommu
*iommu
;
1870 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1871 alias
= dev_data
->alias
;
1872 ats
= dev_data
->ats
.enabled
;
1874 /* Update data structures */
1875 dev_data
->domain
= domain
;
1876 list_add(&dev_data
->list
, &domain
->dev_list
);
1878 /* Do reference counting */
1879 domain
->dev_iommu
[iommu
->index
] += 1;
1880 domain
->dev_cnt
+= 1;
1882 /* Update device table */
1883 set_dte_entry(dev_data
->devid
, domain
, ats
);
1884 if (alias
!= dev_data
->devid
)
1885 set_dte_entry(alias
, domain
, ats
);
1887 device_flush_dte(dev_data
);
1890 static void do_detach(struct iommu_dev_data
*dev_data
)
1892 struct amd_iommu
*iommu
;
1896 * First check if the device is still attached. It might already
1897 * be detached from its domain because the generic
1898 * iommu_detach_group code detached it and we try again here in
1899 * our alias handling.
1901 if (!dev_data
->domain
)
1904 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1905 alias
= dev_data
->alias
;
1907 /* decrease reference counters */
1908 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
1909 dev_data
->domain
->dev_cnt
-= 1;
1911 /* Update data structures */
1912 dev_data
->domain
= NULL
;
1913 list_del(&dev_data
->list
);
1914 clear_dte_entry(dev_data
->devid
);
1915 if (alias
!= dev_data
->devid
)
1916 clear_dte_entry(alias
);
1918 /* Flush the DTE entry */
1919 device_flush_dte(dev_data
);
1923 * If a device is not yet associated with a domain, this function does
1924 * assigns it visible for the hardware
1926 static int __attach_device(struct iommu_dev_data
*dev_data
,
1927 struct protection_domain
*domain
)
1932 * Must be called with IRQs disabled. Warn here to detect early
1935 WARN_ON(!irqs_disabled());
1938 spin_lock(&domain
->lock
);
1941 if (dev_data
->domain
!= NULL
)
1944 /* Attach alias group root */
1945 do_attach(dev_data
, domain
);
1952 spin_unlock(&domain
->lock
);
1958 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
1960 pci_disable_ats(pdev
);
1961 pci_disable_pri(pdev
);
1962 pci_disable_pasid(pdev
);
1965 /* FIXME: Change generic reset-function to do the same */
1966 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
1971 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
1975 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
1976 control
|= PCI_PRI_CTRL_RESET
;
1977 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
1982 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
1987 /* FIXME: Hardcode number of outstanding requests for now */
1989 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
1991 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
1993 /* Only allow access to user-accessible pages */
1994 ret
= pci_enable_pasid(pdev
, 0);
1998 /* First reset the PRI state of the device */
1999 ret
= pci_reset_pri(pdev
);
2004 ret
= pci_enable_pri(pdev
, reqs
);
2009 ret
= pri_reset_while_enabled(pdev
);
2014 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2021 pci_disable_pri(pdev
);
2022 pci_disable_pasid(pdev
);
2027 /* FIXME: Move this to PCI code */
2028 #define PCI_PRI_TLP_OFF (1 << 15)
2030 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2035 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2039 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2041 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2045 * If a device is not yet associated with a domain, this function
2046 * assigns it visible for the hardware
2048 static int attach_device(struct device
*dev
,
2049 struct protection_domain
*domain
)
2051 struct pci_dev
*pdev
;
2052 struct iommu_dev_data
*dev_data
;
2053 unsigned long flags
;
2056 dev_data
= get_dev_data(dev
);
2058 if (!dev_is_pci(dev
))
2059 goto skip_ats_check
;
2061 pdev
= to_pci_dev(dev
);
2062 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2063 if (!dev_data
->passthrough
)
2066 if (dev_data
->iommu_v2
) {
2067 if (pdev_iommuv2_enable(pdev
) != 0)
2070 dev_data
->ats
.enabled
= true;
2071 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2072 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2074 } else if (amd_iommu_iotlb_sup
&&
2075 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2076 dev_data
->ats
.enabled
= true;
2077 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2081 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2082 ret
= __attach_device(dev_data
, domain
);
2083 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2086 * We might boot into a crash-kernel here. The crashed kernel
2087 * left the caches in the IOMMU dirty. So we have to flush
2088 * here to evict all dirty stuff.
2090 domain_flush_tlb_pde(domain
);
2096 * Removes a device from a protection domain (unlocked)
2098 static void __detach_device(struct iommu_dev_data
*dev_data
)
2100 struct protection_domain
*domain
;
2103 * Must be called with IRQs disabled. Warn here to detect early
2106 WARN_ON(!irqs_disabled());
2108 if (WARN_ON(!dev_data
->domain
))
2111 domain
= dev_data
->domain
;
2113 spin_lock(&domain
->lock
);
2115 do_detach(dev_data
);
2117 spin_unlock(&domain
->lock
);
2121 * Removes a device from a protection domain (with devtable_lock held)
2123 static void detach_device(struct device
*dev
)
2125 struct protection_domain
*domain
;
2126 struct iommu_dev_data
*dev_data
;
2127 unsigned long flags
;
2129 dev_data
= get_dev_data(dev
);
2130 domain
= dev_data
->domain
;
2132 /* lock device table */
2133 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2134 __detach_device(dev_data
);
2135 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2137 if (!dev_is_pci(dev
))
2140 if (domain
->flags
& PD_IOMMUV2_MASK
&& dev_data
->iommu_v2
)
2141 pdev_iommuv2_disable(to_pci_dev(dev
));
2142 else if (dev_data
->ats
.enabled
)
2143 pci_disable_ats(to_pci_dev(dev
));
2145 dev_data
->ats
.enabled
= false;
2148 static int amd_iommu_add_device(struct device
*dev
)
2150 struct iommu_dev_data
*dev_data
;
2151 struct iommu_domain
*domain
;
2152 struct amd_iommu
*iommu
;
2155 if (!check_device(dev
) || get_dev_data(dev
))
2158 devid
= get_device_id(dev
);
2162 iommu
= amd_iommu_rlookup_table
[devid
];
2164 ret
= iommu_init_device(dev
);
2166 if (ret
!= -ENOTSUPP
)
2167 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2170 iommu_ignore_device(dev
);
2171 dev
->dma_ops
= &nommu_dma_ops
;
2174 init_iommu_group(dev
);
2176 dev_data
= get_dev_data(dev
);
2180 if (iommu_pass_through
|| dev_data
->iommu_v2
)
2181 iommu_request_dm_for_dev(dev
);
2183 /* Domains are initialized for this device - have a look what we ended up with */
2184 domain
= iommu_get_domain_for_dev(dev
);
2185 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
)
2186 dev_data
->passthrough
= true;
2188 dev
->dma_ops
= &amd_iommu_dma_ops
;
2191 iommu_completion_wait(iommu
);
2196 static void amd_iommu_remove_device(struct device
*dev
)
2198 struct amd_iommu
*iommu
;
2201 if (!check_device(dev
))
2204 devid
= get_device_id(dev
);
2208 iommu
= amd_iommu_rlookup_table
[devid
];
2210 iommu_uninit_device(dev
);
2211 iommu_completion_wait(iommu
);
2214 static struct iommu_group
*amd_iommu_device_group(struct device
*dev
)
2216 if (dev_is_pci(dev
))
2217 return pci_device_group(dev
);
2219 return acpihid_device_group(dev
);
2222 /*****************************************************************************
2224 * The next functions belong to the dma_ops mapping/unmapping code.
2226 *****************************************************************************/
2228 static void __queue_flush(struct flush_queue
*queue
)
2230 struct protection_domain
*domain
;
2231 unsigned long flags
;
2234 /* First flush TLB of all known domains */
2235 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
2236 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
)
2237 domain_flush_tlb(domain
);
2238 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
2240 /* Wait until flushes have completed */
2241 domain_flush_complete(NULL
);
2243 for (idx
= 0; idx
< queue
->next
; ++idx
) {
2244 struct flush_queue_entry
*entry
;
2246 entry
= queue
->entries
+ idx
;
2248 free_iova_fast(&entry
->dma_dom
->iovad
,
2252 /* Not really necessary, just to make sure we catch any bugs */
2253 entry
->dma_dom
= NULL
;
2259 static void queue_flush_all(void)
2263 for_each_possible_cpu(cpu
) {
2264 struct flush_queue
*queue
;
2265 unsigned long flags
;
2267 queue
= per_cpu_ptr(&flush_queue
, cpu
);
2268 spin_lock_irqsave(&queue
->lock
, flags
);
2269 if (queue
->next
> 0)
2270 __queue_flush(queue
);
2271 spin_unlock_irqrestore(&queue
->lock
, flags
);
2275 static void queue_flush_timeout(unsigned long unsused
)
2277 atomic_set(&queue_timer_on
, 0);
2281 static void queue_add(struct dma_ops_domain
*dma_dom
,
2282 unsigned long address
, unsigned long pages
)
2284 struct flush_queue_entry
*entry
;
2285 struct flush_queue
*queue
;
2286 unsigned long flags
;
2289 pages
= __roundup_pow_of_two(pages
);
2290 address
>>= PAGE_SHIFT
;
2292 queue
= get_cpu_ptr(&flush_queue
);
2293 spin_lock_irqsave(&queue
->lock
, flags
);
2295 if (queue
->next
== FLUSH_QUEUE_SIZE
)
2296 __queue_flush(queue
);
2298 idx
= queue
->next
++;
2299 entry
= queue
->entries
+ idx
;
2301 entry
->iova_pfn
= address
;
2302 entry
->pages
= pages
;
2303 entry
->dma_dom
= dma_dom
;
2305 spin_unlock_irqrestore(&queue
->lock
, flags
);
2307 if (atomic_cmpxchg(&queue_timer_on
, 0, 1) == 0)
2308 mod_timer(&queue_timer
, jiffies
+ msecs_to_jiffies(10));
2310 put_cpu_ptr(&flush_queue
);
2315 * In the dma_ops path we only have the struct device. This function
2316 * finds the corresponding IOMMU, the protection domain and the
2317 * requestor id for a given device.
2318 * If the device is not yet associated with a domain this is also done
2321 static struct protection_domain
*get_domain(struct device
*dev
)
2323 struct protection_domain
*domain
;
2325 if (!check_device(dev
))
2326 return ERR_PTR(-EINVAL
);
2328 domain
= get_dev_data(dev
)->domain
;
2329 if (!dma_ops_domain(domain
))
2330 return ERR_PTR(-EBUSY
);
2335 static void update_device_table(struct protection_domain
*domain
)
2337 struct iommu_dev_data
*dev_data
;
2339 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
2340 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2342 if (dev_data
->devid
== dev_data
->alias
)
2345 /* There is an alias, update device table entry for it */
2346 set_dte_entry(dev_data
->alias
, domain
, dev_data
->ats
.enabled
);
2350 static void update_domain(struct protection_domain
*domain
)
2352 if (!domain
->updated
)
2355 update_device_table(domain
);
2357 domain_flush_devices(domain
);
2358 domain_flush_tlb_pde(domain
);
2360 domain
->updated
= false;
2363 static int dir2prot(enum dma_data_direction direction
)
2365 if (direction
== DMA_TO_DEVICE
)
2366 return IOMMU_PROT_IR
;
2367 else if (direction
== DMA_FROM_DEVICE
)
2368 return IOMMU_PROT_IW
;
2369 else if (direction
== DMA_BIDIRECTIONAL
)
2370 return IOMMU_PROT_IW
| IOMMU_PROT_IR
;
2375 * This function contains common code for mapping of a physically
2376 * contiguous memory region into DMA address space. It is used by all
2377 * mapping functions provided with this IOMMU driver.
2378 * Must be called with the domain lock held.
2380 static dma_addr_t
__map_single(struct device
*dev
,
2381 struct dma_ops_domain
*dma_dom
,
2384 enum dma_data_direction direction
,
2387 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2388 dma_addr_t address
, start
, ret
;
2393 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2396 address
= dma_ops_alloc_iova(dev
, dma_dom
, pages
, dma_mask
);
2397 if (address
== DMA_ERROR_CODE
)
2400 prot
= dir2prot(direction
);
2403 for (i
= 0; i
< pages
; ++i
) {
2404 ret
= iommu_map_page(&dma_dom
->domain
, start
, paddr
,
2405 PAGE_SIZE
, prot
, GFP_ATOMIC
);
2414 if (unlikely(amd_iommu_np_cache
)) {
2415 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2416 domain_flush_complete(&dma_dom
->domain
);
2424 for (--i
; i
>= 0; --i
) {
2426 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2429 domain_flush_tlb(&dma_dom
->domain
);
2430 domain_flush_complete(&dma_dom
->domain
);
2432 dma_ops_free_iova(dma_dom
, address
, pages
);
2434 return DMA_ERROR_CODE
;
2438 * Does the reverse of the __map_single function. Must be called with
2439 * the domain lock held too
2441 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2442 dma_addr_t dma_addr
,
2446 dma_addr_t flush_addr
;
2447 dma_addr_t i
, start
;
2450 flush_addr
= dma_addr
;
2451 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2452 dma_addr
&= PAGE_MASK
;
2455 for (i
= 0; i
< pages
; ++i
) {
2456 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2460 if (amd_iommu_unmap_flush
) {
2461 dma_ops_free_iova(dma_dom
, dma_addr
, pages
);
2462 domain_flush_tlb(&dma_dom
->domain
);
2463 domain_flush_complete(&dma_dom
->domain
);
2465 queue_add(dma_dom
, dma_addr
, pages
);
2470 * The exported map_single function for dma_ops.
2472 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2473 unsigned long offset
, size_t size
,
2474 enum dma_data_direction dir
,
2475 unsigned long attrs
)
2477 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2478 struct protection_domain
*domain
;
2479 struct dma_ops_domain
*dma_dom
;
2482 domain
= get_domain(dev
);
2483 if (PTR_ERR(domain
) == -EINVAL
)
2484 return (dma_addr_t
)paddr
;
2485 else if (IS_ERR(domain
))
2486 return DMA_ERROR_CODE
;
2488 dma_mask
= *dev
->dma_mask
;
2489 dma_dom
= to_dma_ops_domain(domain
);
2491 return __map_single(dev
, dma_dom
, paddr
, size
, dir
, dma_mask
);
2495 * The exported unmap_single function for dma_ops.
2497 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2498 enum dma_data_direction dir
, unsigned long attrs
)
2500 struct protection_domain
*domain
;
2501 struct dma_ops_domain
*dma_dom
;
2503 domain
= get_domain(dev
);
2507 dma_dom
= to_dma_ops_domain(domain
);
2509 __unmap_single(dma_dom
, dma_addr
, size
, dir
);
2512 static int sg_num_pages(struct device
*dev
,
2513 struct scatterlist
*sglist
,
2516 unsigned long mask
, boundary_size
;
2517 struct scatterlist
*s
;
2520 mask
= dma_get_seg_boundary(dev
);
2521 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
2522 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
2524 for_each_sg(sglist
, s
, nelems
, i
) {
2527 s
->dma_address
= npages
<< PAGE_SHIFT
;
2528 p
= npages
% boundary_size
;
2529 n
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2530 if (p
+ n
> boundary_size
)
2531 npages
+= boundary_size
- p
;
2539 * The exported map_sg function for dma_ops (handles scatter-gather
2542 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2543 int nelems
, enum dma_data_direction direction
,
2544 unsigned long attrs
)
2546 int mapped_pages
= 0, npages
= 0, prot
= 0, i
;
2547 struct protection_domain
*domain
;
2548 struct dma_ops_domain
*dma_dom
;
2549 struct scatterlist
*s
;
2550 unsigned long address
;
2553 domain
= get_domain(dev
);
2557 dma_dom
= to_dma_ops_domain(domain
);
2558 dma_mask
= *dev
->dma_mask
;
2560 npages
= sg_num_pages(dev
, sglist
, nelems
);
2562 address
= dma_ops_alloc_iova(dev
, dma_dom
, npages
, dma_mask
);
2563 if (address
== DMA_ERROR_CODE
)
2566 prot
= dir2prot(direction
);
2568 /* Map all sg entries */
2569 for_each_sg(sglist
, s
, nelems
, i
) {
2570 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2572 for (j
= 0; j
< pages
; ++j
) {
2573 unsigned long bus_addr
, phys_addr
;
2576 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2577 phys_addr
= (sg_phys(s
) & PAGE_MASK
) + (j
<< PAGE_SHIFT
);
2578 ret
= iommu_map_page(domain
, bus_addr
, phys_addr
, PAGE_SIZE
, prot
, GFP_ATOMIC
);
2586 /* Everything is mapped - write the right values into s->dma_address */
2587 for_each_sg(sglist
, s
, nelems
, i
) {
2588 s
->dma_address
+= address
+ s
->offset
;
2589 s
->dma_length
= s
->length
;
2595 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2596 dev_name(dev
), npages
);
2598 for_each_sg(sglist
, s
, nelems
, i
) {
2599 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2601 for (j
= 0; j
< pages
; ++j
) {
2602 unsigned long bus_addr
;
2604 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2605 iommu_unmap_page(domain
, bus_addr
, PAGE_SIZE
);
2613 free_iova_fast(&dma_dom
->iovad
, address
, npages
);
2620 * The exported map_sg function for dma_ops (handles scatter-gather
2623 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2624 int nelems
, enum dma_data_direction dir
,
2625 unsigned long attrs
)
2627 struct protection_domain
*domain
;
2628 struct dma_ops_domain
*dma_dom
;
2629 unsigned long startaddr
;
2632 domain
= get_domain(dev
);
2636 startaddr
= sg_dma_address(sglist
) & PAGE_MASK
;
2637 dma_dom
= to_dma_ops_domain(domain
);
2638 npages
= sg_num_pages(dev
, sglist
, nelems
);
2640 __unmap_single(dma_dom
, startaddr
, npages
<< PAGE_SHIFT
, dir
);
2644 * The exported alloc_coherent function for dma_ops.
2646 static void *alloc_coherent(struct device
*dev
, size_t size
,
2647 dma_addr_t
*dma_addr
, gfp_t flag
,
2648 unsigned long attrs
)
2650 u64 dma_mask
= dev
->coherent_dma_mask
;
2651 struct protection_domain
*domain
;
2652 struct dma_ops_domain
*dma_dom
;
2655 domain
= get_domain(dev
);
2656 if (PTR_ERR(domain
) == -EINVAL
) {
2657 page
= alloc_pages(flag
, get_order(size
));
2658 *dma_addr
= page_to_phys(page
);
2659 return page_address(page
);
2660 } else if (IS_ERR(domain
))
2663 dma_dom
= to_dma_ops_domain(domain
);
2664 size
= PAGE_ALIGN(size
);
2665 dma_mask
= dev
->coherent_dma_mask
;
2666 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2669 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2671 if (!gfpflags_allow_blocking(flag
))
2674 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2675 get_order(size
), flag
);
2681 dma_mask
= *dev
->dma_mask
;
2683 *dma_addr
= __map_single(dev
, dma_dom
, page_to_phys(page
),
2684 size
, DMA_BIDIRECTIONAL
, dma_mask
);
2686 if (*dma_addr
== DMA_ERROR_CODE
)
2689 return page_address(page
);
2693 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2694 __free_pages(page
, get_order(size
));
2700 * The exported free_coherent function for dma_ops.
2702 static void free_coherent(struct device
*dev
, size_t size
,
2703 void *virt_addr
, dma_addr_t dma_addr
,
2704 unsigned long attrs
)
2706 struct protection_domain
*domain
;
2707 struct dma_ops_domain
*dma_dom
;
2710 page
= virt_to_page(virt_addr
);
2711 size
= PAGE_ALIGN(size
);
2713 domain
= get_domain(dev
);
2717 dma_dom
= to_dma_ops_domain(domain
);
2719 __unmap_single(dma_dom
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2722 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2723 __free_pages(page
, get_order(size
));
2727 * This function is called by the DMA layer to find out if we can handle a
2728 * particular device. It is part of the dma_ops.
2730 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2732 return check_device(dev
);
2735 static const struct dma_map_ops amd_iommu_dma_ops
= {
2736 .alloc
= alloc_coherent
,
2737 .free
= free_coherent
,
2738 .map_page
= map_page
,
2739 .unmap_page
= unmap_page
,
2741 .unmap_sg
= unmap_sg
,
2742 .dma_supported
= amd_iommu_dma_supported
,
2745 static int init_reserved_iova_ranges(void)
2747 struct pci_dev
*pdev
= NULL
;
2750 init_iova_domain(&reserved_iova_ranges
, PAGE_SIZE
,
2751 IOVA_START_PFN
, DMA_32BIT_PFN
);
2753 lockdep_set_class(&reserved_iova_ranges
.iova_rbtree_lock
,
2754 &reserved_rbtree_key
);
2756 /* MSI memory range */
2757 val
= reserve_iova(&reserved_iova_ranges
,
2758 IOVA_PFN(MSI_RANGE_START
), IOVA_PFN(MSI_RANGE_END
));
2760 pr_err("Reserving MSI range failed\n");
2764 /* HT memory range */
2765 val
= reserve_iova(&reserved_iova_ranges
,
2766 IOVA_PFN(HT_RANGE_START
), IOVA_PFN(HT_RANGE_END
));
2768 pr_err("Reserving HT range failed\n");
2773 * Memory used for PCI resources
2774 * FIXME: Check whether we can reserve the PCI-hole completly
2776 for_each_pci_dev(pdev
) {
2779 for (i
= 0; i
< PCI_NUM_RESOURCES
; ++i
) {
2780 struct resource
*r
= &pdev
->resource
[i
];
2782 if (!(r
->flags
& IORESOURCE_MEM
))
2785 val
= reserve_iova(&reserved_iova_ranges
,
2789 pr_err("Reserve pci-resource range failed\n");
2798 int __init
amd_iommu_init_api(void)
2800 int ret
, cpu
, err
= 0;
2802 ret
= iova_cache_get();
2806 ret
= init_reserved_iova_ranges();
2810 for_each_possible_cpu(cpu
) {
2811 struct flush_queue
*queue
= per_cpu_ptr(&flush_queue
, cpu
);
2813 queue
->entries
= kzalloc(FLUSH_QUEUE_SIZE
*
2814 sizeof(*queue
->entries
),
2816 if (!queue
->entries
)
2819 spin_lock_init(&queue
->lock
);
2822 err
= bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2825 #ifdef CONFIG_ARM_AMBA
2826 err
= bus_set_iommu(&amba_bustype
, &amd_iommu_ops
);
2830 err
= bus_set_iommu(&platform_bus_type
, &amd_iommu_ops
);
2836 for_each_possible_cpu(cpu
) {
2837 struct flush_queue
*queue
= per_cpu_ptr(&flush_queue
, cpu
);
2839 kfree(queue
->entries
);
2845 int __init
amd_iommu_init_dma_ops(void)
2847 setup_timer(&queue_timer
, queue_flush_timeout
, 0);
2848 atomic_set(&queue_timer_on
, 0);
2850 swiotlb
= iommu_pass_through
? 1 : 0;
2854 * In case we don't initialize SWIOTLB (actually the common case
2855 * when AMD IOMMU is enabled), make sure there are global
2856 * dma_ops set as a fall-back for devices not handled by this
2857 * driver (for example non-PCI devices).
2860 dma_ops
= &nommu_dma_ops
;
2862 if (amd_iommu_unmap_flush
)
2863 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2865 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2871 /*****************************************************************************
2873 * The following functions belong to the exported interface of AMD IOMMU
2875 * This interface allows access to lower level functions of the IOMMU
2876 * like protection domain handling and assignement of devices to domains
2877 * which is not possible with the dma_ops interface.
2879 *****************************************************************************/
2881 static void cleanup_domain(struct protection_domain
*domain
)
2883 struct iommu_dev_data
*entry
;
2884 unsigned long flags
;
2886 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2888 while (!list_empty(&domain
->dev_list
)) {
2889 entry
= list_first_entry(&domain
->dev_list
,
2890 struct iommu_dev_data
, list
);
2891 __detach_device(entry
);
2894 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2897 static void protection_domain_free(struct protection_domain
*domain
)
2902 del_domain_from_list(domain
);
2905 domain_id_free(domain
->id
);
2910 static int protection_domain_init(struct protection_domain
*domain
)
2912 spin_lock_init(&domain
->lock
);
2913 mutex_init(&domain
->api_lock
);
2914 domain
->id
= domain_id_alloc();
2917 INIT_LIST_HEAD(&domain
->dev_list
);
2922 static struct protection_domain
*protection_domain_alloc(void)
2924 struct protection_domain
*domain
;
2926 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2930 if (protection_domain_init(domain
))
2933 add_domain_to_list(domain
);
2943 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
2945 struct protection_domain
*pdomain
;
2946 struct dma_ops_domain
*dma_domain
;
2949 case IOMMU_DOMAIN_UNMANAGED
:
2950 pdomain
= protection_domain_alloc();
2954 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
2955 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2956 if (!pdomain
->pt_root
) {
2957 protection_domain_free(pdomain
);
2961 pdomain
->domain
.geometry
.aperture_start
= 0;
2962 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
2963 pdomain
->domain
.geometry
.force_aperture
= true;
2966 case IOMMU_DOMAIN_DMA
:
2967 dma_domain
= dma_ops_domain_alloc();
2969 pr_err("AMD-Vi: Failed to allocate\n");
2972 pdomain
= &dma_domain
->domain
;
2974 case IOMMU_DOMAIN_IDENTITY
:
2975 pdomain
= protection_domain_alloc();
2979 pdomain
->mode
= PAGE_MODE_NONE
;
2985 return &pdomain
->domain
;
2988 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
2990 struct protection_domain
*domain
;
2991 struct dma_ops_domain
*dma_dom
;
2993 domain
= to_pdomain(dom
);
2995 if (domain
->dev_cnt
> 0)
2996 cleanup_domain(domain
);
2998 BUG_ON(domain
->dev_cnt
!= 0);
3003 switch (dom
->type
) {
3004 case IOMMU_DOMAIN_DMA
:
3006 * First make sure the domain is no longer referenced from the
3011 /* Now release the domain */
3012 dma_dom
= to_dma_ops_domain(domain
);
3013 dma_ops_domain_free(dma_dom
);
3016 if (domain
->mode
!= PAGE_MODE_NONE
)
3017 free_pagetable(domain
);
3019 if (domain
->flags
& PD_IOMMUV2_MASK
)
3020 free_gcr3_table(domain
);
3022 protection_domain_free(domain
);
3027 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3030 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3031 struct amd_iommu
*iommu
;
3034 if (!check_device(dev
))
3037 devid
= get_device_id(dev
);
3041 if (dev_data
->domain
!= NULL
)
3044 iommu
= amd_iommu_rlookup_table
[devid
];
3048 #ifdef CONFIG_IRQ_REMAP
3049 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) &&
3050 (dom
->type
== IOMMU_DOMAIN_UNMANAGED
))
3051 dev_data
->use_vapic
= 0;
3054 iommu_completion_wait(iommu
);
3057 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3060 struct protection_domain
*domain
= to_pdomain(dom
);
3061 struct iommu_dev_data
*dev_data
;
3062 struct amd_iommu
*iommu
;
3065 if (!check_device(dev
))
3068 dev_data
= dev
->archdata
.iommu
;
3070 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3074 if (dev_data
->domain
)
3077 ret
= attach_device(dev
, domain
);
3079 #ifdef CONFIG_IRQ_REMAP
3080 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
3081 if (dom
->type
== IOMMU_DOMAIN_UNMANAGED
)
3082 dev_data
->use_vapic
= 1;
3084 dev_data
->use_vapic
= 0;
3088 iommu_completion_wait(iommu
);
3093 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3094 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3096 struct protection_domain
*domain
= to_pdomain(dom
);
3100 if (domain
->mode
== PAGE_MODE_NONE
)
3103 if (iommu_prot
& IOMMU_READ
)
3104 prot
|= IOMMU_PROT_IR
;
3105 if (iommu_prot
& IOMMU_WRITE
)
3106 prot
|= IOMMU_PROT_IW
;
3108 mutex_lock(&domain
->api_lock
);
3109 ret
= iommu_map_page(domain
, iova
, paddr
, page_size
, prot
, GFP_KERNEL
);
3110 mutex_unlock(&domain
->api_lock
);
3115 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3118 struct protection_domain
*domain
= to_pdomain(dom
);
3121 if (domain
->mode
== PAGE_MODE_NONE
)
3124 mutex_lock(&domain
->api_lock
);
3125 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3126 mutex_unlock(&domain
->api_lock
);
3128 domain_flush_tlb_pde(domain
);
3133 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3136 struct protection_domain
*domain
= to_pdomain(dom
);
3137 unsigned long offset_mask
, pte_pgsize
;
3140 if (domain
->mode
== PAGE_MODE_NONE
)
3143 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3145 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3148 offset_mask
= pte_pgsize
- 1;
3149 __pte
= *pte
& PM_ADDR_MASK
;
3151 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3154 static bool amd_iommu_capable(enum iommu_cap cap
)
3157 case IOMMU_CAP_CACHE_COHERENCY
:
3159 case IOMMU_CAP_INTR_REMAP
:
3160 return (irq_remapping_enabled
== 1);
3161 case IOMMU_CAP_NOEXEC
:
3168 static void amd_iommu_get_resv_regions(struct device
*dev
,
3169 struct list_head
*head
)
3171 struct iommu_resv_region
*region
;
3172 struct unity_map_entry
*entry
;
3175 devid
= get_device_id(dev
);
3179 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3183 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3186 length
= entry
->address_end
- entry
->address_start
;
3187 if (entry
->prot
& IOMMU_PROT_IR
)
3189 if (entry
->prot
& IOMMU_PROT_IW
)
3190 prot
|= IOMMU_WRITE
;
3192 region
= iommu_alloc_resv_region(entry
->address_start
,
3196 pr_err("Out of memory allocating dm-regions for %s\n",
3200 list_add_tail(®ion
->list
, head
);
3203 region
= iommu_alloc_resv_region(MSI_RANGE_START
,
3204 MSI_RANGE_END
- MSI_RANGE_START
+ 1,
3208 list_add_tail(®ion
->list
, head
);
3210 region
= iommu_alloc_resv_region(HT_RANGE_START
,
3211 HT_RANGE_END
- HT_RANGE_START
+ 1,
3212 0, IOMMU_RESV_RESERVED
);
3215 list_add_tail(®ion
->list
, head
);
3218 static void amd_iommu_put_resv_regions(struct device
*dev
,
3219 struct list_head
*head
)
3221 struct iommu_resv_region
*entry
, *next
;
3223 list_for_each_entry_safe(entry
, next
, head
, list
)
3227 static void amd_iommu_apply_resv_region(struct device
*dev
,
3228 struct iommu_domain
*domain
,
3229 struct iommu_resv_region
*region
)
3231 struct dma_ops_domain
*dma_dom
= to_dma_ops_domain(to_pdomain(domain
));
3232 unsigned long start
, end
;
3234 start
= IOVA_PFN(region
->start
);
3235 end
= IOVA_PFN(region
->start
+ region
->length
);
3237 WARN_ON_ONCE(reserve_iova(&dma_dom
->iovad
, start
, end
) == NULL
);
3240 const struct iommu_ops amd_iommu_ops
= {
3241 .capable
= amd_iommu_capable
,
3242 .domain_alloc
= amd_iommu_domain_alloc
,
3243 .domain_free
= amd_iommu_domain_free
,
3244 .attach_dev
= amd_iommu_attach_device
,
3245 .detach_dev
= amd_iommu_detach_device
,
3246 .map
= amd_iommu_map
,
3247 .unmap
= amd_iommu_unmap
,
3248 .map_sg
= default_iommu_map_sg
,
3249 .iova_to_phys
= amd_iommu_iova_to_phys
,
3250 .add_device
= amd_iommu_add_device
,
3251 .remove_device
= amd_iommu_remove_device
,
3252 .device_group
= amd_iommu_device_group
,
3253 .get_resv_regions
= amd_iommu_get_resv_regions
,
3254 .put_resv_regions
= amd_iommu_put_resv_regions
,
3255 .apply_resv_region
= amd_iommu_apply_resv_region
,
3256 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3259 /*****************************************************************************
3261 * The next functions do a basic initialization of IOMMU for pass through
3264 * In passthrough mode the IOMMU is initialized and enabled but not used for
3265 * DMA-API translation.
3267 *****************************************************************************/
3269 /* IOMMUv2 specific functions */
3270 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3272 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3274 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3276 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3278 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3280 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3282 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3284 struct protection_domain
*domain
= to_pdomain(dom
);
3285 unsigned long flags
;
3287 spin_lock_irqsave(&domain
->lock
, flags
);
3289 /* Update data structure */
3290 domain
->mode
= PAGE_MODE_NONE
;
3291 domain
->updated
= true;
3293 /* Make changes visible to IOMMUs */
3294 update_domain(domain
);
3296 /* Page-table is not visible to IOMMU anymore, so free it */
3297 free_pagetable(domain
);
3299 spin_unlock_irqrestore(&domain
->lock
, flags
);
3301 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3303 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3305 struct protection_domain
*domain
= to_pdomain(dom
);
3306 unsigned long flags
;
3309 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3312 /* Number of GCR3 table levels required */
3313 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3316 if (levels
> amd_iommu_max_glx_val
)
3319 spin_lock_irqsave(&domain
->lock
, flags
);
3322 * Save us all sanity checks whether devices already in the
3323 * domain support IOMMUv2. Just force that the domain has no
3324 * devices attached when it is switched into IOMMUv2 mode.
3327 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3331 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3332 if (domain
->gcr3_tbl
== NULL
)
3335 domain
->glx
= levels
;
3336 domain
->flags
|= PD_IOMMUV2_MASK
;
3337 domain
->updated
= true;
3339 update_domain(domain
);
3344 spin_unlock_irqrestore(&domain
->lock
, flags
);
3348 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3350 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3351 u64 address
, bool size
)
3353 struct iommu_dev_data
*dev_data
;
3354 struct iommu_cmd cmd
;
3357 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3360 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3363 * IOMMU TLB needs to be flushed before Device TLB to
3364 * prevent device TLB refill from IOMMU TLB
3366 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3367 if (domain
->dev_iommu
[i
] == 0)
3370 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3375 /* Wait until IOMMU TLB flushes are complete */
3376 domain_flush_complete(domain
);
3378 /* Now flush device TLBs */
3379 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3380 struct amd_iommu
*iommu
;
3384 There might be non-IOMMUv2 capable devices in an IOMMUv2
3387 if (!dev_data
->ats
.enabled
)
3390 qdep
= dev_data
->ats
.qdep
;
3391 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3393 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3394 qdep
, address
, size
);
3396 ret
= iommu_queue_command(iommu
, &cmd
);
3401 /* Wait until all device TLBs are flushed */
3402 domain_flush_complete(domain
);
3411 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3414 return __flush_pasid(domain
, pasid
, address
, false);
3417 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3420 struct protection_domain
*domain
= to_pdomain(dom
);
3421 unsigned long flags
;
3424 spin_lock_irqsave(&domain
->lock
, flags
);
3425 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3426 spin_unlock_irqrestore(&domain
->lock
, flags
);
3430 EXPORT_SYMBOL(amd_iommu_flush_page
);
3432 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3434 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3438 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3440 struct protection_domain
*domain
= to_pdomain(dom
);
3441 unsigned long flags
;
3444 spin_lock_irqsave(&domain
->lock
, flags
);
3445 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3446 spin_unlock_irqrestore(&domain
->lock
, flags
);
3450 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3452 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3459 index
= (pasid
>> (9 * level
)) & 0x1ff;
3465 if (!(*pte
& GCR3_VALID
)) {
3469 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3473 *pte
= __pa(root
) | GCR3_VALID
;
3476 root
= __va(*pte
& PAGE_MASK
);
3484 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3489 if (domain
->mode
!= PAGE_MODE_NONE
)
3492 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3496 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3498 return __amd_iommu_flush_tlb(domain
, pasid
);
3501 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3505 if (domain
->mode
!= PAGE_MODE_NONE
)
3508 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3514 return __amd_iommu_flush_tlb(domain
, pasid
);
3517 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3520 struct protection_domain
*domain
= to_pdomain(dom
);
3521 unsigned long flags
;
3524 spin_lock_irqsave(&domain
->lock
, flags
);
3525 ret
= __set_gcr3(domain
, pasid
, cr3
);
3526 spin_unlock_irqrestore(&domain
->lock
, flags
);
3530 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3532 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3534 struct protection_domain
*domain
= to_pdomain(dom
);
3535 unsigned long flags
;
3538 spin_lock_irqsave(&domain
->lock
, flags
);
3539 ret
= __clear_gcr3(domain
, pasid
);
3540 spin_unlock_irqrestore(&domain
->lock
, flags
);
3544 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3546 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3547 int status
, int tag
)
3549 struct iommu_dev_data
*dev_data
;
3550 struct amd_iommu
*iommu
;
3551 struct iommu_cmd cmd
;
3553 dev_data
= get_dev_data(&pdev
->dev
);
3554 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3556 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3557 tag
, dev_data
->pri_tlp
);
3559 return iommu_queue_command(iommu
, &cmd
);
3561 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3563 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3565 struct protection_domain
*pdomain
;
3567 pdomain
= get_domain(&pdev
->dev
);
3568 if (IS_ERR(pdomain
))
3571 /* Only return IOMMUv2 domains */
3572 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3575 return &pdomain
->domain
;
3577 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3579 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3581 struct iommu_dev_data
*dev_data
;
3583 if (!amd_iommu_v2_supported())
3586 dev_data
= get_dev_data(&pdev
->dev
);
3587 dev_data
->errata
|= (1 << erratum
);
3589 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3591 int amd_iommu_device_info(struct pci_dev
*pdev
,
3592 struct amd_iommu_device_info
*info
)
3597 if (pdev
== NULL
|| info
== NULL
)
3600 if (!amd_iommu_v2_supported())
3603 memset(info
, 0, sizeof(*info
));
3605 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3607 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3609 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3611 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3613 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3617 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3618 max_pasids
= min(max_pasids
, (1 << 20));
3620 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3621 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3623 features
= pci_pasid_features(pdev
);
3624 if (features
& PCI_PASID_CAP_EXEC
)
3625 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3626 if (features
& PCI_PASID_CAP_PRIV
)
3627 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3632 EXPORT_SYMBOL(amd_iommu_device_info
);
3634 #ifdef CONFIG_IRQ_REMAP
3636 /*****************************************************************************
3638 * Interrupt Remapping Implementation
3640 *****************************************************************************/
3642 static struct irq_chip amd_ir_chip
;
3644 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3645 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3646 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3647 #define DTE_IRQ_REMAP_ENABLE 1ULL
3649 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3653 dte
= amd_iommu_dev_table
[devid
].data
[2];
3654 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3655 dte
|= virt_to_phys(table
->table
);
3656 dte
|= DTE_IRQ_REMAP_INTCTL
;
3657 dte
|= DTE_IRQ_TABLE_LEN
;
3658 dte
|= DTE_IRQ_REMAP_ENABLE
;
3660 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3663 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3665 struct irq_remap_table
*table
= NULL
;
3666 struct amd_iommu
*iommu
;
3667 unsigned long flags
;
3670 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3672 iommu
= amd_iommu_rlookup_table
[devid
];
3676 table
= irq_lookup_table
[devid
];
3680 alias
= amd_iommu_alias_table
[devid
];
3681 table
= irq_lookup_table
[alias
];
3683 irq_lookup_table
[devid
] = table
;
3684 set_dte_irq_entry(devid
, table
);
3685 iommu_flush_dte(iommu
, devid
);
3689 /* Nothing there yet, allocate new irq remapping table */
3690 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3694 /* Initialize table spin-lock */
3695 spin_lock_init(&table
->lock
);
3698 /* Keep the first 32 indexes free for IOAPIC interrupts */
3699 table
->min_index
= 32;
3701 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3702 if (!table
->table
) {
3708 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
3709 memset(table
->table
, 0,
3710 MAX_IRQS_PER_TABLE
* sizeof(u32
));
3712 memset(table
->table
, 0,
3713 (MAX_IRQS_PER_TABLE
* (sizeof(u64
) * 2)));
3718 for (i
= 0; i
< 32; ++i
)
3719 iommu
->irte_ops
->set_allocated(table
, i
);
3722 irq_lookup_table
[devid
] = table
;
3723 set_dte_irq_entry(devid
, table
);
3724 iommu_flush_dte(iommu
, devid
);
3725 if (devid
!= alias
) {
3726 irq_lookup_table
[alias
] = table
;
3727 set_dte_irq_entry(alias
, table
);
3728 iommu_flush_dte(iommu
, alias
);
3732 iommu_completion_wait(iommu
);
3735 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3740 static int alloc_irq_index(u16 devid
, int count
)
3742 struct irq_remap_table
*table
;
3743 unsigned long flags
;
3745 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
3750 table
= get_irq_table(devid
, false);
3754 spin_lock_irqsave(&table
->lock
, flags
);
3756 /* Scan table for free entries */
3757 for (c
= 0, index
= table
->min_index
;
3758 index
< MAX_IRQS_PER_TABLE
;
3760 if (!iommu
->irte_ops
->is_allocated(table
, index
))
3767 iommu
->irte_ops
->set_allocated(table
, index
- c
+ 1);
3777 spin_unlock_irqrestore(&table
->lock
, flags
);
3782 static int modify_irte_ga(u16 devid
, int index
, struct irte_ga
*irte
,
3783 struct amd_ir_data
*data
)
3785 struct irq_remap_table
*table
;
3786 struct amd_iommu
*iommu
;
3787 unsigned long flags
;
3788 struct irte_ga
*entry
;
3790 iommu
= amd_iommu_rlookup_table
[devid
];
3794 table
= get_irq_table(devid
, false);
3798 spin_lock_irqsave(&table
->lock
, flags
);
3800 entry
= (struct irte_ga
*)table
->table
;
3801 entry
= &entry
[index
];
3802 entry
->lo
.fields_remap
.valid
= 0;
3803 entry
->hi
.val
= irte
->hi
.val
;
3804 entry
->lo
.val
= irte
->lo
.val
;
3805 entry
->lo
.fields_remap
.valid
= 1;
3809 spin_unlock_irqrestore(&table
->lock
, flags
);
3811 iommu_flush_irt(iommu
, devid
);
3812 iommu_completion_wait(iommu
);
3817 static int modify_irte(u16 devid
, int index
, union irte
*irte
)
3819 struct irq_remap_table
*table
;
3820 struct amd_iommu
*iommu
;
3821 unsigned long flags
;
3823 iommu
= amd_iommu_rlookup_table
[devid
];
3827 table
= get_irq_table(devid
, false);
3831 spin_lock_irqsave(&table
->lock
, flags
);
3832 table
->table
[index
] = irte
->val
;
3833 spin_unlock_irqrestore(&table
->lock
, flags
);
3835 iommu_flush_irt(iommu
, devid
);
3836 iommu_completion_wait(iommu
);
3841 static void free_irte(u16 devid
, int index
)
3843 struct irq_remap_table
*table
;
3844 struct amd_iommu
*iommu
;
3845 unsigned long flags
;
3847 iommu
= amd_iommu_rlookup_table
[devid
];
3851 table
= get_irq_table(devid
, false);
3855 spin_lock_irqsave(&table
->lock
, flags
);
3856 iommu
->irte_ops
->clear_allocated(table
, index
);
3857 spin_unlock_irqrestore(&table
->lock
, flags
);
3859 iommu_flush_irt(iommu
, devid
);
3860 iommu_completion_wait(iommu
);
3863 static void irte_prepare(void *entry
,
3864 u32 delivery_mode
, u32 dest_mode
,
3865 u8 vector
, u32 dest_apicid
, int devid
)
3867 union irte
*irte
= (union irte
*) entry
;
3870 irte
->fields
.vector
= vector
;
3871 irte
->fields
.int_type
= delivery_mode
;
3872 irte
->fields
.destination
= dest_apicid
;
3873 irte
->fields
.dm
= dest_mode
;
3874 irte
->fields
.valid
= 1;
3877 static void irte_ga_prepare(void *entry
,
3878 u32 delivery_mode
, u32 dest_mode
,
3879 u8 vector
, u32 dest_apicid
, int devid
)
3881 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3882 struct iommu_dev_data
*dev_data
= search_dev_data(devid
);
3886 irte
->lo
.fields_remap
.guest_mode
= dev_data
? dev_data
->use_vapic
: 0;
3887 irte
->lo
.fields_remap
.int_type
= delivery_mode
;
3888 irte
->lo
.fields_remap
.dm
= dest_mode
;
3889 irte
->hi
.fields
.vector
= vector
;
3890 irte
->lo
.fields_remap
.destination
= dest_apicid
;
3891 irte
->lo
.fields_remap
.valid
= 1;
3894 static void irte_activate(void *entry
, u16 devid
, u16 index
)
3896 union irte
*irte
= (union irte
*) entry
;
3898 irte
->fields
.valid
= 1;
3899 modify_irte(devid
, index
, irte
);
3902 static void irte_ga_activate(void *entry
, u16 devid
, u16 index
)
3904 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3906 irte
->lo
.fields_remap
.valid
= 1;
3907 modify_irte_ga(devid
, index
, irte
, NULL
);
3910 static void irte_deactivate(void *entry
, u16 devid
, u16 index
)
3912 union irte
*irte
= (union irte
*) entry
;
3914 irte
->fields
.valid
= 0;
3915 modify_irte(devid
, index
, irte
);
3918 static void irte_ga_deactivate(void *entry
, u16 devid
, u16 index
)
3920 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3922 irte
->lo
.fields_remap
.valid
= 0;
3923 modify_irte_ga(devid
, index
, irte
, NULL
);
3926 static void irte_set_affinity(void *entry
, u16 devid
, u16 index
,
3927 u8 vector
, u32 dest_apicid
)
3929 union irte
*irte
= (union irte
*) entry
;
3931 irte
->fields
.vector
= vector
;
3932 irte
->fields
.destination
= dest_apicid
;
3933 modify_irte(devid
, index
, irte
);
3936 static void irte_ga_set_affinity(void *entry
, u16 devid
, u16 index
,
3937 u8 vector
, u32 dest_apicid
)
3939 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3940 struct iommu_dev_data
*dev_data
= search_dev_data(devid
);
3942 if (!dev_data
|| !dev_data
->use_vapic
) {
3943 irte
->hi
.fields
.vector
= vector
;
3944 irte
->lo
.fields_remap
.destination
= dest_apicid
;
3945 irte
->lo
.fields_remap
.guest_mode
= 0;
3946 modify_irte_ga(devid
, index
, irte
, NULL
);
3950 #define IRTE_ALLOCATED (~1U)
3951 static void irte_set_allocated(struct irq_remap_table
*table
, int index
)
3953 table
->table
[index
] = IRTE_ALLOCATED
;
3956 static void irte_ga_set_allocated(struct irq_remap_table
*table
, int index
)
3958 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3959 struct irte_ga
*irte
= &ptr
[index
];
3961 memset(&irte
->lo
.val
, 0, sizeof(u64
));
3962 memset(&irte
->hi
.val
, 0, sizeof(u64
));
3963 irte
->hi
.fields
.vector
= 0xff;
3966 static bool irte_is_allocated(struct irq_remap_table
*table
, int index
)
3968 union irte
*ptr
= (union irte
*)table
->table
;
3969 union irte
*irte
= &ptr
[index
];
3971 return irte
->val
!= 0;
3974 static bool irte_ga_is_allocated(struct irq_remap_table
*table
, int index
)
3976 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3977 struct irte_ga
*irte
= &ptr
[index
];
3979 return irte
->hi
.fields
.vector
!= 0;
3982 static void irte_clear_allocated(struct irq_remap_table
*table
, int index
)
3984 table
->table
[index
] = 0;
3987 static void irte_ga_clear_allocated(struct irq_remap_table
*table
, int index
)
3989 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3990 struct irte_ga
*irte
= &ptr
[index
];
3992 memset(&irte
->lo
.val
, 0, sizeof(u64
));
3993 memset(&irte
->hi
.val
, 0, sizeof(u64
));
3996 static int get_devid(struct irq_alloc_info
*info
)
4000 switch (info
->type
) {
4001 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4002 devid
= get_ioapic_devid(info
->ioapic_id
);
4004 case X86_IRQ_ALLOC_TYPE_HPET
:
4005 devid
= get_hpet_devid(info
->hpet_id
);
4007 case X86_IRQ_ALLOC_TYPE_MSI
:
4008 case X86_IRQ_ALLOC_TYPE_MSIX
:
4009 devid
= get_device_id(&info
->msi_dev
->dev
);
4019 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
4021 struct amd_iommu
*iommu
;
4027 devid
= get_devid(info
);
4029 iommu
= amd_iommu_rlookup_table
[devid
];
4031 return iommu
->ir_domain
;
4037 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
4039 struct amd_iommu
*iommu
;
4045 switch (info
->type
) {
4046 case X86_IRQ_ALLOC_TYPE_MSI
:
4047 case X86_IRQ_ALLOC_TYPE_MSIX
:
4048 devid
= get_device_id(&info
->msi_dev
->dev
);
4052 iommu
= amd_iommu_rlookup_table
[devid
];
4054 return iommu
->msi_domain
;
4063 struct irq_remap_ops amd_iommu_irq_ops
= {
4064 .prepare
= amd_iommu_prepare
,
4065 .enable
= amd_iommu_enable
,
4066 .disable
= amd_iommu_disable
,
4067 .reenable
= amd_iommu_reenable
,
4068 .enable_faulting
= amd_iommu_enable_faulting
,
4069 .get_ir_irq_domain
= get_ir_irq_domain
,
4070 .get_irq_domain
= get_irq_domain
,
4073 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
4074 struct irq_cfg
*irq_cfg
,
4075 struct irq_alloc_info
*info
,
4076 int devid
, int index
, int sub_handle
)
4078 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4079 struct msi_msg
*msg
= &data
->msi_entry
;
4080 struct IO_APIC_route_entry
*entry
;
4081 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
4086 data
->irq_2_irte
.devid
= devid
;
4087 data
->irq_2_irte
.index
= index
+ sub_handle
;
4088 iommu
->irte_ops
->prepare(data
->entry
, apic
->irq_delivery_mode
,
4089 apic
->irq_dest_mode
, irq_cfg
->vector
,
4090 irq_cfg
->dest_apicid
, devid
);
4092 switch (info
->type
) {
4093 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4094 /* Setup IOAPIC entry */
4095 entry
= info
->ioapic_entry
;
4096 info
->ioapic_entry
= NULL
;
4097 memset(entry
, 0, sizeof(*entry
));
4098 entry
->vector
= index
;
4100 entry
->trigger
= info
->ioapic_trigger
;
4101 entry
->polarity
= info
->ioapic_polarity
;
4102 /* Mask level triggered irqs. */
4103 if (info
->ioapic_trigger
)
4107 case X86_IRQ_ALLOC_TYPE_HPET
:
4108 case X86_IRQ_ALLOC_TYPE_MSI
:
4109 case X86_IRQ_ALLOC_TYPE_MSIX
:
4110 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4111 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4112 msg
->data
= irte_info
->index
;
4121 struct amd_irte_ops irte_32_ops
= {
4122 .prepare
= irte_prepare
,
4123 .activate
= irte_activate
,
4124 .deactivate
= irte_deactivate
,
4125 .set_affinity
= irte_set_affinity
,
4126 .set_allocated
= irte_set_allocated
,
4127 .is_allocated
= irte_is_allocated
,
4128 .clear_allocated
= irte_clear_allocated
,
4131 struct amd_irte_ops irte_128_ops
= {
4132 .prepare
= irte_ga_prepare
,
4133 .activate
= irte_ga_activate
,
4134 .deactivate
= irte_ga_deactivate
,
4135 .set_affinity
= irte_ga_set_affinity
,
4136 .set_allocated
= irte_ga_set_allocated
,
4137 .is_allocated
= irte_ga_is_allocated
,
4138 .clear_allocated
= irte_ga_clear_allocated
,
4141 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4142 unsigned int nr_irqs
, void *arg
)
4144 struct irq_alloc_info
*info
= arg
;
4145 struct irq_data
*irq_data
;
4146 struct amd_ir_data
*data
= NULL
;
4147 struct irq_cfg
*cfg
;
4153 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4154 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4158 * With IRQ remapping enabled, don't need contiguous CPU vectors
4159 * to support multiple MSI interrupts.
4161 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4162 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4164 devid
= get_devid(info
);
4168 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4172 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4173 if (get_irq_table(devid
, true))
4174 index
= info
->ioapic_pin
;
4178 index
= alloc_irq_index(devid
, nr_irqs
);
4181 pr_warn("Failed to allocate IRTE\n");
4183 goto out_free_parent
;
4186 for (i
= 0; i
< nr_irqs
; i
++) {
4187 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4188 cfg
= irqd_cfg(irq_data
);
4189 if (!irq_data
|| !cfg
) {
4195 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4199 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
4200 data
->entry
= kzalloc(sizeof(union irte
), GFP_KERNEL
);
4202 data
->entry
= kzalloc(sizeof(struct irte_ga
),
4209 irq_data
->hwirq
= (devid
<< 16) + i
;
4210 irq_data
->chip_data
= data
;
4211 irq_data
->chip
= &amd_ir_chip
;
4212 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4213 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4219 for (i
--; i
>= 0; i
--) {
4220 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4222 kfree(irq_data
->chip_data
);
4224 for (i
= 0; i
< nr_irqs
; i
++)
4225 free_irte(devid
, index
+ i
);
4227 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4231 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4232 unsigned int nr_irqs
)
4234 struct irq_2_irte
*irte_info
;
4235 struct irq_data
*irq_data
;
4236 struct amd_ir_data
*data
;
4239 for (i
= 0; i
< nr_irqs
; i
++) {
4240 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4241 if (irq_data
&& irq_data
->chip_data
) {
4242 data
= irq_data
->chip_data
;
4243 irte_info
= &data
->irq_2_irte
;
4244 free_irte(irte_info
->devid
, irte_info
->index
);
4249 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4252 static void irq_remapping_activate(struct irq_domain
*domain
,
4253 struct irq_data
*irq_data
)
4255 struct amd_ir_data
*data
= irq_data
->chip_data
;
4256 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4257 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4260 iommu
->irte_ops
->activate(data
->entry
, irte_info
->devid
,
4264 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4265 struct irq_data
*irq_data
)
4267 struct amd_ir_data
*data
= irq_data
->chip_data
;
4268 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4269 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4272 iommu
->irte_ops
->deactivate(data
->entry
, irte_info
->devid
,
4276 static struct irq_domain_ops amd_ir_domain_ops
= {
4277 .alloc
= irq_remapping_alloc
,
4278 .free
= irq_remapping_free
,
4279 .activate
= irq_remapping_activate
,
4280 .deactivate
= irq_remapping_deactivate
,
4283 static int amd_ir_set_vcpu_affinity(struct irq_data
*data
, void *vcpu_info
)
4285 struct amd_iommu
*iommu
;
4286 struct amd_iommu_pi_data
*pi_data
= vcpu_info
;
4287 struct vcpu_data
*vcpu_pi_info
= pi_data
->vcpu_data
;
4288 struct amd_ir_data
*ir_data
= data
->chip_data
;
4289 struct irte_ga
*irte
= (struct irte_ga
*) ir_data
->entry
;
4290 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4291 struct iommu_dev_data
*dev_data
= search_dev_data(irte_info
->devid
);
4294 * This device has never been set up for guest mode.
4295 * we should not modify the IRTE
4297 if (!dev_data
|| !dev_data
->use_vapic
)
4300 pi_data
->ir_data
= ir_data
;
4303 * SVM tries to set up for VAPIC mode, but we are in
4304 * legacy mode. So, we force legacy mode instead.
4306 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
4307 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4309 pi_data
->is_guest_mode
= false;
4312 iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4316 pi_data
->prev_ga_tag
= ir_data
->cached_ga_tag
;
4317 if (pi_data
->is_guest_mode
) {
4319 irte
->hi
.fields
.ga_root_ptr
= (pi_data
->base
>> 12);
4320 irte
->hi
.fields
.vector
= vcpu_pi_info
->vector
;
4321 irte
->lo
.fields_vapic
.guest_mode
= 1;
4322 irte
->lo
.fields_vapic
.ga_tag
= pi_data
->ga_tag
;
4324 ir_data
->cached_ga_tag
= pi_data
->ga_tag
;
4327 struct irq_cfg
*cfg
= irqd_cfg(data
);
4331 irte
->hi
.fields
.vector
= cfg
->vector
;
4332 irte
->lo
.fields_remap
.guest_mode
= 0;
4333 irte
->lo
.fields_remap
.destination
= cfg
->dest_apicid
;
4334 irte
->lo
.fields_remap
.int_type
= apic
->irq_delivery_mode
;
4335 irte
->lo
.fields_remap
.dm
= apic
->irq_dest_mode
;
4338 * This communicates the ga_tag back to the caller
4339 * so that it can do all the necessary clean up.
4341 ir_data
->cached_ga_tag
= 0;
4344 return modify_irte_ga(irte_info
->devid
, irte_info
->index
, irte
, ir_data
);
4347 static int amd_ir_set_affinity(struct irq_data
*data
,
4348 const struct cpumask
*mask
, bool force
)
4350 struct amd_ir_data
*ir_data
= data
->chip_data
;
4351 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4352 struct irq_cfg
*cfg
= irqd_cfg(data
);
4353 struct irq_data
*parent
= data
->parent_data
;
4354 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4360 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4361 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4365 * Atomically updates the IRTE with the new destination, vector
4366 * and flushes the interrupt entry cache.
4368 iommu
->irte_ops
->set_affinity(ir_data
->entry
, irte_info
->devid
,
4369 irte_info
->index
, cfg
->vector
, cfg
->dest_apicid
);
4372 * After this point, all the interrupts will start arriving
4373 * at the new destination. So, time to cleanup the previous
4374 * vector allocation.
4376 send_cleanup_vector(cfg
);
4378 return IRQ_SET_MASK_OK_DONE
;
4381 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4383 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4385 *msg
= ir_data
->msi_entry
;
4388 static struct irq_chip amd_ir_chip
= {
4389 .irq_ack
= ir_ack_apic_edge
,
4390 .irq_set_affinity
= amd_ir_set_affinity
,
4391 .irq_set_vcpu_affinity
= amd_ir_set_vcpu_affinity
,
4392 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4395 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4397 iommu
->ir_domain
= irq_domain_add_tree(NULL
, &amd_ir_domain_ops
, iommu
);
4398 if (!iommu
->ir_domain
)
4401 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4402 iommu
->msi_domain
= arch_create_msi_irq_domain(iommu
->ir_domain
);
4407 int amd_iommu_update_ga(int cpu
, bool is_run
, void *data
)
4409 unsigned long flags
;
4410 struct amd_iommu
*iommu
;
4411 struct irq_remap_table
*irt
;
4412 struct amd_ir_data
*ir_data
= (struct amd_ir_data
*)data
;
4413 int devid
= ir_data
->irq_2_irte
.devid
;
4414 struct irte_ga
*entry
= (struct irte_ga
*) ir_data
->entry
;
4415 struct irte_ga
*ref
= (struct irte_ga
*) ir_data
->ref
;
4417 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) ||
4418 !ref
|| !entry
|| !entry
->lo
.fields_vapic
.guest_mode
)
4421 iommu
= amd_iommu_rlookup_table
[devid
];
4425 irt
= get_irq_table(devid
, false);
4429 spin_lock_irqsave(&irt
->lock
, flags
);
4431 if (ref
->lo
.fields_vapic
.guest_mode
) {
4433 ref
->lo
.fields_vapic
.destination
= cpu
;
4434 ref
->lo
.fields_vapic
.is_run
= is_run
;
4438 spin_unlock_irqrestore(&irt
->lock
, flags
);
4440 iommu_flush_irt(iommu
, devid
);
4441 iommu_completion_wait(iommu
);
4444 EXPORT_SYMBOL(amd_iommu_update_ga
);