arch/arm/mach-ux500/devices-db8500.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/gpio.h>
  13 #include <linux/amba/bus.h>
  14 #include <linux/amba/pl022.h>
  15
  16 #include <plat/ste_dma40.h>
  17
  18 #include <mach/hardware.h>
  19 #include <mach/setup.h>
  20
  21 #include "ste-dma40-db8500.h"
  22
  23 static struct resource dma40_resources[] = {
  24         [0] = {
  25                 .start = U8500_DMA_BASE,
  26                 .end   = U8500_DMA_BASE + SZ_4K - 1,
  27                 .flags = IORESOURCE_MEM,
  28                 .name  = "base",
  29         },
  30         [1] = {
  31                 .start = U8500_DMA_LCPA_BASE,
  32                 .end   = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
  33                 .flags = IORESOURCE_MEM,
  34                 .name  = "lcpa",
  35         },
  36         [2] = {
  37                 .start = IRQ_DB8500_DMA,
  38                 .end   = IRQ_DB8500_DMA,
  39                 .flags = IORESOURCE_IRQ,
  40         }
  41 };
  42
  43 /* Default configuration for physcial memcpy */
  44 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  45         .mode = STEDMA40_MODE_PHYSICAL,
  46         .dir = STEDMA40_MEM_TO_MEM,
  47
  48         .src_info.data_width = STEDMA40_BYTE_WIDTH,
  49         .src_info.psize = STEDMA40_PSIZE_PHY_1,
  50         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  51
  52         .dst_info.data_width = STEDMA40_BYTE_WIDTH,
  53         .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  54         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  55 };
  56 /* Default configuration for logical memcpy */
  57 struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  58         .dir = STEDMA40_MEM_TO_MEM,
  59
  60         .src_info.data_width = STEDMA40_BYTE_WIDTH,
  61         .src_info.psize = STEDMA40_PSIZE_LOG_1,
  62         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  63
  64         .dst_info.data_width = STEDMA40_BYTE_WIDTH,
  65         .dst_info.psize = STEDMA40_PSIZE_LOG_1,
  66         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  67 };
  68
  69 /*
  70  * Mapping between destination event lines and physical device address.
  71  * The event line is tied to a device and therefore the address is constant.
  72  * When the address comes from a primecell it will be configured in runtime
  73  * and we set the address to -1 as a placeholder.
  74  */
  75 static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
  76         /* MUSB - these will be runtime-reconfigured */
  77         [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
  78         [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
  79         [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
  80         [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
  81         [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
  82         [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
  83         [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
  84         [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
  85         /* PrimeCells - run-time configured */
  86         [DB8500_DMA_DEV0_SPI0_TX] = -1,
  87         [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
  88         [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
  89         [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
  90         [DB8500_DMA_DEV8_SSP0_TX] = -1,
  91         [DB8500_DMA_DEV9_SSP1_TX] = -1,
  92         [DB8500_DMA_DEV11_UART2_TX] = -1,
  93         [DB8500_DMA_DEV12_UART1_TX] = -1,
  94         [DB8500_DMA_DEV13_UART0_TX] = -1,
  95         [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
  96         [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
  97         [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
  98         [DB8500_DMA_DEV33_SPI2_TX] = -1,
  99         [DB8500_DMA_DEV35_SPI1_TX] = -1,
 100         [DB8500_DMA_DEV40_SPI3_TX] = -1,
 101         [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
 102         [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
 103         [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
 104         [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
 105         [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
 106         [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 107 };
 108
 109 /* Mapping between source event lines and physical device address */
 110 static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 111         /* MUSB - these will be runtime-reconfigured */
 112         [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
 113         [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
 114         [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
 115         [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
 116         [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
 117         [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
 118         [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
 119         [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
 120         /* PrimeCells */
 121         [DB8500_DMA_DEV0_SPI0_RX] = -1,
 122         [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
 123         [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
 124         [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
 125         [DB8500_DMA_DEV8_SSP0_RX] = -1,
 126         [DB8500_DMA_DEV9_SSP1_RX] = -1,
 127         [DB8500_DMA_DEV11_UART2_RX] = -1,
 128         [DB8500_DMA_DEV12_UART1_RX] = -1,
 129         [DB8500_DMA_DEV13_UART0_RX] = -1,
 130         [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
 131         [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
 132         [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
 133         [DB8500_DMA_DEV33_SPI2_RX] = -1,
 134         [DB8500_DMA_DEV35_SPI1_RX] = -1,
 135         [DB8500_DMA_DEV40_SPI3_RX] = -1,
 136         [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
 137         [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
 138         [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
 139         [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
 140         [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
 141         [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 142 };
 143
 144 /* Reserved event lines for memcpy only */
 145 static int dma40_memcpy_event[] = {
 146         DB8500_DMA_MEMCPY_TX_0,
 147         DB8500_DMA_MEMCPY_TX_1,
 148         DB8500_DMA_MEMCPY_TX_2,
 149         DB8500_DMA_MEMCPY_TX_3,
 150         DB8500_DMA_MEMCPY_TX_4,
 151         DB8500_DMA_MEMCPY_TX_5,
 152 };
 153
 154 static struct stedma40_platform_data dma40_plat_data = {
 155         .dev_len = DB8500_DMA_NR_DEV,
 156         .dev_rx = dma40_rx_map,
 157         .dev_tx = dma40_tx_map,
 158         .memcpy = dma40_memcpy_event,
 159         .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
 160         .memcpy_conf_phy = &dma40_memcpy_conf_phy,
 161         .memcpy_conf_log = &dma40_memcpy_conf_log,
 162         .disabled_channels = {-1},
 163 };
 164
 165 struct platform_device u8500_dma40_device = {
 166         .dev = {
 167                 .platform_data = &dma40_plat_data,
 168         },
 169         .name = "dma40",
 170         .id = 0,
 171         .num_resources = ARRAY_SIZE(dma40_resources),
 172         .resource = dma40_resources
 173 };
 174
 175 struct resource keypad_resources[] = {
 176         [0] = {
 177                 .start = U8500_SKE_BASE,
 178                 .end = U8500_SKE_BASE + SZ_4K - 1,
 179                 .flags = IORESOURCE_MEM,
 180         },
 181         [1] = {
 182                 .start = IRQ_DB8500_KB,
 183                 .end = IRQ_DB8500_KB,
 184                 .flags = IORESOURCE_IRQ,
 185         },
 186 };
 187
 188 struct platform_device u8500_ske_keypad_device = {
 189         .name = "nmk-ske-keypad",
 190         .id = -1,
 191         .num_resources = ARRAY_SIZE(keypad_resources),
 192         .resource = keypad_resources,
 193 };