arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2011 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/list.h>
  21
  22 #include <linux/clkdev.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/clk/ti.h>
  25
  26 /* struct clksel_rate.flags possibilities */
  27 #define RATE_IN_242X            (1 << 0)
  28 #define RATE_IN_243X            (1 << 1)
  29 #define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
  30 #define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
  31 #define RATE_IN_36XX            (1 << 4)
  32 #define RATE_IN_4430            (1 << 5)
  33 #define RATE_IN_TI816X          (1 << 6)
  34 #define RATE_IN_4460            (1 << 7)
  35 #define RATE_IN_AM33XX          (1 << 8)
  36 #define RATE_IN_TI814X          (1 << 9)
  37
  38 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
  39 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
  40 #define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
  41 #define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
  42
  43 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
  44 #define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
  45
  46 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
  47 #define CORE_CLK_SRC_32K                0x0
  48 #define CORE_CLK_SRC_DPLL               0x1
  49 #define CORE_CLK_SRC_DPLL_X2            0x2
  50
  51 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
  52 #define OMAP2XXX_EN_DPLL_LPBYPASS               0x1
  53 #define OMAP2XXX_EN_DPLL_FRBYPASS               0x2
  54 #define OMAP2XXX_EN_DPLL_LOCKED                 0x3
  55
  56 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
  57 #define OMAP3XXX_EN_DPLL_LPBYPASS               0x5
  58 #define OMAP3XXX_EN_DPLL_FRBYPASS               0x6
  59 #define OMAP3XXX_EN_DPLL_LOCKED                 0x7
  60
  61 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
  62 #define OMAP4XXX_EN_DPLL_MNBYPASS               0x4
  63 #define OMAP4XXX_EN_DPLL_LPBYPASS               0x5
  64 #define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
  65 #define OMAP4XXX_EN_DPLL_LOCKED                 0x7
  66
  67 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
  68                                const char *core_ck_name,
  69                                const char *mpu_ck_name);
  70
  71 extern u16 cpu_mask;
  72
  73 extern const struct clkops clkops_omap2_dflt_wait;
  74 extern const struct clkops clkops_omap2_dflt;
  75
  76 extern struct clk_functions omap2_clk_functions;
  77
  78 int __init omap2_clk_setup_ll_ops(void);
  79
  80 void __init ti_clk_init_features(void);
  81 #endif