x86: Make the vdso2c compiler use the host architecture headers
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap-smp.c
blob8cd1de914ee492beaaae1934a9ff910f3208c1f3
1 /*
2 * OMAP4 SMP source file. It contains platform specific functions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
21 #include <linux/io.h>
22 #include <linux/irqchip/arm-gic.h>
24 #include <asm/smp_scu.h>
25 #include <asm/virt.h>
27 #include "omap-secure.h"
28 #include "omap-wakeupgen.h"
29 #include <asm/cputype.h>
31 #include "soc.h"
32 #include "iomap.h"
33 #include "common.h"
34 #include "clockdomain.h"
35 #include "pm.h"
37 #define CPU_MASK 0xff0ffff0
38 #define CPU_CORTEX_A9 0x410FC090
39 #define CPU_CORTEX_A15 0x410FC0F0
41 #define OMAP5_CORE_COUNT 0x2
43 /* SCU base address */
44 static void __iomem *scu_base;
46 static DEFINE_SPINLOCK(boot_lock);
48 void __iomem *omap4_get_scu_base(void)
50 return scu_base;
53 #ifdef CONFIG_OMAP5_ERRATA_801819
54 void omap5_erratum_workaround_801819(void)
56 u32 acr, revidr;
57 u32 acr_mask;
59 /* REVIDR[3] indicates erratum fix available on silicon */
60 asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
61 if (revidr & (0x1 << 3))
62 return;
64 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
66 * BIT(27) - Disables streaming. All write-allocate lines allocate in
67 * the L1 or L2 cache.
68 * BIT(25) - Disables streaming. All write-allocate lines allocate in
69 * the L1 cache.
71 acr_mask = (0x3 << 25) | (0x3 << 27);
72 /* do we already have it done.. if yes, skip expensive smc */
73 if ((acr & acr_mask) == acr_mask)
74 return;
76 acr |= acr_mask;
77 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
79 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
80 __func__, smp_processor_id());
82 #else
83 static inline void omap5_erratum_workaround_801819(void) { }
84 #endif
86 static void omap4_secondary_init(unsigned int cpu)
89 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
90 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
91 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
92 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
93 * OMAP443X GP devices- SMP bit isn't accessible.
94 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
96 if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
97 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
98 4, 0, 0, 0, 0, 0);
100 if (soc_is_omap54xx() || soc_is_dra7xx()) {
102 * Configure the CNTFRQ register for the secondary cpu's which
103 * indicates the frequency of the cpu local timers.
105 set_cntfreq();
106 /* Configure ACR to disable streaming WA for 801819 */
107 omap5_erratum_workaround_801819();
111 * Synchronise with the boot thread.
113 spin_lock(&boot_lock);
114 spin_unlock(&boot_lock);
117 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
119 static struct clockdomain *cpu1_clkdm;
120 static bool booted;
121 static struct powerdomain *cpu1_pwrdm;
122 void __iomem *base = omap_get_wakeupgen_base();
125 * Set synchronisation state between this boot processor
126 * and the secondary one
128 spin_lock(&boot_lock);
131 * Update the AuxCoreBoot0 with boot state for secondary core.
132 * omap4_secondary_startup() routine will hold the secondary core till
133 * the AuxCoreBoot1 register is updated with cpu state
134 * A barrier is added to ensure that write buffer is drained
136 if (omap_secure_apis_support())
137 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
138 else
139 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
141 if (!cpu1_clkdm && !cpu1_pwrdm) {
142 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
143 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
147 * The SGI(Software Generated Interrupts) are not wakeup capable
148 * from low power states. This is known limitation on OMAP4 and
149 * needs to be worked around by using software forced clockdomain
150 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
151 * software force wakeup. The clockdomain is then put back to
152 * hardware supervised mode.
153 * More details can be found in OMAP4430 TRM - Version J
154 * Section :
155 * 4.3.4.2 Power States of CPU0 and CPU1
157 if (booted && cpu1_pwrdm && cpu1_clkdm) {
159 * GIC distributor control register has changed between
160 * CortexA9 r1pX and r2pX. The Control Register secure
161 * banked version is now composed of 2 bits:
162 * bit 0 == Secure Enable
163 * bit 1 == Non-Secure Enable
164 * The Non-Secure banked register has not changed
165 * Because the ROM Code is based on the r1pX GIC, the CPU1
166 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
167 * The workaround must be:
168 * 1) Before doing the CPU1 wakeup, CPU0 must disable
169 * the GIC distributor
170 * 2) CPU1 must re-enable the GIC distributor on
171 * it's wakeup path.
173 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
174 local_irq_disable();
175 gic_dist_disable();
179 * Ensure that CPU power state is set to ON to avoid CPU
180 * powerdomain transition on wfi
182 clkdm_wakeup_nolock(cpu1_clkdm);
183 pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
184 clkdm_allow_idle_nolock(cpu1_clkdm);
186 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
187 while (gic_dist_disabled()) {
188 udelay(1);
189 cpu_relax();
191 gic_timer_retrigger();
192 local_irq_enable();
194 } else {
195 dsb_sev();
196 booted = true;
199 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
202 * Now the secondary core is starting up let it run its
203 * calibrations, then wait for it to finish
205 spin_unlock(&boot_lock);
207 return 0;
211 * Initialise the CPU possible map early - this describes the CPUs
212 * which may be present or become present in the system.
214 static void __init omap4_smp_init_cpus(void)
216 unsigned int i = 0, ncores = 1, cpu_id;
218 /* Use ARM cpuid check here, as SoC detection will not work so early */
219 cpu_id = read_cpuid_id() & CPU_MASK;
220 if (cpu_id == CPU_CORTEX_A9) {
222 * Currently we can't call ioremap here because
223 * SoC detection won't work until after init_early.
225 scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
226 BUG_ON(!scu_base);
227 ncores = scu_get_core_count(scu_base);
228 } else if (cpu_id == CPU_CORTEX_A15) {
229 ncores = OMAP5_CORE_COUNT;
232 /* sanity check */
233 if (ncores > nr_cpu_ids) {
234 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
235 ncores, nr_cpu_ids);
236 ncores = nr_cpu_ids;
239 for (i = 0; i < ncores; i++)
240 set_cpu_possible(i, true);
243 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
245 void *startup_addr = omap4_secondary_startup;
246 void __iomem *base = omap_get_wakeupgen_base();
249 * Initialise the SCU and wake up the secondary core using
250 * wakeup_secondary().
252 if (scu_base)
253 scu_enable(scu_base);
255 if (cpu_is_omap446x())
256 startup_addr = omap4460_secondary_startup;
257 if (soc_is_dra74x() || soc_is_omap54xx())
258 omap5_erratum_workaround_801819();
261 * Write the address of secondary startup routine into the
262 * AuxCoreBoot1 where ROM code will jump and start executing
263 * on secondary core once out of WFE
264 * A barrier is added to ensure that write buffer is drained
266 if (omap_secure_apis_support())
267 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
268 else
270 * If the boot CPU is in HYP mode then start secondary
271 * CPU in HYP mode as well.
273 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
274 writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
275 base + OMAP_AUX_CORE_BOOT_1);
276 else
277 writel_relaxed(virt_to_phys(omap5_secondary_startup),
278 base + OMAP_AUX_CORE_BOOT_1);
282 const struct smp_operations omap4_smp_ops __initconst = {
283 .smp_init_cpus = omap4_smp_init_cpus,
284 .smp_prepare_cpus = omap4_smp_prepare_cpus,
285 .smp_secondary_init = omap4_secondary_init,
286 .smp_boot_secondary = omap4_boot_secondary,
287 #ifdef CONFIG_HOTPLUG_CPU
288 .cpu_die = omap4_cpu_die,
289 #endif