arch/arm/mach-omap2/prcm_mpu54xx.h

   1 /*
   2  * OMAP54xx PRCM MPU instance offset macros
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley (paul@pwsan.com)
   7  * Rajendra Nayak (rnayak@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
  22 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
  23
  24 #include "prcm_mpu_44xx_54xx.h"
  25 #include "common.h"
  26
  27 #define OMAP54XX_PRCM_MPU_BASE                  0x48243000
  28
  29 #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)                            \
  30         OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
  31
  32 /* PRCM_MPU instances */
  33 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST       0x0000
  34 #define OMAP54XX_PRCM_MPU_DEVICE_INST           0x0200
  35 #define OMAP54XX_PRCM_MPU_PRM_C0_INST           0x0400
  36 #define OMAP54XX_PRCM_MPU_CM_C0_INST            0x0600
  37 #define OMAP54XX_PRCM_MPU_PRM_C1_INST           0x0800
  38 #define OMAP54XX_PRCM_MPU_CM_C1_INST            0x0a00
  39
  40 /* PRCM_MPU clockdomain register offsets (from instance start) */
  41 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS     0x0000
  42 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS     0x0000
  43
  44
  45 /*
  46  * PRCM_MPU
  47  *
  48  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
  49  * point of view the PRCM_MPU is a single entity. It shares the same
  50  * programming model as the global PRCM and thus can be assimilate as two new
  51  * MOD inside the PRCM
  52  */
  53
  54 /* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
  55 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET                       0x0000
  56
  57 /* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
  58 #define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET                      0x0000
  59 #define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET                0x0004
  60 #define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET          0x0010
  61 #define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
  62
  63 /* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
  64 #define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET                       0x0000
  65 #define OMAP54XX_PM_CPU0_PWRSTST_OFFSET                         0x0004
  66 #define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                    0x0010
  67 #define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET                      0x0014
  68 #define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET                    0x0024
  69
  70 /* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
  71 #define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET                       0x0000
  72 #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                    0x0020
  73 #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
  74
  75 /* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
  76 #define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET                       0x0000
  77 #define OMAP54XX_PM_CPU1_PWRSTST_OFFSET                         0x0004
  78 #define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                    0x0010
  79 #define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET                      0x0014
  80 #define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET                    0x0024
  81
  82 /* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
  83 #define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET                       0x0000
  84 #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                    0x0020
  85 #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
  86
  87 #endif