2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/interrupt.h>
31 #include <linux/wait.h>
32 #include <linux/clk.h>
33 #include <linux/cpufreq.h>
34 #include <linux/console.h>
35 #include <linux/spinlock.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/lcm.h>
39 #include <video/da8xx-fb.h>
40 #include <asm/div64.h>
42 #define DRIVER_NAME "da8xx_lcdc"
44 #define LCD_VERSION_1 1
45 #define LCD_VERSION_2 2
47 /* LCD Status Register */
48 #define LCD_END_OF_FRAME1 BIT(9)
49 #define LCD_END_OF_FRAME0 BIT(8)
50 #define LCD_PL_LOAD_DONE BIT(6)
51 #define LCD_FIFO_UNDERFLOW BIT(5)
52 #define LCD_SYNC_LOST BIT(2)
53 #define LCD_FRAME_DONE BIT(0)
55 /* LCD DMA Control Register */
56 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
57 #define LCD_DMA_BURST_1 0x0
58 #define LCD_DMA_BURST_2 0x1
59 #define LCD_DMA_BURST_4 0x2
60 #define LCD_DMA_BURST_8 0x3
61 #define LCD_DMA_BURST_16 0x4
62 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
63 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
64 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
65 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
67 /* LCD Control Register */
68 #define LCD_CLK_DIVISOR(x) ((x) << 8)
69 #define LCD_RASTER_MODE 0x01
71 /* LCD Raster Control Register */
72 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
73 #define PALETTE_AND_DATA 0x00
74 #define PALETTE_ONLY 0x01
75 #define DATA_ONLY 0x02
77 #define LCD_MONO_8BIT_MODE BIT(9)
78 #define LCD_RASTER_ORDER BIT(8)
79 #define LCD_TFT_MODE BIT(7)
80 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
81 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
82 #define LCD_V1_PL_INT_ENA BIT(4)
83 #define LCD_V2_PL_INT_ENA BIT(6)
84 #define LCD_MONOCHROME_MODE BIT(1)
85 #define LCD_RASTER_ENABLE BIT(0)
86 #define LCD_TFT_ALT_ENABLE BIT(23)
87 #define LCD_STN_565_ENABLE BIT(24)
88 #define LCD_V2_DMA_CLK_EN BIT(2)
89 #define LCD_V2_LIDD_CLK_EN BIT(1)
90 #define LCD_V2_CORE_CLK_EN BIT(0)
91 #define LCD_V2_LPP_B10 26
92 #define LCD_V2_TFT_24BPP_MODE BIT(25)
93 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
95 /* LCD Raster Timing 2 Register */
96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
97 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
98 #define LCD_SYNC_CTRL BIT(25)
99 #define LCD_SYNC_EDGE BIT(24)
100 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
101 #define LCD_INVERT_LINE_CLOCK BIT(21)
102 #define LCD_INVERT_FRAME_CLOCK BIT(20)
105 #define LCD_PID_REG 0x0
106 #define LCD_CTRL_REG 0x4
107 #define LCD_STAT_REG 0x8
108 #define LCD_RASTER_CTRL_REG 0x28
109 #define LCD_RASTER_TIMING_0_REG 0x2C
110 #define LCD_RASTER_TIMING_1_REG 0x30
111 #define LCD_RASTER_TIMING_2_REG 0x34
112 #define LCD_DMA_CTRL_REG 0x40
113 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
114 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
115 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
116 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
118 /* Interrupt Registers available only in Version 2 */
119 #define LCD_RAW_STAT_REG 0x58
120 #define LCD_MASKED_STAT_REG 0x5c
121 #define LCD_INT_ENABLE_SET_REG 0x60
122 #define LCD_INT_ENABLE_CLR_REG 0x64
123 #define LCD_END_OF_INT_IND_REG 0x68
125 /* Clock registers available only on Version 2 */
126 #define LCD_CLK_ENABLE_REG 0x6c
127 #define LCD_CLK_RESET_REG 0x70
128 #define LCD_CLK_MAIN_RESET BIT(3)
130 #define LCD_NUM_BUFFERS 2
132 #define WSI_TIMEOUT 50
133 #define PALETTE_SIZE 256
134 #define LEFT_MARGIN 64
135 #define RIGHT_MARGIN 64
136 #define UPPER_MARGIN 32
137 #define LOWER_MARGIN 32
139 static void __iomem
*da8xx_fb_reg_base
;
140 static struct resource
*lcdc_regs
;
141 static unsigned int lcd_revision
;
142 static irq_handler_t lcdc_irq_handler
;
143 static wait_queue_head_t frame_done_wq
;
144 static int frame_done_flag
;
146 static inline unsigned int lcdc_read(unsigned int addr
)
148 return (unsigned int)__raw_readl(da8xx_fb_reg_base
+ (addr
));
151 static inline void lcdc_write(unsigned int val
, unsigned int addr
)
153 __raw_writel(val
, da8xx_fb_reg_base
+ (addr
));
156 struct da8xx_fb_par
{
157 resource_size_t p_palette_base
;
158 unsigned char *v_palette_base
;
159 dma_addr_t vram_phys
;
160 unsigned long vram_size
;
162 unsigned int dma_start
;
163 unsigned int dma_end
;
164 struct clk
*lcdc_clk
;
166 unsigned int palette_sz
;
167 unsigned int pxl_clk
;
169 wait_queue_head_t vsync_wait
;
172 spinlock_t lock_for_chan_update
;
175 * LCDC has 2 ping pong DMA channels, channel 0
178 unsigned int which_dma_channel_done
;
179 #ifdef CONFIG_CPU_FREQ
180 struct notifier_block freq_transition
;
181 unsigned int lcd_fck_rate
;
183 void (*panel_power_ctrl
)(int);
184 u32 pseudo_palette
[16];
187 /* Variable Screen Information */
188 static struct fb_var_screeninfo da8xx_fb_var
= {
197 .left_margin
= LEFT_MARGIN
,
198 .right_margin
= RIGHT_MARGIN
,
199 .upper_margin
= UPPER_MARGIN
,
200 .lower_margin
= LOWER_MARGIN
,
202 .vmode
= FB_VMODE_NONINTERLACED
205 static struct fb_fix_screeninfo da8xx_fb_fix
= {
206 .id
= "DA8xx FB Drv",
207 .type
= FB_TYPE_PACKED_PIXELS
,
209 .visual
= FB_VISUAL_PSEUDOCOLOR
,
213 .accel
= FB_ACCEL_NONE
216 static struct fb_videomode known_lcd_panels
[] = {
217 /* Sharp LCD035Q3DG01 */
219 .name
= "Sharp_LCD035Q3DG01",
229 .sync
= FB_SYNC_CLK_INVERT
|
230 FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
232 /* Sharp LK043T1DG01 */
234 .name
= "Sharp_LK043T1DG01",
244 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
248 /* Hitachi SP10Q010 */
259 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
264 /* Enable the Raster Engine of the LCD Controller */
265 static inline void lcd_enable_raster(void)
269 /* Put LCDC in reset for several cycles */
270 if (lcd_revision
== LCD_VERSION_2
)
271 /* Write 1 to reset LCDC */
272 lcdc_write(LCD_CLK_MAIN_RESET
, LCD_CLK_RESET_REG
);
275 /* Bring LCDC out of reset */
276 if (lcd_revision
== LCD_VERSION_2
)
277 lcdc_write(0, LCD_CLK_RESET_REG
);
280 /* Above reset sequence doesnot reset register context */
281 reg
= lcdc_read(LCD_RASTER_CTRL_REG
);
282 if (!(reg
& LCD_RASTER_ENABLE
))
283 lcdc_write(reg
| LCD_RASTER_ENABLE
, LCD_RASTER_CTRL_REG
);
286 /* Disable the Raster Engine of the LCD Controller */
287 static inline void lcd_disable_raster(bool wait_for_frame_done
)
292 reg
= lcdc_read(LCD_RASTER_CTRL_REG
);
293 if (reg
& LCD_RASTER_ENABLE
)
294 lcdc_write(reg
& ~LCD_RASTER_ENABLE
, LCD_RASTER_CTRL_REG
);
296 /* return if already disabled */
299 if ((wait_for_frame_done
== true) && (lcd_revision
== LCD_VERSION_2
)) {
301 ret
= wait_event_interruptible_timeout(frame_done_wq
,
302 frame_done_flag
!= 0,
303 msecs_to_jiffies(50));
305 pr_err("LCD Controller timed out\n");
309 static void lcd_blit(int load_mode
, struct da8xx_fb_par
*par
)
317 /* init reg to clear PLM (loading mode) fields */
318 reg_ras
= lcdc_read(LCD_RASTER_CTRL_REG
);
319 reg_ras
&= ~(3 << 20);
321 reg_dma
= lcdc_read(LCD_DMA_CTRL_REG
);
323 if (load_mode
== LOAD_DATA
) {
324 start
= par
->dma_start
;
327 reg_ras
|= LCD_PALETTE_LOAD_MODE(DATA_ONLY
);
328 if (lcd_revision
== LCD_VERSION_1
) {
329 reg_dma
|= LCD_V1_END_OF_FRAME_INT_ENA
;
331 reg_int
= lcdc_read(LCD_INT_ENABLE_SET_REG
) |
332 LCD_V2_END_OF_FRAME0_INT_ENA
|
333 LCD_V2_END_OF_FRAME1_INT_ENA
|
335 lcdc_write(reg_int
, LCD_INT_ENABLE_SET_REG
);
337 reg_dma
|= LCD_DUAL_FRAME_BUFFER_ENABLE
;
339 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
340 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
341 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
342 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
343 } else if (load_mode
== LOAD_PALETTE
) {
344 start
= par
->p_palette_base
;
345 end
= start
+ par
->palette_sz
- 1;
347 reg_ras
|= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY
);
349 if (lcd_revision
== LCD_VERSION_1
) {
350 reg_ras
|= LCD_V1_PL_INT_ENA
;
352 reg_int
= lcdc_read(LCD_INT_ENABLE_SET_REG
) |
354 lcdc_write(reg_int
, LCD_INT_ENABLE_SET_REG
);
357 lcdc_write(start
, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
358 lcdc_write(end
, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
361 lcdc_write(reg_dma
, LCD_DMA_CTRL_REG
);
362 lcdc_write(reg_ras
, LCD_RASTER_CTRL_REG
);
365 * The Raster enable bit must be set after all other control fields are
371 /* Configure the Burst Size and fifo threhold of DMA */
372 static int lcd_cfg_dma(int burst_size
, int fifo_th
)
376 reg
= lcdc_read(LCD_DMA_CTRL_REG
) & 0x00000001;
377 switch (burst_size
) {
379 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1
);
382 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2
);
385 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4
);
388 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8
);
392 reg
|= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16
);
396 reg
|= (fifo_th
<< 8);
398 lcdc_write(reg
, LCD_DMA_CTRL_REG
);
403 static void lcd_cfg_ac_bias(int period
, int transitions_per_int
)
407 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
408 reg
= lcdc_read(LCD_RASTER_TIMING_2_REG
) & 0xFFF00000;
409 reg
|= LCD_AC_BIAS_FREQUENCY(period
) |
410 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int
);
411 lcdc_write(reg
, LCD_RASTER_TIMING_2_REG
);
414 static void lcd_cfg_horizontal_sync(int back_porch
, int pulse_width
,
419 reg
= lcdc_read(LCD_RASTER_TIMING_0_REG
) & 0xf;
420 reg
|= ((back_porch
& 0xff) << 24)
421 | ((front_porch
& 0xff) << 16)
422 | ((pulse_width
& 0x3f) << 10);
423 lcdc_write(reg
, LCD_RASTER_TIMING_0_REG
);
426 static void lcd_cfg_vertical_sync(int back_porch
, int pulse_width
,
431 reg
= lcdc_read(LCD_RASTER_TIMING_1_REG
) & 0x3ff;
432 reg
|= ((back_porch
& 0xff) << 24)
433 | ((front_porch
& 0xff) << 16)
434 | ((pulse_width
& 0x3f) << 10);
435 lcdc_write(reg
, LCD_RASTER_TIMING_1_REG
);
438 static int lcd_cfg_display(const struct lcd_ctrl_config
*cfg
,
439 struct fb_videomode
*panel
)
444 reg
= lcdc_read(LCD_RASTER_CTRL_REG
) & ~(LCD_TFT_MODE
|
446 LCD_MONOCHROME_MODE
);
448 switch (cfg
->panel_shade
) {
450 reg
|= LCD_MONOCHROME_MODE
;
451 if (cfg
->mono_8bit_mode
)
452 reg
|= LCD_MONO_8BIT_MODE
;
456 if (cfg
->tft_alt_mode
)
457 reg
|= LCD_TFT_ALT_ENABLE
;
461 /* AC bias applicable only for Pasive panels */
462 lcd_cfg_ac_bias(cfg
->ac_bias
, cfg
->ac_bias_intrpt
);
463 if (cfg
->bpp
== 12 && cfg
->stn_565_mode
)
464 reg
|= LCD_STN_565_ENABLE
;
471 /* enable additional interrupts here */
472 if (lcd_revision
== LCD_VERSION_1
) {
473 reg
|= LCD_V1_UNDERFLOW_INT_ENA
;
475 reg_int
= lcdc_read(LCD_INT_ENABLE_SET_REG
) |
476 LCD_V2_UNDERFLOW_INT_ENA
;
477 lcdc_write(reg_int
, LCD_INT_ENABLE_SET_REG
);
480 lcdc_write(reg
, LCD_RASTER_CTRL_REG
);
482 reg
= lcdc_read(LCD_RASTER_TIMING_2_REG
);
484 reg
|= LCD_SYNC_CTRL
;
487 reg
|= LCD_SYNC_EDGE
;
489 reg
&= ~LCD_SYNC_EDGE
;
491 if (panel
->sync
& FB_SYNC_HOR_HIGH_ACT
)
492 reg
|= LCD_INVERT_LINE_CLOCK
;
494 reg
&= ~LCD_INVERT_LINE_CLOCK
;
496 if (panel
->sync
& FB_SYNC_VERT_HIGH_ACT
)
497 reg
|= LCD_INVERT_FRAME_CLOCK
;
499 reg
&= ~LCD_INVERT_FRAME_CLOCK
;
501 lcdc_write(reg
, LCD_RASTER_TIMING_2_REG
);
506 static int lcd_cfg_frame_buffer(struct da8xx_fb_par
*par
, u32 width
, u32 height
,
507 u32 bpp
, u32 raster_order
)
511 if (bpp
> 16 && lcd_revision
== LCD_VERSION_1
)
514 /* Set the Panel Width */
515 /* Pixels per line = (PPL + 1)*16 */
516 if (lcd_revision
== LCD_VERSION_1
) {
518 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
524 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
530 reg
= lcdc_read(LCD_RASTER_TIMING_0_REG
);
532 if (lcd_revision
== LCD_VERSION_1
) {
533 reg
|= ((width
>> 4) - 1) << 4;
535 width
= (width
>> 4) - 1;
536 reg
|= ((width
& 0x3f) << 4) | ((width
& 0x40) >> 3);
538 lcdc_write(reg
, LCD_RASTER_TIMING_0_REG
);
540 /* Set the Panel Height */
541 /* Set bits 9:0 of Lines Per Pixel */
542 reg
= lcdc_read(LCD_RASTER_TIMING_1_REG
);
543 reg
= ((height
- 1) & 0x3ff) | (reg
& 0xfffffc00);
544 lcdc_write(reg
, LCD_RASTER_TIMING_1_REG
);
546 /* Set bit 10 of Lines Per Pixel */
547 if (lcd_revision
== LCD_VERSION_2
) {
548 reg
= lcdc_read(LCD_RASTER_TIMING_2_REG
);
549 reg
|= ((height
- 1) & 0x400) << 16;
550 lcdc_write(reg
, LCD_RASTER_TIMING_2_REG
);
553 /* Set the Raster Order of the Frame Buffer */
554 reg
= lcdc_read(LCD_RASTER_CTRL_REG
) & ~(1 << 8);
556 reg
|= LCD_RASTER_ORDER
;
558 par
->palette_sz
= 16 * 2;
567 reg
|= LCD_V2_TFT_24BPP_MODE
;
569 reg
|= LCD_V2_TFT_24BPP_UNPACK
;
573 par
->palette_sz
= 256 * 2;
580 lcdc_write(reg
, LCD_RASTER_CTRL_REG
);
585 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
586 static int fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
587 unsigned blue
, unsigned transp
,
588 struct fb_info
*info
)
590 struct da8xx_fb_par
*par
= info
->par
;
591 unsigned short *palette
= (unsigned short *) par
->v_palette_base
;
598 if (info
->fix
.visual
== FB_VISUAL_DIRECTCOLOR
)
601 if (info
->var
.bits_per_pixel
> 16 && lcd_revision
== LCD_VERSION_1
)
604 switch (info
->fix
.visual
) {
605 case FB_VISUAL_TRUECOLOR
:
606 red
= CNVT_TOHW(red
, info
->var
.red
.length
);
607 green
= CNVT_TOHW(green
, info
->var
.green
.length
);
608 blue
= CNVT_TOHW(blue
, info
->var
.blue
.length
);
610 case FB_VISUAL_PSEUDOCOLOR
:
611 switch (info
->var
.bits_per_pixel
) {
616 if (info
->var
.grayscale
) {
624 pal
|= green
& 0x00f0;
625 pal
|= blue
& 0x000f;
629 palette
[regno
] = pal
;
637 pal
= (red
& 0x0f00);
638 pal
|= (green
& 0x00f0);
639 pal
|= (blue
& 0x000f);
641 if (palette
[regno
] != pal
) {
643 palette
[regno
] = pal
;
650 /* Truecolor has hardware independent palette */
651 if (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) {
657 v
= (red
<< info
->var
.red
.offset
) |
658 (green
<< info
->var
.green
.offset
) |
659 (blue
<< info
->var
.blue
.offset
);
661 switch (info
->var
.bits_per_pixel
) {
663 ((u16
*) (info
->pseudo_palette
))[regno
] = v
;
667 ((u32
*) (info
->pseudo_palette
))[regno
] = v
;
670 if (palette
[0] != 0x4000) {
676 /* Update the palette in the h/w as needed. */
678 lcd_blit(LOAD_PALETTE
, par
);
684 static void lcd_reset(struct da8xx_fb_par
*par
)
686 /* Disable the Raster if previously Enabled */
687 lcd_disable_raster(false);
689 /* DMA has to be disabled */
690 lcdc_write(0, LCD_DMA_CTRL_REG
);
691 lcdc_write(0, LCD_RASTER_CTRL_REG
);
693 if (lcd_revision
== LCD_VERSION_2
) {
694 lcdc_write(0, LCD_INT_ENABLE_SET_REG
);
695 /* Write 1 to reset */
696 lcdc_write(LCD_CLK_MAIN_RESET
, LCD_CLK_RESET_REG
);
697 lcdc_write(0, LCD_CLK_RESET_REG
);
701 static void lcd_calc_clk_divider(struct da8xx_fb_par
*par
)
703 unsigned int lcd_clk
, div
;
705 lcd_clk
= clk_get_rate(par
->lcdc_clk
);
706 div
= lcd_clk
/ par
->pxl_clk
;
708 /* Configure the LCD clock divisor. */
709 lcdc_write(LCD_CLK_DIVISOR(div
) |
710 (LCD_RASTER_MODE
& 0x1), LCD_CTRL_REG
);
712 if (lcd_revision
== LCD_VERSION_2
)
713 lcdc_write(LCD_V2_DMA_CLK_EN
| LCD_V2_LIDD_CLK_EN
|
714 LCD_V2_CORE_CLK_EN
, LCD_CLK_ENABLE_REG
);
718 static int lcd_init(struct da8xx_fb_par
*par
, const struct lcd_ctrl_config
*cfg
,
719 struct fb_videomode
*panel
)
726 /* Calculate the divider */
727 lcd_calc_clk_divider(par
);
729 if (panel
->sync
& FB_SYNC_CLK_INVERT
)
730 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG
) |
731 LCD_INVERT_PIXEL_CLOCK
), LCD_RASTER_TIMING_2_REG
);
733 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG
) &
734 ~LCD_INVERT_PIXEL_CLOCK
), LCD_RASTER_TIMING_2_REG
);
736 /* Configure the DMA burst size and fifo threshold. */
737 ret
= lcd_cfg_dma(cfg
->dma_burst_sz
, cfg
->fifo_th
);
741 /* Configure the vertical and horizontal sync properties. */
742 lcd_cfg_vertical_sync(panel
->lower_margin
, panel
->vsync_len
,
743 panel
->upper_margin
);
744 lcd_cfg_horizontal_sync(panel
->right_margin
, panel
->hsync_len
,
747 /* Configure for disply */
748 ret
= lcd_cfg_display(cfg
, panel
);
756 ret
= lcd_cfg_frame_buffer(par
, (unsigned int)panel
->xres
,
757 (unsigned int)panel
->yres
, bpp
,
763 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG
) & 0xfff00fff) |
764 (cfg
->fdd
<< 12), LCD_RASTER_CTRL_REG
);
769 /* IRQ handler for version 2 of LCDC */
770 static irqreturn_t
lcdc_irq_handler_rev02(int irq
, void *arg
)
772 struct da8xx_fb_par
*par
= arg
;
773 u32 stat
= lcdc_read(LCD_MASKED_STAT_REG
);
775 if ((stat
& LCD_SYNC_LOST
) && (stat
& LCD_FIFO_UNDERFLOW
)) {
776 lcd_disable_raster(false);
777 lcdc_write(stat
, LCD_MASKED_STAT_REG
);
779 } else if (stat
& LCD_PL_LOAD_DONE
) {
781 * Must disable raster before changing state of any control bit.
782 * And also must be disabled before clearing the PL loading
783 * interrupt via the following write to the status register. If
784 * this is done after then one gets multiple PL done interrupts.
786 lcd_disable_raster(false);
788 lcdc_write(stat
, LCD_MASKED_STAT_REG
);
790 /* Disable PL completion interrupt */
791 lcdc_write(LCD_V2_PL_INT_ENA
, LCD_INT_ENABLE_CLR_REG
);
793 /* Setup and start data loading mode */
794 lcd_blit(LOAD_DATA
, par
);
796 lcdc_write(stat
, LCD_MASKED_STAT_REG
);
798 if (stat
& LCD_END_OF_FRAME0
) {
799 par
->which_dma_channel_done
= 0;
800 lcdc_write(par
->dma_start
,
801 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
802 lcdc_write(par
->dma_end
,
803 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
805 wake_up_interruptible(&par
->vsync_wait
);
808 if (stat
& LCD_END_OF_FRAME1
) {
809 par
->which_dma_channel_done
= 1;
810 lcdc_write(par
->dma_start
,
811 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
812 lcdc_write(par
->dma_end
,
813 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
815 wake_up_interruptible(&par
->vsync_wait
);
818 /* Set only when controller is disabled and at the end of
823 wake_up_interruptible(&frame_done_wq
);
827 lcdc_write(0, LCD_END_OF_INT_IND_REG
);
831 /* IRQ handler for version 1 LCDC */
832 static irqreturn_t
lcdc_irq_handler_rev01(int irq
, void *arg
)
834 struct da8xx_fb_par
*par
= arg
;
835 u32 stat
= lcdc_read(LCD_STAT_REG
);
838 if ((stat
& LCD_SYNC_LOST
) && (stat
& LCD_FIFO_UNDERFLOW
)) {
839 lcd_disable_raster(false);
840 lcdc_write(stat
, LCD_STAT_REG
);
842 } else if (stat
& LCD_PL_LOAD_DONE
) {
844 * Must disable raster before changing state of any control bit.
845 * And also must be disabled before clearing the PL loading
846 * interrupt via the following write to the status register. If
847 * this is done after then one gets multiple PL done interrupts.
849 lcd_disable_raster(false);
851 lcdc_write(stat
, LCD_STAT_REG
);
853 /* Disable PL completion inerrupt */
854 reg_ras
= lcdc_read(LCD_RASTER_CTRL_REG
);
855 reg_ras
&= ~LCD_V1_PL_INT_ENA
;
856 lcdc_write(reg_ras
, LCD_RASTER_CTRL_REG
);
858 /* Setup and start data loading mode */
859 lcd_blit(LOAD_DATA
, par
);
861 lcdc_write(stat
, LCD_STAT_REG
);
863 if (stat
& LCD_END_OF_FRAME0
) {
864 par
->which_dma_channel_done
= 0;
865 lcdc_write(par
->dma_start
,
866 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
867 lcdc_write(par
->dma_end
,
868 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
870 wake_up_interruptible(&par
->vsync_wait
);
873 if (stat
& LCD_END_OF_FRAME1
) {
874 par
->which_dma_channel_done
= 1;
875 lcdc_write(par
->dma_start
,
876 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
877 lcdc_write(par
->dma_end
,
878 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
880 wake_up_interruptible(&par
->vsync_wait
);
887 static int fb_check_var(struct fb_var_screeninfo
*var
,
888 struct fb_info
*info
)
892 if (var
->bits_per_pixel
> 16 && lcd_revision
== LCD_VERSION_1
)
895 switch (var
->bits_per_pixel
) {
900 var
->green
.offset
= 0;
901 var
->green
.length
= 8;
902 var
->blue
.offset
= 0;
903 var
->blue
.length
= 8;
904 var
->transp
.offset
= 0;
905 var
->transp
.length
= 0;
911 var
->green
.offset
= 0;
912 var
->green
.length
= 4;
913 var
->blue
.offset
= 0;
914 var
->blue
.length
= 4;
915 var
->transp
.offset
= 0;
916 var
->transp
.length
= 0;
917 var
->nonstd
= FB_NONSTD_REV_PIX_IN_B
;
919 case 16: /* RGB 565 */
920 var
->red
.offset
= 11;
922 var
->green
.offset
= 5;
923 var
->green
.length
= 6;
924 var
->blue
.offset
= 0;
925 var
->blue
.length
= 5;
926 var
->transp
.offset
= 0;
927 var
->transp
.length
= 0;
931 var
->red
.offset
= 16;
933 var
->green
.offset
= 8;
934 var
->green
.length
= 8;
935 var
->blue
.offset
= 0;
936 var
->blue
.length
= 8;
940 var
->transp
.offset
= 24;
941 var
->transp
.length
= 8;
942 var
->red
.offset
= 16;
944 var
->green
.offset
= 8;
945 var
->green
.length
= 8;
946 var
->blue
.offset
= 0;
947 var
->blue
.length
= 8;
954 var
->red
.msb_right
= 0;
955 var
->green
.msb_right
= 0;
956 var
->blue
.msb_right
= 0;
957 var
->transp
.msb_right
= 0;
961 #ifdef CONFIG_CPU_FREQ
962 static int lcd_da8xx_cpufreq_transition(struct notifier_block
*nb
,
963 unsigned long val
, void *data
)
965 struct da8xx_fb_par
*par
;
967 par
= container_of(nb
, struct da8xx_fb_par
, freq_transition
);
968 if (val
== CPUFREQ_POSTCHANGE
) {
969 if (par
->lcd_fck_rate
!= clk_get_rate(par
->lcdc_clk
)) {
970 par
->lcd_fck_rate
= clk_get_rate(par
->lcdc_clk
);
971 lcd_disable_raster(true);
972 lcd_calc_clk_divider(par
);
973 if (par
->blank
== FB_BLANK_UNBLANK
)
981 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par
*par
)
983 par
->freq_transition
.notifier_call
= lcd_da8xx_cpufreq_transition
;
985 return cpufreq_register_notifier(&par
->freq_transition
,
986 CPUFREQ_TRANSITION_NOTIFIER
);
989 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par
*par
)
991 cpufreq_unregister_notifier(&par
->freq_transition
,
992 CPUFREQ_TRANSITION_NOTIFIER
);
996 static int fb_remove(struct platform_device
*dev
)
998 struct fb_info
*info
= dev_get_drvdata(&dev
->dev
);
1001 struct da8xx_fb_par
*par
= info
->par
;
1003 #ifdef CONFIG_CPU_FREQ
1004 lcd_da8xx_cpufreq_deregister(par
);
1006 if (par
->panel_power_ctrl
)
1007 par
->panel_power_ctrl(0);
1009 lcd_disable_raster(true);
1010 lcdc_write(0, LCD_RASTER_CTRL_REG
);
1013 lcdc_write(0, LCD_DMA_CTRL_REG
);
1015 unregister_framebuffer(info
);
1016 fb_dealloc_cmap(&info
->cmap
);
1017 dma_free_coherent(NULL
, PALETTE_SIZE
, par
->v_palette_base
,
1018 par
->p_palette_base
);
1019 dma_free_coherent(NULL
, par
->vram_size
, par
->vram_virt
,
1021 free_irq(par
->irq
, par
);
1022 pm_runtime_put_sync(&dev
->dev
);
1023 pm_runtime_disable(&dev
->dev
);
1024 framebuffer_release(info
);
1025 iounmap(da8xx_fb_reg_base
);
1026 release_mem_region(lcdc_regs
->start
, resource_size(lcdc_regs
));
1033 * Function to wait for vertical sync which for this LCD peripheral
1034 * translates into waiting for the current raster frame to complete.
1036 static int fb_wait_for_vsync(struct fb_info
*info
)
1038 struct da8xx_fb_par
*par
= info
->par
;
1042 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1043 * race condition here where the ISR could have occurred just before or
1044 * just after this set. But since we are just coarsely waiting for
1045 * a frame to complete then that's OK. i.e. if the frame completed
1046 * just before this code executed then we have to wait another full
1047 * frame time but there is no way to avoid such a situation. On the
1048 * other hand if the frame completed just after then we don't need
1049 * to wait long at all. Either way we are guaranteed to return to the
1050 * user immediately after a frame completion which is all that is
1053 par
->vsync_flag
= 0;
1054 ret
= wait_event_interruptible_timeout(par
->vsync_wait
,
1055 par
->vsync_flag
!= 0,
1056 par
->vsync_timeout
);
1065 static int fb_ioctl(struct fb_info
*info
, unsigned int cmd
,
1068 struct lcd_sync_arg sync_arg
;
1071 case FBIOGET_CONTRAST
:
1072 case FBIOPUT_CONTRAST
:
1073 case FBIGET_BRIGHTNESS
:
1074 case FBIPUT_BRIGHTNESS
:
1079 if (copy_from_user(&sync_arg
, (char *)arg
,
1080 sizeof(struct lcd_sync_arg
)))
1082 lcd_cfg_horizontal_sync(sync_arg
.back_porch
,
1083 sync_arg
.pulse_width
,
1084 sync_arg
.front_porch
);
1087 if (copy_from_user(&sync_arg
, (char *)arg
,
1088 sizeof(struct lcd_sync_arg
)))
1090 lcd_cfg_vertical_sync(sync_arg
.back_porch
,
1091 sync_arg
.pulse_width
,
1092 sync_arg
.front_porch
);
1094 case FBIO_WAITFORVSYNC
:
1095 return fb_wait_for_vsync(info
);
1102 static int cfb_blank(int blank
, struct fb_info
*info
)
1104 struct da8xx_fb_par
*par
= info
->par
;
1107 if (par
->blank
== blank
)
1112 case FB_BLANK_UNBLANK
:
1113 lcd_enable_raster();
1115 if (par
->panel_power_ctrl
)
1116 par
->panel_power_ctrl(1);
1118 case FB_BLANK_NORMAL
:
1119 case FB_BLANK_VSYNC_SUSPEND
:
1120 case FB_BLANK_HSYNC_SUSPEND
:
1121 case FB_BLANK_POWERDOWN
:
1122 if (par
->panel_power_ctrl
)
1123 par
->panel_power_ctrl(0);
1125 lcd_disable_raster(true);
1135 * Set new x,y offsets in the virtual display for the visible area and switch
1138 static int da8xx_pan_display(struct fb_var_screeninfo
*var
,
1139 struct fb_info
*fbi
)
1142 struct fb_var_screeninfo new_var
;
1143 struct da8xx_fb_par
*par
= fbi
->par
;
1144 struct fb_fix_screeninfo
*fix
= &fbi
->fix
;
1147 unsigned long irq_flags
;
1149 if (var
->xoffset
!= fbi
->var
.xoffset
||
1150 var
->yoffset
!= fbi
->var
.yoffset
) {
1151 memcpy(&new_var
, &fbi
->var
, sizeof(new_var
));
1152 new_var
.xoffset
= var
->xoffset
;
1153 new_var
.yoffset
= var
->yoffset
;
1154 if (fb_check_var(&new_var
, fbi
))
1157 memcpy(&fbi
->var
, &new_var
, sizeof(new_var
));
1159 start
= fix
->smem_start
+
1160 new_var
.yoffset
* fix
->line_length
+
1161 new_var
.xoffset
* fbi
->var
.bits_per_pixel
/ 8;
1162 end
= start
+ fbi
->var
.yres
* fix
->line_length
- 1;
1163 par
->dma_start
= start
;
1165 spin_lock_irqsave(&par
->lock_for_chan_update
,
1167 if (par
->which_dma_channel_done
== 0) {
1168 lcdc_write(par
->dma_start
,
1169 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
1170 lcdc_write(par
->dma_end
,
1171 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
1172 } else if (par
->which_dma_channel_done
== 1) {
1173 lcdc_write(par
->dma_start
,
1174 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
1175 lcdc_write(par
->dma_end
,
1176 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
1178 spin_unlock_irqrestore(&par
->lock_for_chan_update
,
1186 static struct fb_ops da8xx_fb_ops
= {
1187 .owner
= THIS_MODULE
,
1188 .fb_check_var
= fb_check_var
,
1189 .fb_setcolreg
= fb_setcolreg
,
1190 .fb_pan_display
= da8xx_pan_display
,
1191 .fb_ioctl
= fb_ioctl
,
1192 .fb_fillrect
= cfb_fillrect
,
1193 .fb_copyarea
= cfb_copyarea
,
1194 .fb_imageblit
= cfb_imageblit
,
1195 .fb_blank
= cfb_blank
,
1198 /* Calculate and return pixel clock period in pico seconds */
1199 static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par
*par
)
1201 unsigned int lcd_clk
, div
;
1202 unsigned int configured_pix_clk
;
1203 unsigned long long pix_clk_period_picosec
= 1000000000000ULL;
1205 lcd_clk
= clk_get_rate(par
->lcdc_clk
);
1206 div
= lcd_clk
/ par
->pxl_clk
;
1207 configured_pix_clk
= (lcd_clk
/ div
);
1209 do_div(pix_clk_period_picosec
, configured_pix_clk
);
1211 return pix_clk_period_picosec
;
1214 static int fb_probe(struct platform_device
*device
)
1216 struct da8xx_lcdc_platform_data
*fb_pdata
=
1217 device
->dev
.platform_data
;
1218 struct lcd_ctrl_config
*lcd_cfg
;
1219 struct fb_videomode
*lcdc_info
;
1220 struct fb_info
*da8xx_fb_info
;
1221 struct clk
*fb_clk
= NULL
;
1222 struct da8xx_fb_par
*par
;
1223 resource_size_t len
;
1227 if (fb_pdata
== NULL
) {
1228 dev_err(&device
->dev
, "Can not get platform data\n");
1232 lcdc_regs
= platform_get_resource(device
, IORESOURCE_MEM
, 0);
1234 dev_err(&device
->dev
,
1235 "Can not get memory resource for LCD controller\n");
1239 len
= resource_size(lcdc_regs
);
1241 lcdc_regs
= request_mem_region(lcdc_regs
->start
, len
, lcdc_regs
->name
);
1245 da8xx_fb_reg_base
= ioremap(lcdc_regs
->start
, len
);
1246 if (!da8xx_fb_reg_base
) {
1248 goto err_request_mem
;
1251 fb_clk
= clk_get(&device
->dev
, "fck");
1252 if (IS_ERR(fb_clk
)) {
1253 dev_err(&device
->dev
, "Can not get device clock\n");
1258 pm_runtime_enable(&device
->dev
);
1259 pm_runtime_get_sync(&device
->dev
);
1261 /* Determine LCD IP Version */
1262 switch (lcdc_read(LCD_PID_REG
)) {
1264 lcd_revision
= LCD_VERSION_1
;
1268 lcd_revision
= LCD_VERSION_2
;
1271 dev_warn(&device
->dev
, "Unknown PID Reg value 0x%x, "
1272 "defaulting to LCD revision 1\n",
1273 lcdc_read(LCD_PID_REG
));
1274 lcd_revision
= LCD_VERSION_1
;
1278 for (i
= 0, lcdc_info
= known_lcd_panels
;
1279 i
< ARRAY_SIZE(known_lcd_panels
);
1281 if (strcmp(fb_pdata
->type
, lcdc_info
->name
) == 0)
1285 if (i
== ARRAY_SIZE(known_lcd_panels
)) {
1286 dev_err(&device
->dev
, "GLCD: No valid panel found\n");
1288 goto err_pm_runtime_disable
;
1290 dev_info(&device
->dev
, "GLCD: Found %s panel\n",
1293 lcd_cfg
= (struct lcd_ctrl_config
*)fb_pdata
->controller_data
;
1295 da8xx_fb_info
= framebuffer_alloc(sizeof(struct da8xx_fb_par
),
1297 if (!da8xx_fb_info
) {
1298 dev_dbg(&device
->dev
, "Memory allocation failed for fb_info\n");
1300 goto err_pm_runtime_disable
;
1303 par
= da8xx_fb_info
->par
;
1304 par
->lcdc_clk
= fb_clk
;
1305 #ifdef CONFIG_CPU_FREQ
1306 par
->lcd_fck_rate
= clk_get_rate(fb_clk
);
1308 par
->pxl_clk
= lcdc_info
->pixclock
;
1309 if (fb_pdata
->panel_power_ctrl
) {
1310 par
->panel_power_ctrl
= fb_pdata
->panel_power_ctrl
;
1311 par
->panel_power_ctrl(1);
1314 if (lcd_init(par
, lcd_cfg
, lcdc_info
) < 0) {
1315 dev_err(&device
->dev
, "lcd_init failed\n");
1317 goto err_release_fb
;
1320 /* allocate frame buffer */
1321 par
->vram_size
= lcdc_info
->xres
* lcdc_info
->yres
* lcd_cfg
->bpp
;
1322 ulcm
= lcm((lcdc_info
->xres
* lcd_cfg
->bpp
)/8, PAGE_SIZE
);
1323 par
->vram_size
= roundup(par
->vram_size
/8, ulcm
);
1324 par
->vram_size
= par
->vram_size
* LCD_NUM_BUFFERS
;
1326 par
->vram_virt
= dma_alloc_coherent(NULL
,
1328 (resource_size_t
*) &par
->vram_phys
,
1329 GFP_KERNEL
| GFP_DMA
);
1330 if (!par
->vram_virt
) {
1331 dev_err(&device
->dev
,
1332 "GLCD: kmalloc for frame buffer failed\n");
1334 goto err_release_fb
;
1337 da8xx_fb_info
->screen_base
= (char __iomem
*) par
->vram_virt
;
1338 da8xx_fb_fix
.smem_start
= par
->vram_phys
;
1339 da8xx_fb_fix
.smem_len
= par
->vram_size
;
1340 da8xx_fb_fix
.line_length
= (lcdc_info
->xres
* lcd_cfg
->bpp
) / 8;
1342 par
->dma_start
= par
->vram_phys
;
1343 par
->dma_end
= par
->dma_start
+ lcdc_info
->yres
*
1344 da8xx_fb_fix
.line_length
- 1;
1346 /* allocate palette buffer */
1347 par
->v_palette_base
= dma_alloc_coherent(NULL
,
1350 &par
->p_palette_base
,
1351 GFP_KERNEL
| GFP_DMA
);
1352 if (!par
->v_palette_base
) {
1353 dev_err(&device
->dev
,
1354 "GLCD: kmalloc for palette buffer failed\n");
1356 goto err_release_fb_mem
;
1358 memset(par
->v_palette_base
, 0, PALETTE_SIZE
);
1360 par
->irq
= platform_get_irq(device
, 0);
1363 goto err_release_pl_mem
;
1366 /* Initialize par */
1367 da8xx_fb_info
->var
.bits_per_pixel
= lcd_cfg
->bpp
;
1369 da8xx_fb_var
.xres
= lcdc_info
->xres
;
1370 da8xx_fb_var
.xres_virtual
= lcdc_info
->xres
;
1372 da8xx_fb_var
.yres
= lcdc_info
->yres
;
1373 da8xx_fb_var
.yres_virtual
= lcdc_info
->yres
* LCD_NUM_BUFFERS
;
1375 da8xx_fb_var
.grayscale
=
1376 lcd_cfg
->panel_shade
== MONOCHROME
? 1 : 0;
1377 da8xx_fb_var
.bits_per_pixel
= lcd_cfg
->bpp
;
1379 da8xx_fb_var
.hsync_len
= lcdc_info
->hsync_len
;
1380 da8xx_fb_var
.vsync_len
= lcdc_info
->vsync_len
;
1381 da8xx_fb_var
.right_margin
= lcdc_info
->right_margin
;
1382 da8xx_fb_var
.left_margin
= lcdc_info
->left_margin
;
1383 da8xx_fb_var
.lower_margin
= lcdc_info
->lower_margin
;
1384 da8xx_fb_var
.upper_margin
= lcdc_info
->upper_margin
;
1385 da8xx_fb_var
.pixclock
= da8xxfb_pixel_clk_period(par
);
1387 /* Initialize fbinfo */
1388 da8xx_fb_info
->flags
= FBINFO_FLAG_DEFAULT
;
1389 da8xx_fb_info
->fix
= da8xx_fb_fix
;
1390 da8xx_fb_info
->var
= da8xx_fb_var
;
1391 da8xx_fb_info
->fbops
= &da8xx_fb_ops
;
1392 da8xx_fb_info
->pseudo_palette
= par
->pseudo_palette
;
1393 da8xx_fb_info
->fix
.visual
= (da8xx_fb_info
->var
.bits_per_pixel
<= 8) ?
1394 FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
1396 ret
= fb_alloc_cmap(&da8xx_fb_info
->cmap
, PALETTE_SIZE
, 0);
1398 goto err_release_pl_mem
;
1399 da8xx_fb_info
->cmap
.len
= par
->palette_sz
;
1401 /* initialize var_screeninfo */
1402 da8xx_fb_var
.activate
= FB_ACTIVATE_FORCE
;
1403 fb_set_var(da8xx_fb_info
, &da8xx_fb_var
);
1405 dev_set_drvdata(&device
->dev
, da8xx_fb_info
);
1407 /* initialize the vsync wait queue */
1408 init_waitqueue_head(&par
->vsync_wait
);
1409 par
->vsync_timeout
= HZ
/ 5;
1410 par
->which_dma_channel_done
= -1;
1411 spin_lock_init(&par
->lock_for_chan_update
);
1413 /* Register the Frame Buffer */
1414 if (register_framebuffer(da8xx_fb_info
) < 0) {
1415 dev_err(&device
->dev
,
1416 "GLCD: Frame Buffer Registration Failed!\n");
1418 goto err_dealloc_cmap
;
1421 #ifdef CONFIG_CPU_FREQ
1422 ret
= lcd_da8xx_cpufreq_register(par
);
1424 dev_err(&device
->dev
, "failed to register cpufreq\n");
1429 if (lcd_revision
== LCD_VERSION_1
)
1430 lcdc_irq_handler
= lcdc_irq_handler_rev01
;
1432 init_waitqueue_head(&frame_done_wq
);
1433 lcdc_irq_handler
= lcdc_irq_handler_rev02
;
1436 ret
= request_irq(par
->irq
, lcdc_irq_handler
, 0,
1443 #ifdef CONFIG_CPU_FREQ
1444 lcd_da8xx_cpufreq_deregister(par
);
1447 unregister_framebuffer(da8xx_fb_info
);
1450 fb_dealloc_cmap(&da8xx_fb_info
->cmap
);
1453 dma_free_coherent(NULL
, PALETTE_SIZE
, par
->v_palette_base
,
1454 par
->p_palette_base
);
1457 dma_free_coherent(NULL
, par
->vram_size
, par
->vram_virt
, par
->vram_phys
);
1460 framebuffer_release(da8xx_fb_info
);
1462 err_pm_runtime_disable
:
1463 pm_runtime_put_sync(&device
->dev
);
1464 pm_runtime_disable(&device
->dev
);
1467 iounmap(da8xx_fb_reg_base
);
1470 release_mem_region(lcdc_regs
->start
, len
);
1476 struct lcdc_context
{
1480 u32 raster_timing_0
;
1481 u32 raster_timing_1
;
1482 u32 raster_timing_2
;
1484 u32 dma_frm_buf_base_addr_0
;
1485 u32 dma_frm_buf_ceiling_addr_0
;
1486 u32 dma_frm_buf_base_addr_1
;
1487 u32 dma_frm_buf_ceiling_addr_1
;
1491 static void lcd_context_save(void)
1493 if (lcd_revision
== LCD_VERSION_2
) {
1494 reg_context
.clk_enable
= lcdc_read(LCD_CLK_ENABLE_REG
);
1495 reg_context
.int_enable_set
= lcdc_read(LCD_INT_ENABLE_SET_REG
);
1498 reg_context
.ctrl
= lcdc_read(LCD_CTRL_REG
);
1499 reg_context
.dma_ctrl
= lcdc_read(LCD_DMA_CTRL_REG
);
1500 reg_context
.raster_timing_0
= lcdc_read(LCD_RASTER_TIMING_0_REG
);
1501 reg_context
.raster_timing_1
= lcdc_read(LCD_RASTER_TIMING_1_REG
);
1502 reg_context
.raster_timing_2
= lcdc_read(LCD_RASTER_TIMING_2_REG
);
1503 reg_context
.dma_frm_buf_base_addr_0
=
1504 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
1505 reg_context
.dma_frm_buf_ceiling_addr_0
=
1506 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
1507 reg_context
.dma_frm_buf_base_addr_1
=
1508 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
1509 reg_context
.dma_frm_buf_ceiling_addr_1
=
1510 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
1511 reg_context
.raster_ctrl
= lcdc_read(LCD_RASTER_CTRL_REG
);
1515 static void lcd_context_restore(void)
1517 if (lcd_revision
== LCD_VERSION_2
) {
1518 lcdc_write(reg_context
.clk_enable
, LCD_CLK_ENABLE_REG
);
1519 lcdc_write(reg_context
.int_enable_set
, LCD_INT_ENABLE_SET_REG
);
1522 lcdc_write(reg_context
.ctrl
, LCD_CTRL_REG
);
1523 lcdc_write(reg_context
.dma_ctrl
, LCD_DMA_CTRL_REG
);
1524 lcdc_write(reg_context
.raster_timing_0
, LCD_RASTER_TIMING_0_REG
);
1525 lcdc_write(reg_context
.raster_timing_1
, LCD_RASTER_TIMING_1_REG
);
1526 lcdc_write(reg_context
.raster_timing_2
, LCD_RASTER_TIMING_2_REG
);
1527 lcdc_write(reg_context
.dma_frm_buf_base_addr_0
,
1528 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG
);
1529 lcdc_write(reg_context
.dma_frm_buf_ceiling_addr_0
,
1530 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG
);
1531 lcdc_write(reg_context
.dma_frm_buf_base_addr_1
,
1532 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG
);
1533 lcdc_write(reg_context
.dma_frm_buf_ceiling_addr_1
,
1534 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG
);
1535 lcdc_write(reg_context
.raster_ctrl
, LCD_RASTER_CTRL_REG
);
1539 static int fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1541 struct fb_info
*info
= platform_get_drvdata(dev
);
1542 struct da8xx_fb_par
*par
= info
->par
;
1545 if (par
->panel_power_ctrl
)
1546 par
->panel_power_ctrl(0);
1548 fb_set_suspend(info
, 1);
1549 lcd_disable_raster(true);
1551 pm_runtime_put_sync(&dev
->dev
);
1556 static int fb_resume(struct platform_device
*dev
)
1558 struct fb_info
*info
= platform_get_drvdata(dev
);
1559 struct da8xx_fb_par
*par
= info
->par
;
1562 pm_runtime_get_sync(&dev
->dev
);
1563 lcd_context_restore();
1564 if (par
->blank
== FB_BLANK_UNBLANK
) {
1565 lcd_enable_raster();
1567 if (par
->panel_power_ctrl
)
1568 par
->panel_power_ctrl(1);
1571 fb_set_suspend(info
, 0);
1577 #define fb_suspend NULL
1578 #define fb_resume NULL
1581 static struct platform_driver da8xx_fb_driver
= {
1583 .remove
= fb_remove
,
1584 .suspend
= fb_suspend
,
1585 .resume
= fb_resume
,
1587 .name
= DRIVER_NAME
,
1588 .owner
= THIS_MODULE
,
1592 static int __init
da8xx_fb_init(void)
1594 return platform_driver_register(&da8xx_fb_driver
);
1597 static void __exit
da8xx_fb_cleanup(void)
1599 platform_driver_unregister(&da8xx_fb_driver
);
1602 module_init(da8xx_fb_init
);
1603 module_exit(da8xx_fb_cleanup
);
1605 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1606 MODULE_AUTHOR("Texas Instruments");
1607 MODULE_LICENSE("GPL");