tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json

   1 [
   2     {
   3         "EventCode": "0xAE",
   4         "Counter": "0,1,2,3",
   5         "UMask": "0x1",
   6         "EventName": "ITLB.ITLB_FLUSH",
   7         "SampleAfterValue": "100007",
   8         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
   9         "CounterHTOff": "0,1,2,3,4,5,6,7"
  10     },
  11     {
  12         "EventCode": "0x4F",
  13         "Counter": "0,1,2,3",
  14         "UMask": "0x10",
  15         "EventName": "EPT.WALK_CYCLES",
  16         "SampleAfterValue": "2000003",
  17         "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
  18         "CounterHTOff": "0,1,2,3,4,5,6,7"
  19     },
  20     {
  21         "EventCode": "0x85",
  22         "Counter": "0,1,2,3",
  23         "UMask": "0x1",
  24         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
  25         "SampleAfterValue": "100003",
  26         "BriefDescription": "Misses at all ITLB levels that cause page walks.",
  27         "CounterHTOff": "0,1,2,3,4,5,6,7"
  28     },
  29     {
  30         "EventCode": "0x85",
  31         "Counter": "0,1,2,3",
  32         "UMask": "0x2",
  33         "EventName": "ITLB_MISSES.WALK_COMPLETED",
  34         "SampleAfterValue": "100003",
  35         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
  36         "CounterHTOff": "0,1,2,3,4,5,6,7"
  37     },
  38     {
  39         "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
  40         "EventCode": "0x85",
  41         "Counter": "0,1,2,3",
  42         "UMask": "0x4",
  43         "EventName": "ITLB_MISSES.WALK_DURATION",
  44         "SampleAfterValue": "2000003",
  45         "BriefDescription": "Cycles when PMH is busy with page walks.",
  46         "CounterHTOff": "0,1,2,3,4,5,6,7"
  47     },
  48     {
  49         "EventCode": "0x85",
  50         "Counter": "0,1,2,3",
  51         "UMask": "0x10",
  52         "EventName": "ITLB_MISSES.STLB_HIT",
  53         "SampleAfterValue": "100003",
  54         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
  55         "CounterHTOff": "0,1,2,3,4,5,6,7"
  56     },
  57     {
  58         "EventCode": "0x08",
  59         "Counter": "0,1,2,3",
  60         "UMask": "0x1",
  61         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
  62         "SampleAfterValue": "100003",
  63         "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
  64         "CounterHTOff": "0,1,2,3,4,5,6,7"
  65     },
  66     {
  67         "EventCode": "0x08",
  68         "Counter": "0,1,2,3",
  69         "UMask": "0x2",
  70         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
  71         "SampleAfterValue": "100003",
  72         "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
  73         "CounterHTOff": "0,1,2,3,4,5,6,7"
  74     },
  75     {
  76         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
  77         "EventCode": "0x08",
  78         "Counter": "0,1,2,3",
  79         "UMask": "0x4",
  80         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
  81         "SampleAfterValue": "2000003",
  82         "BriefDescription": "Cycles when PMH is busy with page walks.",
  83         "CounterHTOff": "0,1,2,3,4,5,6,7"
  84     },
  85     {
  86         "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
  87         "EventCode": "0x08",
  88         "Counter": "0,1,2,3",
  89         "UMask": "0x10",
  90         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
  91         "SampleAfterValue": "100003",
  92         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
  93         "CounterHTOff": "0,1,2,3,4,5,6,7"
  94     },
  95     {
  96         "EventCode": "0x49",
  97         "Counter": "0,1,2,3",
  98         "UMask": "0x1",
  99         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
 100         "SampleAfterValue": "100003",
 101         "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
 102         "CounterHTOff": "0,1,2,3,4,5,6,7"
 103     },
 104     {
 105         "EventCode": "0x49",
 106         "Counter": "0,1,2,3",
 107         "UMask": "0x2",
 108         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
 109         "SampleAfterValue": "100003",
 110         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
 111         "CounterHTOff": "0,1,2,3,4,5,6,7"
 112     },
 113     {
 114         "EventCode": "0x49",
 115         "Counter": "0,1,2,3",
 116         "UMask": "0x4",
 117         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
 118         "SampleAfterValue": "2000003",
 119         "BriefDescription": "Cycles when PMH is busy with page walks.",
 120         "CounterHTOff": "0,1,2,3,4,5,6,7"
 121     },
 122     {
 123         "EventCode": "0x49",
 124         "Counter": "0,1,2,3",
 125         "UMask": "0x10",
 126         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
 127         "SampleAfterValue": "100003",
 128         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
 129         "CounterHTOff": "0,1,2,3,4,5,6,7"
 130     },
 131     {
 132         "EventCode": "0xBD",
 133         "Counter": "0,1,2,3",
 134         "UMask": "0x1",
 135         "EventName": "TLB_FLUSH.DTLB_THREAD",
 136         "SampleAfterValue": "100007",
 137         "BriefDescription": "DTLB flush attempts of the thread-specific entries.",
 138         "CounterHTOff": "0,1,2,3,4,5,6,7"
 139     },
 140     {
 141         "EventCode": "0xBD",
 142         "Counter": "0,1,2,3",
 143         "UMask": "0x20",
 144         "EventName": "TLB_FLUSH.STLB_ANY",
 145         "SampleAfterValue": "100007",
 146         "BriefDescription": "STLB flush attempts.",
 147         "CounterHTOff": "0,1,2,3,4,5,6,7"
 148     }
 149 ]