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ALSA: hda/ca0132 - Call pci_iounmap() instead of iounmap()
[linux/fpc-iii.git] / drivers / iommu / amd_iommu_init.c
blobbb2cd29e165885d1697e4d77614a42333c5457dc
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/mem_encrypt.h>
33 #include <asm/pci-direct.h>
34 #include <asm/iommu.h>
35 #include <asm/gart.h>
36 #include <asm/x86_init.h>
37 #include <asm/iommu_table.h>
38 #include <asm/io_apic.h>
39 #include <asm/irq_remapping.h>
40
41 #include <linux/crash_dump.h>
42 #include "amd_iommu_proto.h"
43 #include "amd_iommu_types.h"
44 #include "irq_remapping.h"
45
46 /*
47 * definitions for the ACPI scanning code
48 */
49 #define IVRS_HEADER_LENGTH 48
50
51 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
52 #define ACPI_IVMD_TYPE_ALL 0x20
53 #define ACPI_IVMD_TYPE 0x21
54 #define ACPI_IVMD_TYPE_RANGE 0x22
55
56 #define IVHD_DEV_ALL 0x01
57 #define IVHD_DEV_SELECT 0x02
58 #define IVHD_DEV_SELECT_RANGE_START 0x03
59 #define IVHD_DEV_RANGE_END 0x04
60 #define IVHD_DEV_ALIAS 0x42
61 #define IVHD_DEV_ALIAS_RANGE 0x43
62 #define IVHD_DEV_EXT_SELECT 0x46
63 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
64 #define IVHD_DEV_SPECIAL 0x48
65 #define IVHD_DEV_ACPI_HID 0xf0
66
67 #define UID_NOT_PRESENT 0
68 #define UID_IS_INTEGER 1
69 #define UID_IS_CHARACTER 2
70
71 #define IVHD_SPECIAL_IOAPIC 1
72 #define IVHD_SPECIAL_HPET 2
73
74 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
75 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
76 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
77 #define IVHD_FLAG_ISOC_EN_MASK 0x08
78
79 #define IVMD_FLAG_EXCL_RANGE 0x08
80 #define IVMD_FLAG_UNITY_MAP 0x01
81
82 #define ACPI_DEVFLAG_INITPASS 0x01
83 #define ACPI_DEVFLAG_EXTINT 0x02
84 #define ACPI_DEVFLAG_NMI 0x04
85 #define ACPI_DEVFLAG_SYSMGT1 0x10
86 #define ACPI_DEVFLAG_SYSMGT2 0x20
87 #define ACPI_DEVFLAG_LINT0 0x40
88 #define ACPI_DEVFLAG_LINT1 0x80
89 #define ACPI_DEVFLAG_ATSDIS 0x10000000
90
91 #define LOOP_TIMEOUT 100000
92 /*
93 * ACPI table definitions
94 *
95 * These data structures are laid over the table to parse the important values
96 * out of it.
97 */
98
99 extern const struct iommu_ops amd_iommu_ops;
100
101 /*
102 * structure describing one IOMMU in the ACPI table. Typically followed by one
103 * or more ivhd_entrys.
104 */
105 struct ivhd_header {
106 u8 type;
107 u8 flags;
108 u16 length;
109 u16 devid;
110 u16 cap_ptr;
111 u64 mmio_phys;
112 u16 pci_seg;
113 u16 info;
114 u32 efr_attr;
115
116 /* Following only valid on IVHD type 11h and 40h */
117 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
118 u64 res;
119 } __attribute__((packed));
120
121 /*
122 * A device entry describing which devices a specific IOMMU translates and
123 * which requestor ids they use.
124 */
125 struct ivhd_entry {
126 u8 type;
127 u16 devid;
128 u8 flags;
129 u32 ext;
130 u32 hidh;
131 u64 cid;
132 u8 uidf;
133 u8 uidl;
134 u8 uid;
135 } __attribute__((packed));
136
137 /*
138 * An AMD IOMMU memory definition structure. It defines things like exclusion
139 * ranges for devices and regions that should be unity mapped.
140 */
141 struct ivmd_header {
142 u8 type;
143 u8 flags;
144 u16 length;
145 u16 devid;
146 u16 aux;
147 u64 resv;
148 u64 range_start;
149 u64 range_length;
150 } __attribute__((packed));
151
152 bool amd_iommu_dump;
153 bool amd_iommu_irq_remap __read_mostly;
154
155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
156 static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
157
158 static bool amd_iommu_detected;
159 static bool __initdata amd_iommu_disabled;
160 static int amd_iommu_target_ivhd_type;
161
162 u16 amd_iommu_last_bdf; /* largest PCI device id we have
163 to handle */
164 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
165 we find in ACPI */
166 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
167
168 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
169 system */
170
171 /* Array to assign indices to IOMMUs*/
172 struct amd_iommu *amd_iommus[MAX_IOMMUS];
173
174 /* Number of IOMMUs present in the system */
175 static int amd_iommus_present;
176
177 /* IOMMUs have a non-present cache? */
178 bool amd_iommu_np_cache __read_mostly;
179 bool amd_iommu_iotlb_sup __read_mostly = true;
180
181 u32 amd_iommu_max_pasid __read_mostly = ~0;
182
183 bool amd_iommu_v2_present __read_mostly;
184 static bool amd_iommu_pc_present __read_mostly;
185
186 bool amd_iommu_force_isolation __read_mostly;
187
188 /*
189 * List of protection domains - used during resume
190 */
191 LIST_HEAD(amd_iommu_pd_list);
192 spinlock_t amd_iommu_pd_lock;
193
194 /*
195 * Pointer to the device table which is shared by all AMD IOMMUs
196 * it is indexed by the PCI device id or the HT unit id and contains
197 * information about the domain the device belongs to as well as the
198 * page table root pointer.
199 */
200 struct dev_table_entry *amd_iommu_dev_table;
201 /*
202 * Pointer to a device table which the content of old device table
203 * will be copied to. It's only be used in kdump kernel.
204 */
205 static struct dev_table_entry *old_dev_tbl_cpy;
206
207 /*
208 * The alias table is a driver specific data structure which contains the
209 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
210 * More than one device can share the same requestor id.
211 */
212 u16 *amd_iommu_alias_table;
213
214 /*
215 * The rlookup table is used to find the IOMMU which is responsible
216 * for a specific device. It is also indexed by the PCI device id.
217 */
218 struct amd_iommu **amd_iommu_rlookup_table;
219 EXPORT_SYMBOL(amd_iommu_rlookup_table);
220
221 /*
222 * This table is used to find the irq remapping table for a given device id
223 * quickly.
224 */
225 struct irq_remap_table **irq_lookup_table;
226
227 /*
228 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
229 * to know which ones are already in use.
230 */
231 unsigned long *amd_iommu_pd_alloc_bitmap;
232
233 static u32 dev_table_size; /* size of the device table */
234 static u32 alias_table_size; /* size of the alias table */
235 static u32 rlookup_table_size; /* size if the rlookup table */
236
237 enum iommu_init_state {
238 IOMMU_START_STATE,
239 IOMMU_IVRS_DETECTED,
240 IOMMU_ACPI_FINISHED,
241 IOMMU_ENABLED,
242 IOMMU_PCI_INIT,
243 IOMMU_INTERRUPTS_EN,
244 IOMMU_DMA_OPS,
245 IOMMU_INITIALIZED,
246 IOMMU_NOT_FOUND,
247 IOMMU_INIT_ERROR,
248 IOMMU_CMDLINE_DISABLED,
249 };
250
251 /* Early ioapic and hpet maps from kernel command line */
252 #define EARLY_MAP_SIZE 4
253 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
254 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
255 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
256
257 static int __initdata early_ioapic_map_size;
258 static int __initdata early_hpet_map_size;
259 static int __initdata early_acpihid_map_size;
260
261 static bool __initdata cmdline_maps;
262
263 static enum iommu_init_state init_state = IOMMU_START_STATE;
264
265 static int amd_iommu_enable_interrupts(void);
266 static int __init iommu_go_to_state(enum iommu_init_state state);
267 static void init_device_table_dma(void);
268
269 static bool amd_iommu_pre_enabled = true;
270
271 bool translation_pre_enabled(struct amd_iommu *iommu)
272 {
273 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
274 }
275 EXPORT_SYMBOL(translation_pre_enabled);
276
277 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
278 {
279 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
280 }
281
282 static void init_translation_status(struct amd_iommu *iommu)
283 {
284 u64 ctrl;
285
286 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
287 if (ctrl & (1<<CONTROL_IOMMU_EN))
288 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
289 }
290
291 static inline void update_last_devid(u16 devid)
292 {
293 if (devid > amd_iommu_last_bdf)
294 amd_iommu_last_bdf = devid;
295 }
296
297 static inline unsigned long tbl_size(int entry_size)
298 {
299 unsigned shift = PAGE_SHIFT +
300 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
301
302 return 1UL << shift;
303 }
304
305 int amd_iommu_get_num_iommus(void)
306 {
307 return amd_iommus_present;
308 }
309
310 /* Access to l1 and l2 indexed register spaces */
311
312 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
313 {
314 u32 val;
315
316 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
317 pci_read_config_dword(iommu->dev, 0xfc, &val);
318 return val;
319 }
320
321 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
322 {
323 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
324 pci_write_config_dword(iommu->dev, 0xfc, val);
325 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
326 }
327
328 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
329 {
330 u32 val;
331
332 pci_write_config_dword(iommu->dev, 0xf0, address);
333 pci_read_config_dword(iommu->dev, 0xf4, &val);
334 return val;
335 }
336
337 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
338 {
339 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
340 pci_write_config_dword(iommu->dev, 0xf4, val);
341 }
342
343 /****************************************************************************
344 *
345 * AMD IOMMU MMIO register space handling functions
346 *
347 * These functions are used to program the IOMMU device registers in
348 * MMIO space required for that driver.
349 *
350 ****************************************************************************/
351
352 /*
353 * This function set the exclusion range in the IOMMU. DMA accesses to the
354 * exclusion range are passed through untranslated
355 */
356 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
357 {
358 u64 start = iommu->exclusion_start & PAGE_MASK;
359 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
360 u64 entry;
361
362 if (!iommu->exclusion_start)
363 return;
364
365 entry = start | MMIO_EXCL_ENABLE_MASK;
366 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
367 &entry, sizeof(entry));
368
369 entry = limit;
370 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
371 &entry, sizeof(entry));
372 }
373
374 /* Programs the physical address of the device table into the IOMMU hardware */
375 static void iommu_set_device_table(struct amd_iommu *iommu)
376 {
377 u64 entry;
378
379 BUG_ON(iommu->mmio_base == NULL);
380
381 entry = iommu_virt_to_phys(amd_iommu_dev_table);
382 entry |= (dev_table_size >> 12) - 1;
383 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
384 &entry, sizeof(entry));
385 }
386
387 /* Generic functions to enable/disable certain features of the IOMMU. */
388 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
389 {
390 u64 ctrl;
391
392 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
393 ctrl |= (1ULL << bit);
394 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
395 }
396
397 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
398 {
399 u64 ctrl;
400
401 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
402 ctrl &= ~(1ULL << bit);
403 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
404 }
405
406 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
407 {
408 u64 ctrl;
409
410 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
411 ctrl &= ~CTRL_INV_TO_MASK;
412 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
413 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
414 }
415
416 /* Function to enable the hardware */
417 static void iommu_enable(struct amd_iommu *iommu)
418 {
419 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
420 }
421
422 static void iommu_disable(struct amd_iommu *iommu)
423 {
424 /* Disable command buffer */
425 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
426
427 /* Disable event logging and event interrupts */
428 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
429 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
430
431 /* Disable IOMMU GA_LOG */
432 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
433 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
434
435 /* Disable IOMMU hardware itself */
436 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
437 }
438
439 /*
440 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
441 * the system has one.
442 */
443 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
444 {
445 if (!request_mem_region(address, end, "amd_iommu")) {
446 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
447 address, end);
448 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
449 return NULL;
450 }
451
452 return (u8 __iomem *)ioremap_nocache(address, end);
453 }
454
455 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
456 {
457 if (iommu->mmio_base)
458 iounmap(iommu->mmio_base);
459 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
460 }
461
462 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
463 {
464 u32 size = 0;
465
466 switch (h->type) {
467 case 0x10:
468 size = 24;
469 break;
470 case 0x11:
471 case 0x40:
472 size = 40;
473 break;
474 }
475 return size;
476 }
477
478 /****************************************************************************
479 *
480 * The functions below belong to the first pass of AMD IOMMU ACPI table
481 * parsing. In this pass we try to find out the highest device id this
482 * code has to handle. Upon this information the size of the shared data
483 * structures is determined later.
484 *
485 ****************************************************************************/
486
487 /*
488 * This function calculates the length of a given IVHD entry
489 */
490 static inline int ivhd_entry_length(u8 *ivhd)
491 {
492 u32 type = ((struct ivhd_entry *)ivhd)->type;
493
494 if (type < 0x80) {
495 return 0x04 << (*ivhd >> 6);
496 } else if (type == IVHD_DEV_ACPI_HID) {
497 /* For ACPI_HID, offset 21 is uid len */
498 return *((u8 *)ivhd + 21) + 22;
499 }
500 return 0;
501 }
502
503 /*
504 * After reading the highest device id from the IOMMU PCI capability header
505 * this function looks if there is a higher device id defined in the ACPI table
506 */
507 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
508 {
509 u8 *p = (void *)h, *end = (void *)h;
510 struct ivhd_entry *dev;
511
512 u32 ivhd_size = get_ivhd_header_size(h);
513
514 if (!ivhd_size) {
515 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
516 return -EINVAL;
517 }
518
519 p += ivhd_size;
520 end += h->length;
521
522 while (p < end) {
523 dev = (struct ivhd_entry *)p;
524 switch (dev->type) {
525 case IVHD_DEV_ALL:
526 /* Use maximum BDF value for DEV_ALL */
527 update_last_devid(0xffff);
528 break;
529 case IVHD_DEV_SELECT:
530 case IVHD_DEV_RANGE_END:
531 case IVHD_DEV_ALIAS:
532 case IVHD_DEV_EXT_SELECT:
533 /* all the above subfield types refer to device ids */
534 update_last_devid(dev->devid);
535 break;
536 default:
537 break;
538 }
539 p += ivhd_entry_length(p);
540 }
541
542 WARN_ON(p != end);
543
544 return 0;
545 }
546
547 static int __init check_ivrs_checksum(struct acpi_table_header *table)
548 {
549 int i;
550 u8 checksum = 0, *p = (u8 *)table;
551
552 for (i = 0; i < table->length; ++i)
553 checksum += p[i];
554 if (checksum != 0) {
555 /* ACPI table corrupt */
556 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
557 return -ENODEV;
558 }
559
560 return 0;
561 }
562
563 /*
564 * Iterate over all IVHD entries in the ACPI table and find the highest device
565 * id which we need to handle. This is the first of three functions which parse
566 * the ACPI table. So we check the checksum here.
567 */
568 static int __init find_last_devid_acpi(struct acpi_table_header *table)
569 {
570 u8 *p = (u8 *)table, *end = (u8 *)table;
571 struct ivhd_header *h;
572
573 p += IVRS_HEADER_LENGTH;
574
575 end += table->length;
576 while (p < end) {
577 h = (struct ivhd_header *)p;
578 if (h->type == amd_iommu_target_ivhd_type) {
579 int ret = find_last_devid_from_ivhd(h);
580
581 if (ret)
582 return ret;
583 }
584 p += h->length;
585 }
586 WARN_ON(p != end);
587
588 return 0;
589 }
590
591 /****************************************************************************
592 *
593 * The following functions belong to the code path which parses the ACPI table
594 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
595 * data structures, initialize the device/alias/rlookup table and also
596 * basically initialize the hardware.
597 *
598 ****************************************************************************/
599
600 /*
601 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
602 * write commands to that buffer later and the IOMMU will execute them
603 * asynchronously
604 */
605 static int __init alloc_command_buffer(struct amd_iommu *iommu)
606 {
607 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
608 get_order(CMD_BUFFER_SIZE));
609
610 return iommu->cmd_buf ? 0 : -ENOMEM;
611 }
612
613 /*
614 * This function resets the command buffer if the IOMMU stopped fetching
615 * commands from it.
616 */
617 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
618 {
619 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
620
621 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
622 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
623 iommu->cmd_buf_head = 0;
624 iommu->cmd_buf_tail = 0;
625
626 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
627 }
628
629 /*
630 * This function writes the command buffer address to the hardware and
631 * enables it.
632 */
633 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
634 {
635 u64 entry;
636
637 BUG_ON(iommu->cmd_buf == NULL);
638
639 entry = iommu_virt_to_phys(iommu->cmd_buf);
640 entry |= MMIO_CMD_SIZE_512;
641
642 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
643 &entry, sizeof(entry));
644
645 amd_iommu_reset_cmd_buffer(iommu);
646 }
647
648 /*
649 * This function disables the command buffer
650 */
651 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
652 {
653 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
654 }
655
656 static void __init free_command_buffer(struct amd_iommu *iommu)
657 {
658 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
659 }
660
661 /* allocates the memory where the IOMMU will log its events to */
662 static int __init alloc_event_buffer(struct amd_iommu *iommu)
663 {
664 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
665 get_order(EVT_BUFFER_SIZE));
666
667 return iommu->evt_buf ? 0 : -ENOMEM;
668 }
669
670 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
671 {
672 u64 entry;
673
674 BUG_ON(iommu->evt_buf == NULL);
675
676 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
677
678 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
679 &entry, sizeof(entry));
680
681 /* set head and tail to zero manually */
682 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
683 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
684
685 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
686 }
687
688 /*
689 * This function disables the event log buffer
690 */
691 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
692 {
693 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
694 }
695
696 static void __init free_event_buffer(struct amd_iommu *iommu)
697 {
698 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
699 }
700
701 /* allocates the memory where the IOMMU will log its events to */
702 static int __init alloc_ppr_log(struct amd_iommu *iommu)
703 {
704 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
705 get_order(PPR_LOG_SIZE));
706
707 return iommu->ppr_log ? 0 : -ENOMEM;
708 }
709
710 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
711 {
712 u64 entry;
713
714 if (iommu->ppr_log == NULL)
715 return;
716
717 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
718
719 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
720 &entry, sizeof(entry));
721
722 /* set head and tail to zero manually */
723 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
724 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
725
726 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
727 iommu_feature_enable(iommu, CONTROL_PPR_EN);
728 }
729
730 static void __init free_ppr_log(struct amd_iommu *iommu)
731 {
732 if (iommu->ppr_log == NULL)
733 return;
734
735 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
736 }
737
738 static void free_ga_log(struct amd_iommu *iommu)
739 {
740 #ifdef CONFIG_IRQ_REMAP
741 if (iommu->ga_log)
742 free_pages((unsigned long)iommu->ga_log,
743 get_order(GA_LOG_SIZE));
744 if (iommu->ga_log_tail)
745 free_pages((unsigned long)iommu->ga_log_tail,
746 get_order(8));
747 #endif
748 }
749
750 static int iommu_ga_log_enable(struct amd_iommu *iommu)
751 {
752 #ifdef CONFIG_IRQ_REMAP
753 u32 status, i;
754
755 if (!iommu->ga_log)
756 return -EINVAL;
757
758 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
759
760 /* Check if already running */
761 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
762 return 0;
763
764 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
765 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
766
767 for (i = 0; i < LOOP_TIMEOUT; ++i) {
768 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
769 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
770 break;
771 }
772
773 if (i >= LOOP_TIMEOUT)
774 return -EINVAL;
775 #endif /* CONFIG_IRQ_REMAP */
776 return 0;
777 }
778
779 #ifdef CONFIG_IRQ_REMAP
780 static int iommu_init_ga_log(struct amd_iommu *iommu)
781 {
782 u64 entry;
783
784 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
785 return 0;
786
787 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
788 get_order(GA_LOG_SIZE));
789 if (!iommu->ga_log)
790 goto err_out;
791
792 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
793 get_order(8));
794 if (!iommu->ga_log_tail)
795 goto err_out;
796
797 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
798 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
799 &entry, sizeof(entry));
800 entry = (iommu_virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
801 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
802 &entry, sizeof(entry));
803 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
804 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
805
806 return 0;
807 err_out:
808 free_ga_log(iommu);
809 return -EINVAL;
810 }
811 #endif /* CONFIG_IRQ_REMAP */
812
813 static int iommu_init_ga(struct amd_iommu *iommu)
814 {
815 int ret = 0;
816
817 #ifdef CONFIG_IRQ_REMAP
818 /* Note: We have already checked GASup from IVRS table.
819 * Now, we need to make sure that GAMSup is set.
820 */
821 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
822 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
823 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
824
825 ret = iommu_init_ga_log(iommu);
826 #endif /* CONFIG_IRQ_REMAP */
827
828 return ret;
829 }
830
831 static void iommu_enable_xt(struct amd_iommu *iommu)
832 {
833 #ifdef CONFIG_IRQ_REMAP
834 /*
835 * XT mode (32-bit APIC destination ID) requires
836 * GA mode (128-bit IRTE support) as a prerequisite.
837 */
838 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
839 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
840 iommu_feature_enable(iommu, CONTROL_XT_EN);
841 #endif /* CONFIG_IRQ_REMAP */
842 }
843
844 static void iommu_enable_gt(struct amd_iommu *iommu)
845 {
846 if (!iommu_feature(iommu, FEATURE_GT))
847 return;
848
849 iommu_feature_enable(iommu, CONTROL_GT_EN);
850 }
851
852 /* sets a specific bit in the device table entry. */
853 static void set_dev_entry_bit(u16 devid, u8 bit)
854 {
855 int i = (bit >> 6) & 0x03;
856 int _bit = bit & 0x3f;
857
858 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
859 }
860
861 static int get_dev_entry_bit(u16 devid, u8 bit)
862 {
863 int i = (bit >> 6) & 0x03;
864 int _bit = bit & 0x3f;
865
866 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
867 }
868
869
870 static bool copy_device_table(void)
871 {
872 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
873 struct dev_table_entry *old_devtb = NULL;
874 u32 lo, hi, devid, old_devtb_size;
875 phys_addr_t old_devtb_phys;
876 struct amd_iommu *iommu;
877 u16 dom_id, dte_v, irq_v;
878 gfp_t gfp_flag;
879 u64 tmp;
880
881 if (!amd_iommu_pre_enabled)
882 return false;
883
884 pr_warn("Translation is already enabled - trying to copy translation structures\n");
885 for_each_iommu(iommu) {
886 /* All IOMMUs should use the same device table with the same size */
887 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
888 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
889 entry = (((u64) hi) << 32) + lo;
890 if (last_entry && last_entry != entry) {
891 pr_err("IOMMU:%d should use the same dev table as others!\n",
892 iommu->index);
893 return false;
894 }
895 last_entry = entry;
896
897 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
898 if (old_devtb_size != dev_table_size) {
899 pr_err("The device table size of IOMMU:%d is not expected!\n",
900 iommu->index);
901 return false;
902 }
903 }
904
905 /*
906 * When SME is enabled in the first kernel, the entry includes the
907 * memory encryption mask(sme_me_mask), we must remove the memory
908 * encryption mask to obtain the true physical address in kdump kernel.
909 */
910 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
911
912 if (old_devtb_phys >= 0x100000000ULL) {
913 pr_err("The address of old device table is above 4G, not trustworthy!\n");
914 return false;
915 }
916 old_devtb = (sme_active() && is_kdump_kernel())
917 ? (__force void *)ioremap_encrypted(old_devtb_phys,
918 dev_table_size)
919 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
920
921 if (!old_devtb)
922 return false;
923
924 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
925 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
926 get_order(dev_table_size));
927 if (old_dev_tbl_cpy == NULL) {
928 pr_err("Failed to allocate memory for copying old device table!\n");
929 return false;
930 }
931
932 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
933 old_dev_tbl_cpy[devid] = old_devtb[devid];
934 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
935 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
936
937 if (dte_v && dom_id) {
938 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
939 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
940 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
941 /* If gcr3 table existed, mask it out */
942 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
943 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
944 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
945 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
946 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
947 tmp |= DTE_FLAG_GV;
948 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
949 }
950 }
951
952 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
953 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
954 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
955 if (irq_v && (int_ctl || int_tab_len)) {
956 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
957 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
958 pr_err("Wrong old irq remapping flag: %#x\n", devid);
959 return false;
960 }
961
962 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
963 }
964 }
965 memunmap(old_devtb);
966
967 return true;
968 }
969
970 void amd_iommu_apply_erratum_63(u16 devid)
971 {
972 int sysmgt;
973
974 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
975 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
976
977 if (sysmgt == 0x01)
978 set_dev_entry_bit(devid, DEV_ENTRY_IW);
979 }
980
981 /* Writes the specific IOMMU for a device into the rlookup table */
982 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
983 {
984 amd_iommu_rlookup_table[devid] = iommu;
985 }
986
987 /*
988 * This function takes the device specific flags read from the ACPI
989 * table and sets up the device table entry with that information
990 */
991 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
992 u16 devid, u32 flags, u32 ext_flags)
993 {
994 if (flags & ACPI_DEVFLAG_INITPASS)
995 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
996 if (flags & ACPI_DEVFLAG_EXTINT)
997 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
998 if (flags & ACPI_DEVFLAG_NMI)
999 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
1000 if (flags & ACPI_DEVFLAG_SYSMGT1)
1001 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
1002 if (flags & ACPI_DEVFLAG_SYSMGT2)
1003 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
1004 if (flags & ACPI_DEVFLAG_LINT0)
1005 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
1006 if (flags & ACPI_DEVFLAG_LINT1)
1007 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
1008
1009 amd_iommu_apply_erratum_63(devid);
1010
1011 set_iommu_for_device(iommu, devid);
1012 }
1013
1014 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1015 {
1016 struct devid_map *entry;
1017 struct list_head *list;
1018
1019 if (type == IVHD_SPECIAL_IOAPIC)
1020 list = &ioapic_map;
1021 else if (type == IVHD_SPECIAL_HPET)
1022 list = &hpet_map;
1023 else
1024 return -EINVAL;
1025
1026 list_for_each_entry(entry, list, list) {
1027 if (!(entry->id == id && entry->cmd_line))
1028 continue;
1029
1030 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
1031 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1032
1033 *devid = entry->devid;
1034
1035 return 0;
1036 }
1037
1038 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1039 if (!entry)
1040 return -ENOMEM;
1041
1042 entry->id = id;
1043 entry->devid = *devid;
1044 entry->cmd_line = cmd_line;
1045
1046 list_add_tail(&entry->list, list);
1047
1048 return 0;
1049 }
1050
1051 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1052 bool cmd_line)
1053 {
1054 struct acpihid_map_entry *entry;
1055 struct list_head *list = &acpihid_map;
1056
1057 list_for_each_entry(entry, list, list) {
1058 if (strcmp(entry->hid, hid) ||
1059 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1060 !entry->cmd_line)
1061 continue;
1062
1063 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
1064 hid, uid);
1065 *devid = entry->devid;
1066 return 0;
1067 }
1068
1069 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1070 if (!entry)
1071 return -ENOMEM;
1072
1073 memcpy(entry->uid, uid, strlen(uid));
1074 memcpy(entry->hid, hid, strlen(hid));
1075 entry->devid = *devid;
1076 entry->cmd_line = cmd_line;
1077 entry->root_devid = (entry->devid & (~0x7));
1078
1079 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
1080 entry->cmd_line ? "cmd" : "ivrs",
1081 entry->hid, entry->uid, entry->root_devid);
1082
1083 list_add_tail(&entry->list, list);
1084 return 0;
1085 }
1086
1087 static int __init add_early_maps(void)
1088 {
1089 int i, ret;
1090
1091 for (i = 0; i < early_ioapic_map_size; ++i) {
1092 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1093 early_ioapic_map[i].id,
1094 &early_ioapic_map[i].devid,
1095 early_ioapic_map[i].cmd_line);
1096 if (ret)
1097 return ret;
1098 }
1099
1100 for (i = 0; i < early_hpet_map_size; ++i) {
1101 ret = add_special_device(IVHD_SPECIAL_HPET,
1102 early_hpet_map[i].id,
1103 &early_hpet_map[i].devid,
1104 early_hpet_map[i].cmd_line);
1105 if (ret)
1106 return ret;
1107 }
1108
1109 for (i = 0; i < early_acpihid_map_size; ++i) {
1110 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1111 early_acpihid_map[i].uid,
1112 &early_acpihid_map[i].devid,
1113 early_acpihid_map[i].cmd_line);
1114 if (ret)
1115 return ret;
1116 }
1117
1118 return 0;
1119 }
1120
1121 /*
1122 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1123 * it
1124 */
1125 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1126 {
1127 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1128
1129 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1130 return;
1131
1132 if (iommu) {
1133 /*
1134 * We only can configure exclusion ranges per IOMMU, not
1135 * per device. But we can enable the exclusion range per
1136 * device. This is done here
1137 */
1138 set_dev_entry_bit(devid, DEV_ENTRY_EX);
1139 iommu->exclusion_start = m->range_start;
1140 iommu->exclusion_length = m->range_length;
1141 }
1142 }
1143
1144 /*
1145 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1146 * initializes the hardware and our data structures with it.
1147 */
1148 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1149 struct ivhd_header *h)
1150 {
1151 u8 *p = (u8 *)h;
1152 u8 *end = p, flags = 0;
1153 u16 devid = 0, devid_start = 0, devid_to = 0;
1154 u32 dev_i, ext_flags = 0;
1155 bool alias = false;
1156 struct ivhd_entry *e;
1157 u32 ivhd_size;
1158 int ret;
1159
1160
1161 ret = add_early_maps();
1162 if (ret)
1163 return ret;
1164
1165 /*
1166 * First save the recommended feature enable bits from ACPI
1167 */
1168 iommu->acpi_flags = h->flags;
1169
1170 /*
1171 * Done. Now parse the device entries
1172 */
1173 ivhd_size = get_ivhd_header_size(h);
1174 if (!ivhd_size) {
1175 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1176 return -EINVAL;
1177 }
1178
1179 p += ivhd_size;
1180
1181 end += h->length;
1182
1183
1184 while (p < end) {
1185 e = (struct ivhd_entry *)p;
1186 switch (e->type) {
1187 case IVHD_DEV_ALL:
1188
1189 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1190
1191 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1192 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1193 break;
1194 case IVHD_DEV_SELECT:
1195
1196 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1197 "flags: %02x\n",
1198 PCI_BUS_NUM(e->devid),
1199 PCI_SLOT(e->devid),
1200 PCI_FUNC(e->devid),
1201 e->flags);
1202
1203 devid = e->devid;
1204 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1205 break;
1206 case IVHD_DEV_SELECT_RANGE_START:
1207
1208 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1209 "devid: %02x:%02x.%x flags: %02x\n",
1210 PCI_BUS_NUM(e->devid),
1211 PCI_SLOT(e->devid),
1212 PCI_FUNC(e->devid),
1213 e->flags);
1214
1215 devid_start = e->devid;
1216 flags = e->flags;
1217 ext_flags = 0;
1218 alias = false;
1219 break;
1220 case IVHD_DEV_ALIAS:
1221
1222 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1223 "flags: %02x devid_to: %02x:%02x.%x\n",
1224 PCI_BUS_NUM(e->devid),
1225 PCI_SLOT(e->devid),
1226 PCI_FUNC(e->devid),
1227 e->flags,
1228 PCI_BUS_NUM(e->ext >> 8),
1229 PCI_SLOT(e->ext >> 8),
1230 PCI_FUNC(e->ext >> 8));
1231
1232 devid = e->devid;
1233 devid_to = e->ext >> 8;
1234 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1235 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1236 amd_iommu_alias_table[devid] = devid_to;
1237 break;
1238 case IVHD_DEV_ALIAS_RANGE:
1239
1240 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1241 "devid: %02x:%02x.%x flags: %02x "
1242 "devid_to: %02x:%02x.%x\n",
1243 PCI_BUS_NUM(e->devid),
1244 PCI_SLOT(e->devid),
1245 PCI_FUNC(e->devid),
1246 e->flags,
1247 PCI_BUS_NUM(e->ext >> 8),
1248 PCI_SLOT(e->ext >> 8),
1249 PCI_FUNC(e->ext >> 8));
1250
1251 devid_start = e->devid;
1252 flags = e->flags;
1253 devid_to = e->ext >> 8;
1254 ext_flags = 0;
1255 alias = true;
1256 break;
1257 case IVHD_DEV_EXT_SELECT:
1258
1259 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1260 "flags: %02x ext: %08x\n",
1261 PCI_BUS_NUM(e->devid),
1262 PCI_SLOT(e->devid),
1263 PCI_FUNC(e->devid),
1264 e->flags, e->ext);
1265
1266 devid = e->devid;
1267 set_dev_entry_from_acpi(iommu, devid, e->flags,
1268 e->ext);
1269 break;
1270 case IVHD_DEV_EXT_SELECT_RANGE:
1271
1272 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1273 "%02x:%02x.%x flags: %02x ext: %08x\n",
1274 PCI_BUS_NUM(e->devid),
1275 PCI_SLOT(e->devid),
1276 PCI_FUNC(e->devid),
1277 e->flags, e->ext);
1278
1279 devid_start = e->devid;
1280 flags = e->flags;
1281 ext_flags = e->ext;
1282 alias = false;
1283 break;
1284 case IVHD_DEV_RANGE_END:
1285
1286 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1287 PCI_BUS_NUM(e->devid),
1288 PCI_SLOT(e->devid),
1289 PCI_FUNC(e->devid));
1290
1291 devid = e->devid;
1292 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1293 if (alias) {
1294 amd_iommu_alias_table[dev_i] = devid_to;
1295 set_dev_entry_from_acpi(iommu,
1296 devid_to, flags, ext_flags);
1297 }
1298 set_dev_entry_from_acpi(iommu, dev_i,
1299 flags, ext_flags);
1300 }
1301 break;
1302 case IVHD_DEV_SPECIAL: {
1303 u8 handle, type;
1304 const char *var;
1305 u16 devid;
1306 int ret;
1307
1308 handle = e->ext & 0xff;
1309 devid = (e->ext >> 8) & 0xffff;
1310 type = (e->ext >> 24) & 0xff;
1311
1312 if (type == IVHD_SPECIAL_IOAPIC)
1313 var = "IOAPIC";
1314 else if (type == IVHD_SPECIAL_HPET)
1315 var = "HPET";
1316 else
1317 var = "UNKNOWN";
1318
1319 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1320 var, (int)handle,
1321 PCI_BUS_NUM(devid),
1322 PCI_SLOT(devid),
1323 PCI_FUNC(devid));
1324
1325 ret = add_special_device(type, handle, &devid, false);
1326 if (ret)
1327 return ret;
1328
1329 /*
1330 * add_special_device might update the devid in case a
1331 * command-line override is present. So call
1332 * set_dev_entry_from_acpi after add_special_device.
1333 */
1334 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1335
1336 break;
1337 }
1338 case IVHD_DEV_ACPI_HID: {
1339 u16 devid;
1340 u8 hid[ACPIHID_HID_LEN] = {0};
1341 u8 uid[ACPIHID_UID_LEN] = {0};
1342 int ret;
1343
1344 if (h->type != 0x40) {
1345 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1346 e->type);
1347 break;
1348 }
1349
1350 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1351 hid[ACPIHID_HID_LEN - 1] = '\0';
1352
1353 if (!(*hid)) {
1354 pr_err(FW_BUG "Invalid HID.\n");
1355 break;
1356 }
1357
1358 switch (e->uidf) {
1359 case UID_NOT_PRESENT:
1360
1361 if (e->uidl != 0)
1362 pr_warn(FW_BUG "Invalid UID length.\n");
1363
1364 break;
1365 case UID_IS_INTEGER:
1366
1367 sprintf(uid, "%d", e->uid);
1368
1369 break;
1370 case UID_IS_CHARACTER:
1371
1372 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1373 uid[ACPIHID_UID_LEN - 1] = '\0';
1374
1375 break;
1376 default:
1377 break;
1378 }
1379
1380 devid = e->devid;
1381 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1382 hid, uid,
1383 PCI_BUS_NUM(devid),
1384 PCI_SLOT(devid),
1385 PCI_FUNC(devid));
1386
1387 flags = e->flags;
1388
1389 ret = add_acpi_hid_device(hid, uid, &devid, false);
1390 if (ret)
1391 return ret;
1392
1393 /*
1394 * add_special_device might update the devid in case a
1395 * command-line override is present. So call
1396 * set_dev_entry_from_acpi after add_special_device.
1397 */
1398 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1399
1400 break;
1401 }
1402 default:
1403 break;
1404 }
1405
1406 p += ivhd_entry_length(p);
1407 }
1408
1409 return 0;
1410 }
1411
1412 static void __init free_iommu_one(struct amd_iommu *iommu)
1413 {
1414 free_command_buffer(iommu);
1415 free_event_buffer(iommu);
1416 free_ppr_log(iommu);
1417 free_ga_log(iommu);
1418 iommu_unmap_mmio_space(iommu);
1419 }
1420
1421 static void __init free_iommu_all(void)
1422 {
1423 struct amd_iommu *iommu, *next;
1424
1425 for_each_iommu_safe(iommu, next) {
1426 list_del(&iommu->list);
1427 free_iommu_one(iommu);
1428 kfree(iommu);
1429 }
1430 }
1431
1432 /*
1433 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1434 * Workaround:
1435 * BIOS should disable L2B micellaneous clock gating by setting
1436 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1437 */
1438 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1439 {
1440 u32 value;
1441
1442 if ((boot_cpu_data.x86 != 0x15) ||
1443 (boot_cpu_data.x86_model < 0x10) ||
1444 (boot_cpu_data.x86_model > 0x1f))
1445 return;
1446
1447 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1448 pci_read_config_dword(iommu->dev, 0xf4, &value);
1449
1450 if (value & BIT(2))
1451 return;
1452
1453 /* Select NB indirect register 0x90 and enable writing */
1454 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1455
1456 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1457 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1458 dev_name(&iommu->dev->dev));
1459
1460 /* Clear the enable writing bit */
1461 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1462 }
1463
1464 /*
1465 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1466 * Workaround:
1467 * BIOS should enable ATS write permission check by setting
1468 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1469 */
1470 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1471 {
1472 u32 value;
1473
1474 if ((boot_cpu_data.x86 != 0x15) ||
1475 (boot_cpu_data.x86_model < 0x30) ||
1476 (boot_cpu_data.x86_model > 0x3f))
1477 return;
1478
1479 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1480 value = iommu_read_l2(iommu, 0x47);
1481
1482 if (value & BIT(0))
1483 return;
1484
1485 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1486 iommu_write_l2(iommu, 0x47, value | BIT(0));
1487
1488 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1489 dev_name(&iommu->dev->dev));
1490 }
1491
1492 /*
1493 * This function clues the initialization function for one IOMMU
1494 * together and also allocates the command buffer and programs the
1495 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1496 */
1497 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1498 {
1499 int ret;
1500
1501 raw_spin_lock_init(&iommu->lock);
1502
1503 /* Add IOMMU to internal data structures */
1504 list_add_tail(&iommu->list, &amd_iommu_list);
1505 iommu->index = amd_iommus_present++;
1506
1507 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1508 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1509 return -ENOSYS;
1510 }
1511
1512 /* Index is fine - add IOMMU to the array */
1513 amd_iommus[iommu->index] = iommu;
1514
1515 /*
1516 * Copy data from ACPI table entry to the iommu struct
1517 */
1518 iommu->devid = h->devid;
1519 iommu->cap_ptr = h->cap_ptr;
1520 iommu->pci_seg = h->pci_seg;
1521 iommu->mmio_phys = h->mmio_phys;
1522
1523 switch (h->type) {
1524 case 0x10:
1525 /* Check if IVHD EFR contains proper max banks/counters */
1526 if ((h->efr_attr != 0) &&
1527 ((h->efr_attr & (0xF << 13)) != 0) &&
1528 ((h->efr_attr & (0x3F << 17)) != 0))
1529 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1530 else
1531 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1532 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1533 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1534 if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
1535 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1536 break;
1537 case 0x11:
1538 case 0x40:
1539 if (h->efr_reg & (1 << 9))
1540 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1541 else
1542 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1543 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1544 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1545 if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
1546 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551
1552 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1553 iommu->mmio_phys_end);
1554 if (!iommu->mmio_base)
1555 return -ENOMEM;
1556
1557 if (alloc_command_buffer(iommu))
1558 return -ENOMEM;
1559
1560 if (alloc_event_buffer(iommu))
1561 return -ENOMEM;
1562
1563 iommu->int_enabled = false;
1564
1565 init_translation_status(iommu);
1566 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1567 iommu_disable(iommu);
1568 clear_translation_pre_enabled(iommu);
1569 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1570 iommu->index);
1571 }
1572 if (amd_iommu_pre_enabled)
1573 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1574
1575 ret = init_iommu_from_acpi(iommu, h);
1576 if (ret)
1577 return ret;
1578
1579 ret = amd_iommu_create_irq_domain(iommu);
1580 if (ret)
1581 return ret;
1582
1583 /*
1584 * Make sure IOMMU is not considered to translate itself. The IVRS
1585 * table tells us so, but this is a lie!
1586 */
1587 amd_iommu_rlookup_table[iommu->devid] = NULL;
1588
1589 return 0;
1590 }
1591
1592 /**
1593 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1594 * @ivrs Pointer to the IVRS header
1595 *
1596 * This function search through all IVDB of the maximum supported IVHD
1597 */
1598 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1599 {
1600 u8 *base = (u8 *)ivrs;
1601 struct ivhd_header *ivhd = (struct ivhd_header *)
1602 (base + IVRS_HEADER_LENGTH);
1603 u8 last_type = ivhd->type;
1604 u16 devid = ivhd->devid;
1605
1606 while (((u8 *)ivhd - base < ivrs->length) &&
1607 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1608 u8 *p = (u8 *) ivhd;
1609
1610 if (ivhd->devid == devid)
1611 last_type = ivhd->type;
1612 ivhd = (struct ivhd_header *)(p + ivhd->length);
1613 }
1614
1615 return last_type;
1616 }
1617
1618 /*
1619 * Iterates over all IOMMU entries in the ACPI table, allocates the
1620 * IOMMU structure and initializes it with init_iommu_one()
1621 */
1622 static int __init init_iommu_all(struct acpi_table_header *table)
1623 {
1624 u8 *p = (u8 *)table, *end = (u8 *)table;
1625 struct ivhd_header *h;
1626 struct amd_iommu *iommu;
1627 int ret;
1628
1629 end += table->length;
1630 p += IVRS_HEADER_LENGTH;
1631
1632 while (p < end) {
1633 h = (struct ivhd_header *)p;
1634 if (*p == amd_iommu_target_ivhd_type) {
1635
1636 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1637 "seg: %d flags: %01x info %04x\n",
1638 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1639 PCI_FUNC(h->devid), h->cap_ptr,
1640 h->pci_seg, h->flags, h->info);
1641 DUMP_printk(" mmio-addr: %016llx\n",
1642 h->mmio_phys);
1643
1644 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1645 if (iommu == NULL)
1646 return -ENOMEM;
1647
1648 ret = init_iommu_one(iommu, h);
1649 if (ret)
1650 return ret;
1651 }
1652 p += h->length;
1653
1654 }
1655 WARN_ON(p != end);
1656
1657 return 0;
1658 }
1659
1660 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1661 u8 fxn, u64 *value, bool is_write);
1662
1663 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1664 {
1665 u64 val = 0xabcd, val2 = 0;
1666
1667 if (!iommu_feature(iommu, FEATURE_PC))
1668 return;
1669
1670 amd_iommu_pc_present = true;
1671
1672 /* Check if the performance counters can be written to */
1673 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1674 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1675 (val != val2)) {
1676 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1677 amd_iommu_pc_present = false;
1678 return;
1679 }
1680
1681 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1682
1683 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1684 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1685 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1686 }
1687
1688 static ssize_t amd_iommu_show_cap(struct device *dev,
1689 struct device_attribute *attr,
1690 char *buf)
1691 {
1692 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1693 return sprintf(buf, "%x\n", iommu->cap);
1694 }
1695 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1696
1697 static ssize_t amd_iommu_show_features(struct device *dev,
1698 struct device_attribute *attr,
1699 char *buf)
1700 {
1701 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1702 return sprintf(buf, "%llx\n", iommu->features);
1703 }
1704 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1705
1706 static struct attribute *amd_iommu_attrs[] = {
1707 &dev_attr_cap.attr,
1708 &dev_attr_features.attr,
1709 NULL,
1710 };
1711
1712 static struct attribute_group amd_iommu_group = {
1713 .name = "amd-iommu",
1714 .attrs = amd_iommu_attrs,
1715 };
1716
1717 static const struct attribute_group *amd_iommu_groups[] = {
1718 &amd_iommu_group,
1719 NULL,
1720 };
1721
1722 static int __init iommu_init_pci(struct amd_iommu *iommu)
1723 {
1724 int cap_ptr = iommu->cap_ptr;
1725 u32 range, misc, low, high;
1726 int ret;
1727
1728 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1729 iommu->devid & 0xff);
1730 if (!iommu->dev)
1731 return -ENODEV;
1732
1733 /* Prevent binding other PCI device drivers to IOMMU devices */
1734 iommu->dev->match_driver = false;
1735
1736 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1737 &iommu->cap);
1738 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1739 &range);
1740 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1741 &misc);
1742
1743 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1744 amd_iommu_iotlb_sup = false;
1745
1746 /* read extended feature bits */
1747 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1748 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1749
1750 iommu->features = ((u64)high << 32) | low;
1751
1752 if (iommu_feature(iommu, FEATURE_GT)) {
1753 int glxval;
1754 u32 max_pasid;
1755 u64 pasmax;
1756
1757 pasmax = iommu->features & FEATURE_PASID_MASK;
1758 pasmax >>= FEATURE_PASID_SHIFT;
1759 max_pasid = (1 << (pasmax + 1)) - 1;
1760
1761 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1762
1763 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1764
1765 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1766 glxval >>= FEATURE_GLXVAL_SHIFT;
1767
1768 if (amd_iommu_max_glx_val == -1)
1769 amd_iommu_max_glx_val = glxval;
1770 else
1771 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1772 }
1773
1774 if (iommu_feature(iommu, FEATURE_GT) &&
1775 iommu_feature(iommu, FEATURE_PPR)) {
1776 iommu->is_iommu_v2 = true;
1777 amd_iommu_v2_present = true;
1778 }
1779
1780 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1781 return -ENOMEM;
1782
1783 ret = iommu_init_ga(iommu);
1784 if (ret)
1785 return ret;
1786
1787 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1788 amd_iommu_np_cache = true;
1789
1790 init_iommu_perf_ctr(iommu);
1791
1792 if (is_rd890_iommu(iommu->dev)) {
1793 int i, j;
1794
1795 iommu->root_pdev =
1796 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1797 PCI_DEVFN(0, 0));
1798
1799 /*
1800 * Some rd890 systems may not be fully reconfigured by the
1801 * BIOS, so it's necessary for us to store this information so
1802 * it can be reprogrammed on resume
1803 */
1804 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1805 &iommu->stored_addr_lo);
1806 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1807 &iommu->stored_addr_hi);
1808
1809 /* Low bit locks writes to configuration space */
1810 iommu->stored_addr_lo &= ~1;
1811
1812 for (i = 0; i < 6; i++)
1813 for (j = 0; j < 0x12; j++)
1814 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1815
1816 for (i = 0; i < 0x83; i++)
1817 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1818 }
1819
1820 amd_iommu_erratum_746_workaround(iommu);
1821 amd_iommu_ats_write_check_workaround(iommu);
1822
1823 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1824 amd_iommu_groups, "ivhd%d", iommu->index);
1825 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1826 iommu_device_register(&iommu->iommu);
1827
1828 return pci_enable_device(iommu->dev);
1829 }
1830
1831 static void print_iommu_info(void)
1832 {
1833 static const char * const feat_str[] = {
1834 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1835 "IA", "GA", "HE", "PC"
1836 };
1837 struct amd_iommu *iommu;
1838
1839 for_each_iommu(iommu) {
1840 int i;
1841
1842 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1843 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1844
1845 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1846 pr_info("AMD-Vi: Extended features (%#llx):\n",
1847 iommu->features);
1848 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1849 if (iommu_feature(iommu, (1ULL << i)))
1850 pr_cont(" %s", feat_str[i]);
1851 }
1852
1853 if (iommu->features & FEATURE_GAM_VAPIC)
1854 pr_cont(" GA_vAPIC");
1855
1856 pr_cont("\n");
1857 }
1858 }
1859 if (irq_remapping_enabled) {
1860 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1861 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1862 pr_info("AMD-Vi: virtual APIC enabled\n");
1863 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1864 pr_info("AMD-Vi: X2APIC enabled\n");
1865 }
1866 }
1867
1868 static int __init amd_iommu_init_pci(void)
1869 {
1870 struct amd_iommu *iommu;
1871 int ret = 0;
1872
1873 for_each_iommu(iommu) {
1874 ret = iommu_init_pci(iommu);
1875 if (ret)
1876 break;
1877 }
1878
1879 /*
1880 * Order is important here to make sure any unity map requirements are
1881 * fulfilled. The unity mappings are created and written to the device
1882 * table during the amd_iommu_init_api() call.
1883 *
1884 * After that we call init_device_table_dma() to make sure any
1885 * uninitialized DTE will block DMA, and in the end we flush the caches
1886 * of all IOMMUs to make sure the changes to the device table are
1887 * active.
1888 */
1889 ret = amd_iommu_init_api();
1890
1891 init_device_table_dma();
1892
1893 for_each_iommu(iommu)
1894 iommu_flush_all_caches(iommu);
1895
1896 if (!ret)
1897 print_iommu_info();
1898
1899 return ret;
1900 }
1901
1902 /****************************************************************************
1903 *
1904 * The following functions initialize the MSI interrupts for all IOMMUs
1905 * in the system. It's a bit challenging because there could be multiple
1906 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1907 * pci_dev.
1908 *
1909 ****************************************************************************/
1910
1911 static int iommu_setup_msi(struct amd_iommu *iommu)
1912 {
1913 int r;
1914
1915 r = pci_enable_msi(iommu->dev);
1916 if (r)
1917 return r;
1918
1919 r = request_threaded_irq(iommu->dev->irq,
1920 amd_iommu_int_handler,
1921 amd_iommu_int_thread,
1922 0, "AMD-Vi",
1923 iommu);
1924
1925 if (r) {
1926 pci_disable_msi(iommu->dev);
1927 return r;
1928 }
1929
1930 iommu->int_enabled = true;
1931
1932 return 0;
1933 }
1934
1935 static int iommu_init_msi(struct amd_iommu *iommu)
1936 {
1937 int ret;
1938
1939 if (iommu->int_enabled)
1940 goto enable_faults;
1941
1942 if (iommu->dev->msi_cap)
1943 ret = iommu_setup_msi(iommu);
1944 else
1945 ret = -ENODEV;
1946
1947 if (ret)
1948 return ret;
1949
1950 enable_faults:
1951 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1952
1953 if (iommu->ppr_log != NULL)
1954 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1955
1956 iommu_ga_log_enable(iommu);
1957
1958 return 0;
1959 }
1960
1961 /****************************************************************************
1962 *
1963 * The next functions belong to the third pass of parsing the ACPI
1964 * table. In this last pass the memory mapping requirements are
1965 * gathered (like exclusion and unity mapping ranges).
1966 *
1967 ****************************************************************************/
1968
1969 static void __init free_unity_maps(void)
1970 {
1971 struct unity_map_entry *entry, *next;
1972
1973 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1974 list_del(&entry->list);
1975 kfree(entry);
1976 }
1977 }
1978
1979 /* called when we find an exclusion range definition in ACPI */
1980 static int __init init_exclusion_range(struct ivmd_header *m)
1981 {
1982 int i;
1983
1984 switch (m->type) {
1985 case ACPI_IVMD_TYPE:
1986 set_device_exclusion_range(m->devid, m);
1987 break;
1988 case ACPI_IVMD_TYPE_ALL:
1989 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1990 set_device_exclusion_range(i, m);
1991 break;
1992 case ACPI_IVMD_TYPE_RANGE:
1993 for (i = m->devid; i <= m->aux; ++i)
1994 set_device_exclusion_range(i, m);
1995 break;
1996 default:
1997 break;
1998 }
1999
2000 return 0;
2001 }
2002
2003 /* called for unity map ACPI definition */
2004 static int __init init_unity_map_range(struct ivmd_header *m)
2005 {
2006 struct unity_map_entry *e = NULL;
2007 char *s;
2008
2009 e = kzalloc(sizeof(*e), GFP_KERNEL);
2010 if (e == NULL)
2011 return -ENOMEM;
2012
2013 switch (m->type) {
2014 default:
2015 kfree(e);
2016 return 0;
2017 case ACPI_IVMD_TYPE:
2018 s = "IVMD_TYPEi\t\t\t";
2019 e->devid_start = e->devid_end = m->devid;
2020 break;
2021 case ACPI_IVMD_TYPE_ALL:
2022 s = "IVMD_TYPE_ALL\t\t";
2023 e->devid_start = 0;
2024 e->devid_end = amd_iommu_last_bdf;
2025 break;
2026 case ACPI_IVMD_TYPE_RANGE:
2027 s = "IVMD_TYPE_RANGE\t\t";
2028 e->devid_start = m->devid;
2029 e->devid_end = m->aux;
2030 break;
2031 }
2032 e->address_start = PAGE_ALIGN(m->range_start);
2033 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2034 e->prot = m->flags >> 1;
2035
2036 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2037 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2038 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2039 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2040 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2041 e->address_start, e->address_end, m->flags);
2042
2043 list_add_tail(&e->list, &amd_iommu_unity_map);
2044
2045 return 0;
2046 }
2047
2048 /* iterates over all memory definitions we find in the ACPI table */
2049 static int __init init_memory_definitions(struct acpi_table_header *table)
2050 {
2051 u8 *p = (u8 *)table, *end = (u8 *)table;
2052 struct ivmd_header *m;
2053
2054 end += table->length;
2055 p += IVRS_HEADER_LENGTH;
2056
2057 while (p < end) {
2058 m = (struct ivmd_header *)p;
2059 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2060 init_exclusion_range(m);
2061 else if (m->flags & IVMD_FLAG_UNITY_MAP)
2062 init_unity_map_range(m);
2063
2064 p += m->length;
2065 }
2066
2067 return 0;
2068 }
2069
2070 /*
2071 * Init the device table to not allow DMA access for devices
2072 */
2073 static void init_device_table_dma(void)
2074 {
2075 u32 devid;
2076
2077 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2078 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2079 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2080 }
2081 }
2082
2083 static void __init uninit_device_table_dma(void)
2084 {
2085 u32 devid;
2086
2087 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2088 amd_iommu_dev_table[devid].data[0] = 0ULL;
2089 amd_iommu_dev_table[devid].data[1] = 0ULL;
2090 }
2091 }
2092
2093 static void init_device_table(void)
2094 {
2095 u32 devid;
2096
2097 if (!amd_iommu_irq_remap)
2098 return;
2099
2100 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2101 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2102 }
2103
2104 static void iommu_init_flags(struct amd_iommu *iommu)
2105 {
2106 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2107 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2108 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2109
2110 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2111 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2112 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2113
2114 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2115 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2116 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2117
2118 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2119 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2120 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2121
2122 /*
2123 * make IOMMU memory accesses cache coherent
2124 */
2125 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2126
2127 /* Set IOTLB invalidation timeout to 1s */
2128 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2129 }
2130
2131 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2132 {
2133 int i, j;
2134 u32 ioc_feature_control;
2135 struct pci_dev *pdev = iommu->root_pdev;
2136
2137 /* RD890 BIOSes may not have completely reconfigured the iommu */
2138 if (!is_rd890_iommu(iommu->dev) || !pdev)
2139 return;
2140
2141 /*
2142 * First, we need to ensure that the iommu is enabled. This is
2143 * controlled by a register in the northbridge
2144 */
2145
2146 /* Select Northbridge indirect register 0x75 and enable writing */
2147 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2148 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2149
2150 /* Enable the iommu */
2151 if (!(ioc_feature_control & 0x1))
2152 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2153
2154 /* Restore the iommu BAR */
2155 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2156 iommu->stored_addr_lo);
2157 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2158 iommu->stored_addr_hi);
2159
2160 /* Restore the l1 indirect regs for each of the 6 l1s */
2161 for (i = 0; i < 6; i++)
2162 for (j = 0; j < 0x12; j++)
2163 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2164
2165 /* Restore the l2 indirect regs */
2166 for (i = 0; i < 0x83; i++)
2167 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2168
2169 /* Lock PCI setup registers */
2170 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2171 iommu->stored_addr_lo | 1);
2172 }
2173
2174 static void iommu_enable_ga(struct amd_iommu *iommu)
2175 {
2176 #ifdef CONFIG_IRQ_REMAP
2177 switch (amd_iommu_guest_ir) {
2178 case AMD_IOMMU_GUEST_IR_VAPIC:
2179 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2180 /* Fall through */
2181 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2182 iommu_feature_enable(iommu, CONTROL_GA_EN);
2183 iommu->irte_ops = &irte_128_ops;
2184 break;
2185 default:
2186 iommu->irte_ops = &irte_32_ops;
2187 break;
2188 }
2189 #endif
2190 }
2191
2192 static void early_enable_iommu(struct amd_iommu *iommu)
2193 {
2194 iommu_disable(iommu);
2195 iommu_init_flags(iommu);
2196 iommu_set_device_table(iommu);
2197 iommu_enable_command_buffer(iommu);
2198 iommu_enable_event_buffer(iommu);
2199 iommu_set_exclusion_range(iommu);
2200 iommu_enable_ga(iommu);
2201 iommu_enable_xt(iommu);
2202 iommu_enable(iommu);
2203 iommu_flush_all_caches(iommu);
2204 }
2205
2206 /*
2207 * This function finally enables all IOMMUs found in the system after
2208 * they have been initialized.
2209 *
2210 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2211 * the old content of device table entries. Not this case or copy failed,
2212 * just continue as normal kernel does.
2213 */
2214 static void early_enable_iommus(void)
2215 {
2216 struct amd_iommu *iommu;
2217
2218
2219 if (!copy_device_table()) {
2220 /*
2221 * If come here because of failure in copying device table from old
2222 * kernel with all IOMMUs enabled, print error message and try to
2223 * free allocated old_dev_tbl_cpy.
2224 */
2225 if (amd_iommu_pre_enabled)
2226 pr_err("Failed to copy DEV table from previous kernel.\n");
2227 if (old_dev_tbl_cpy != NULL)
2228 free_pages((unsigned long)old_dev_tbl_cpy,
2229 get_order(dev_table_size));
2230
2231 for_each_iommu(iommu) {
2232 clear_translation_pre_enabled(iommu);
2233 early_enable_iommu(iommu);
2234 }
2235 } else {
2236 pr_info("Copied DEV table from previous kernel.\n");
2237 free_pages((unsigned long)amd_iommu_dev_table,
2238 get_order(dev_table_size));
2239 amd_iommu_dev_table = old_dev_tbl_cpy;
2240 for_each_iommu(iommu) {
2241 iommu_disable_command_buffer(iommu);
2242 iommu_disable_event_buffer(iommu);
2243 iommu_enable_command_buffer(iommu);
2244 iommu_enable_event_buffer(iommu);
2245 iommu_enable_ga(iommu);
2246 iommu_enable_xt(iommu);
2247 iommu_set_device_table(iommu);
2248 iommu_flush_all_caches(iommu);
2249 }
2250 }
2251
2252 #ifdef CONFIG_IRQ_REMAP
2253 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2254 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2255 #endif
2256 }
2257
2258 static void enable_iommus_v2(void)
2259 {
2260 struct amd_iommu *iommu;
2261
2262 for_each_iommu(iommu) {
2263 iommu_enable_ppr_log(iommu);
2264 iommu_enable_gt(iommu);
2265 }
2266 }
2267
2268 static void enable_iommus(void)
2269 {
2270 early_enable_iommus();
2271
2272 enable_iommus_v2();
2273 }
2274
2275 static void disable_iommus(void)
2276 {
2277 struct amd_iommu *iommu;
2278
2279 for_each_iommu(iommu)
2280 iommu_disable(iommu);
2281
2282 #ifdef CONFIG_IRQ_REMAP
2283 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2284 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2285 #endif
2286 }
2287
2288 /*
2289 * Suspend/Resume support
2290 * disable suspend until real resume implemented
2291 */
2292
2293 static void amd_iommu_resume(void)
2294 {
2295 struct amd_iommu *iommu;
2296
2297 for_each_iommu(iommu)
2298 iommu_apply_resume_quirks(iommu);
2299
2300 /* re-load the hardware */
2301 enable_iommus();
2302
2303 amd_iommu_enable_interrupts();
2304 }
2305
2306 static int amd_iommu_suspend(void)
2307 {
2308 /* disable IOMMUs to go out of the way for BIOS */
2309 disable_iommus();
2310
2311 return 0;
2312 }
2313
2314 static struct syscore_ops amd_iommu_syscore_ops = {
2315 .suspend = amd_iommu_suspend,
2316 .resume = amd_iommu_resume,
2317 };
2318
2319 static void __init free_iommu_resources(void)
2320 {
2321 kmemleak_free(irq_lookup_table);
2322 free_pages((unsigned long)irq_lookup_table,
2323 get_order(rlookup_table_size));
2324 irq_lookup_table = NULL;
2325
2326 kmem_cache_destroy(amd_iommu_irq_cache);
2327 amd_iommu_irq_cache = NULL;
2328
2329 free_pages((unsigned long)amd_iommu_rlookup_table,
2330 get_order(rlookup_table_size));
2331 amd_iommu_rlookup_table = NULL;
2332
2333 free_pages((unsigned long)amd_iommu_alias_table,
2334 get_order(alias_table_size));
2335 amd_iommu_alias_table = NULL;
2336
2337 free_pages((unsigned long)amd_iommu_dev_table,
2338 get_order(dev_table_size));
2339 amd_iommu_dev_table = NULL;
2340
2341 free_iommu_all();
2342
2343 #ifdef CONFIG_GART_IOMMU
2344 /*
2345 * We failed to initialize the AMD IOMMU - try fallback to GART
2346 * if possible.
2347 */
2348 gart_iommu_init();
2349
2350 #endif
2351 }
2352
2353 /* SB IOAPIC is always on this device in AMD systems */
2354 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2355
2356 static bool __init check_ioapic_information(void)
2357 {
2358 const char *fw_bug = FW_BUG;
2359 bool ret, has_sb_ioapic;
2360 int idx;
2361
2362 has_sb_ioapic = false;
2363 ret = false;
2364
2365 /*
2366 * If we have map overrides on the kernel command line the
2367 * messages in this function might not describe firmware bugs
2368 * anymore - so be careful
2369 */
2370 if (cmdline_maps)
2371 fw_bug = "";
2372
2373 for (idx = 0; idx < nr_ioapics; idx++) {
2374 int devid, id = mpc_ioapic_id(idx);
2375
2376 devid = get_ioapic_devid(id);
2377 if (devid < 0) {
2378 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2379 fw_bug, id);
2380 ret = false;
2381 } else if (devid == IOAPIC_SB_DEVID) {
2382 has_sb_ioapic = true;
2383 ret = true;
2384 }
2385 }
2386
2387 if (!has_sb_ioapic) {
2388 /*
2389 * We expect the SB IOAPIC to be listed in the IVRS
2390 * table. The system timer is connected to the SB IOAPIC
2391 * and if we don't have it in the list the system will
2392 * panic at boot time. This situation usually happens
2393 * when the BIOS is buggy and provides us the wrong
2394 * device id for the IOAPIC in the system.
2395 */
2396 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2397 }
2398
2399 if (!ret)
2400 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2401
2402 return ret;
2403 }
2404
2405 static void __init free_dma_resources(void)
2406 {
2407 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2408 get_order(MAX_DOMAIN_ID/8));
2409 amd_iommu_pd_alloc_bitmap = NULL;
2410
2411 free_unity_maps();
2412 }
2413
2414 /*
2415 * This is the hardware init function for AMD IOMMU in the system.
2416 * This function is called either from amd_iommu_init or from the interrupt
2417 * remapping setup code.
2418 *
2419 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2420 * four times:
2421 *
2422 * 1 pass) Discover the most comprehensive IVHD type to use.
2423 *
2424 * 2 pass) Find the highest PCI device id the driver has to handle.
2425 * Upon this information the size of the data structures is
2426 * determined that needs to be allocated.
2427 *
2428 * 3 pass) Initialize the data structures just allocated with the
2429 * information in the ACPI table about available AMD IOMMUs
2430 * in the system. It also maps the PCI devices in the
2431 * system to specific IOMMUs
2432 *
2433 * 4 pass) After the basic data structures are allocated and
2434 * initialized we update them with information about memory
2435 * remapping requirements parsed out of the ACPI table in
2436 * this last pass.
2437 *
2438 * After everything is set up the IOMMUs are enabled and the necessary
2439 * hotplug and suspend notifiers are registered.
2440 */
2441 static int __init early_amd_iommu_init(void)
2442 {
2443 struct acpi_table_header *ivrs_base;
2444 acpi_status status;
2445 int i, remap_cache_sz, ret = 0;
2446
2447 if (!amd_iommu_detected)
2448 return -ENODEV;
2449
2450 status = acpi_get_table("IVRS", 0, &ivrs_base);
2451 if (status == AE_NOT_FOUND)
2452 return -ENODEV;
2453 else if (ACPI_FAILURE(status)) {
2454 const char *err = acpi_format_exception(status);
2455 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2456 return -EINVAL;
2457 }
2458
2459 /*
2460 * Validate checksum here so we don't need to do it when
2461 * we actually parse the table
2462 */
2463 ret = check_ivrs_checksum(ivrs_base);
2464 if (ret)
2465 goto out;
2466
2467 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2468 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2469
2470 /*
2471 * First parse ACPI tables to find the largest Bus/Dev/Func
2472 * we need to handle. Upon this information the shared data
2473 * structures for the IOMMUs in the system will be allocated
2474 */
2475 ret = find_last_devid_acpi(ivrs_base);
2476 if (ret)
2477 goto out;
2478
2479 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2480 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2481 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2482
2483 /* Device table - directly used by all IOMMUs */
2484 ret = -ENOMEM;
2485 amd_iommu_dev_table = (void *)__get_free_pages(
2486 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2487 get_order(dev_table_size));
2488 if (amd_iommu_dev_table == NULL)
2489 goto out;
2490
2491 /*
2492 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2493 * IOMMU see for that device
2494 */
2495 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2496 get_order(alias_table_size));
2497 if (amd_iommu_alias_table == NULL)
2498 goto out;
2499
2500 /* IOMMU rlookup table - find the IOMMU for a specific device */
2501 amd_iommu_rlookup_table = (void *)__get_free_pages(
2502 GFP_KERNEL | __GFP_ZERO,
2503 get_order(rlookup_table_size));
2504 if (amd_iommu_rlookup_table == NULL)
2505 goto out;
2506
2507 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2508 GFP_KERNEL | __GFP_ZERO,
2509 get_order(MAX_DOMAIN_ID/8));
2510 if (amd_iommu_pd_alloc_bitmap == NULL)
2511 goto out;
2512
2513 /*
2514 * let all alias entries point to itself
2515 */
2516 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2517 amd_iommu_alias_table[i] = i;
2518
2519 /*
2520 * never allocate domain 0 because its used as the non-allocated and
2521 * error value placeholder
2522 */
2523 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2524
2525 spin_lock_init(&amd_iommu_pd_lock);
2526
2527 /*
2528 * now the data structures are allocated and basically initialized
2529 * start the real acpi table scan
2530 */
2531 ret = init_iommu_all(ivrs_base);
2532 if (ret)
2533 goto out;
2534
2535 /* Disable any previously enabled IOMMUs */
2536 if (!is_kdump_kernel() || amd_iommu_disabled)
2537 disable_iommus();
2538
2539 if (amd_iommu_irq_remap)
2540 amd_iommu_irq_remap = check_ioapic_information();
2541
2542 if (amd_iommu_irq_remap) {
2543 /*
2544 * Interrupt remapping enabled, create kmem_cache for the
2545 * remapping tables.
2546 */
2547 ret = -ENOMEM;
2548 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2549 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2550 else
2551 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2552 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2553 remap_cache_sz,
2554 IRQ_TABLE_ALIGNMENT,
2555 0, NULL);
2556 if (!amd_iommu_irq_cache)
2557 goto out;
2558
2559 irq_lookup_table = (void *)__get_free_pages(
2560 GFP_KERNEL | __GFP_ZERO,
2561 get_order(rlookup_table_size));
2562 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2563 1, GFP_KERNEL);
2564 if (!irq_lookup_table)
2565 goto out;
2566 }
2567
2568 ret = init_memory_definitions(ivrs_base);
2569 if (ret)
2570 goto out;
2571
2572 /* init the device table */
2573 init_device_table();
2574
2575 out:
2576 /* Don't leak any ACPI memory */
2577 acpi_put_table(ivrs_base);
2578 ivrs_base = NULL;
2579
2580 return ret;
2581 }
2582
2583 static int amd_iommu_enable_interrupts(void)
2584 {
2585 struct amd_iommu *iommu;
2586 int ret = 0;
2587
2588 for_each_iommu(iommu) {
2589 ret = iommu_init_msi(iommu);
2590 if (ret)
2591 goto out;
2592 }
2593
2594 out:
2595 return ret;
2596 }
2597
2598 static bool detect_ivrs(void)
2599 {
2600 struct acpi_table_header *ivrs_base;
2601 acpi_status status;
2602
2603 status = acpi_get_table("IVRS", 0, &ivrs_base);
2604 if (status == AE_NOT_FOUND)
2605 return false;
2606 else if (ACPI_FAILURE(status)) {
2607 const char *err = acpi_format_exception(status);
2608 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2609 return false;
2610 }
2611
2612 acpi_put_table(ivrs_base);
2613
2614 /* Make sure ACS will be enabled during PCI probe */
2615 pci_request_acs();
2616
2617 return true;
2618 }
2619
2620 /****************************************************************************
2621 *
2622 * AMD IOMMU Initialization State Machine
2623 *
2624 ****************************************************************************/
2625
2626 static int __init state_next(void)
2627 {
2628 int ret = 0;
2629
2630 switch (init_state) {
2631 case IOMMU_START_STATE:
2632 if (!detect_ivrs()) {
2633 init_state = IOMMU_NOT_FOUND;
2634 ret = -ENODEV;
2635 } else {
2636 init_state = IOMMU_IVRS_DETECTED;
2637 }
2638 break;
2639 case IOMMU_IVRS_DETECTED:
2640 ret = early_amd_iommu_init();
2641 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2642 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2643 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2644 free_dma_resources();
2645 free_iommu_resources();
2646 init_state = IOMMU_CMDLINE_DISABLED;
2647 ret = -EINVAL;
2648 }
2649 break;
2650 case IOMMU_ACPI_FINISHED:
2651 early_enable_iommus();
2652 x86_platform.iommu_shutdown = disable_iommus;
2653 init_state = IOMMU_ENABLED;
2654 break;
2655 case IOMMU_ENABLED:
2656 register_syscore_ops(&amd_iommu_syscore_ops);
2657 ret = amd_iommu_init_pci();
2658 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2659 enable_iommus_v2();
2660 break;
2661 case IOMMU_PCI_INIT:
2662 ret = amd_iommu_enable_interrupts();
2663 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2664 break;
2665 case IOMMU_INTERRUPTS_EN:
2666 ret = amd_iommu_init_dma_ops();
2667 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2668 break;
2669 case IOMMU_DMA_OPS:
2670 init_state = IOMMU_INITIALIZED;
2671 break;
2672 case IOMMU_INITIALIZED:
2673 /* Nothing to do */
2674 break;
2675 case IOMMU_NOT_FOUND:
2676 case IOMMU_INIT_ERROR:
2677 case IOMMU_CMDLINE_DISABLED:
2678 /* Error states => do nothing */
2679 ret = -EINVAL;
2680 break;
2681 default:
2682 /* Unknown state */
2683 BUG();
2684 }
2685
2686 return ret;
2687 }
2688
2689 static int __init iommu_go_to_state(enum iommu_init_state state)
2690 {
2691 int ret = -EINVAL;
2692
2693 while (init_state != state) {
2694 if (init_state == IOMMU_NOT_FOUND ||
2695 init_state == IOMMU_INIT_ERROR ||
2696 init_state == IOMMU_CMDLINE_DISABLED)
2697 break;
2698 ret = state_next();
2699 }
2700
2701 return ret;
2702 }
2703
2704 #ifdef CONFIG_IRQ_REMAP
2705 int __init amd_iommu_prepare(void)
2706 {
2707 int ret;
2708
2709 amd_iommu_irq_remap = true;
2710
2711 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2712 if (ret)
2713 return ret;
2714 return amd_iommu_irq_remap ? 0 : -ENODEV;
2715 }
2716
2717 int __init amd_iommu_enable(void)
2718 {
2719 int ret;
2720
2721 ret = iommu_go_to_state(IOMMU_ENABLED);
2722 if (ret)
2723 return ret;
2724
2725 irq_remapping_enabled = 1;
2726 return amd_iommu_xt_mode;
2727 }
2728
2729 void amd_iommu_disable(void)
2730 {
2731 amd_iommu_suspend();
2732 }
2733
2734 int amd_iommu_reenable(int mode)
2735 {
2736 amd_iommu_resume();
2737
2738 return 0;
2739 }
2740
2741 int __init amd_iommu_enable_faulting(void)
2742 {
2743 /* We enable MSI later when PCI is initialized */
2744 return 0;
2745 }
2746 #endif
2747
2748 /*
2749 * This is the core init function for AMD IOMMU hardware in the system.
2750 * This function is called from the generic x86 DMA layer initialization
2751 * code.
2752 */
2753 static int __init amd_iommu_init(void)
2754 {
2755 struct amd_iommu *iommu;
2756 int ret;
2757
2758 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2759 if (ret) {
2760 free_dma_resources();
2761 if (!irq_remapping_enabled) {
2762 disable_iommus();
2763 free_iommu_resources();
2764 } else {
2765 uninit_device_table_dma();
2766 for_each_iommu(iommu)
2767 iommu_flush_all_caches(iommu);
2768 }
2769 }
2770
2771 for_each_iommu(iommu)
2772 amd_iommu_debugfs_setup(iommu);
2773
2774 return ret;
2775 }
2776
2777 static bool amd_iommu_sme_check(void)
2778 {
2779 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2780 return true;
2781
2782 /* For Fam17h, a specific level of support is required */
2783 if (boot_cpu_data.microcode >= 0x08001205)
2784 return true;
2785
2786 if ((boot_cpu_data.microcode >= 0x08001126) &&
2787 (boot_cpu_data.microcode <= 0x080011ff))
2788 return true;
2789
2790 pr_notice("AMD-Vi: IOMMU not currently supported when SME is active\n");
2791
2792 return false;
2793 }
2794
2795 /****************************************************************************
2796 *
2797 * Early detect code. This code runs at IOMMU detection time in the DMA
2798 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2799 * IOMMUs
2800 *
2801 ****************************************************************************/
2802 int __init amd_iommu_detect(void)
2803 {
2804 int ret;
2805
2806 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2807 return -ENODEV;
2808
2809 if (!amd_iommu_sme_check())
2810 return -ENODEV;
2811
2812 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2813 if (ret)
2814 return ret;
2815
2816 amd_iommu_detected = true;
2817 iommu_detected = 1;
2818 x86_init.iommu.iommu_init = amd_iommu_init;
2819
2820 return 1;
2821 }
2822
2823 /****************************************************************************
2824 *
2825 * Parsing functions for the AMD IOMMU specific kernel command line
2826 * options.
2827 *
2828 ****************************************************************************/
2829
2830 static int __init parse_amd_iommu_dump(char *str)
2831 {
2832 amd_iommu_dump = true;
2833
2834 return 1;
2835 }
2836
2837 static int __init parse_amd_iommu_intr(char *str)
2838 {
2839 for (; *str; ++str) {
2840 if (strncmp(str, "legacy", 6) == 0) {
2841 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2842 break;
2843 }
2844 if (strncmp(str, "vapic", 5) == 0) {
2845 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2846 break;
2847 }
2848 }
2849 return 1;
2850 }
2851
2852 static int __init parse_amd_iommu_options(char *str)
2853 {
2854 for (; *str; ++str) {
2855 if (strncmp(str, "fullflush", 9) == 0)
2856 amd_iommu_unmap_flush = true;
2857 if (strncmp(str, "off", 3) == 0)
2858 amd_iommu_disabled = true;
2859 if (strncmp(str, "force_isolation", 15) == 0)
2860 amd_iommu_force_isolation = true;
2861 }
2862
2863 return 1;
2864 }
2865
2866 static int __init parse_ivrs_ioapic(char *str)
2867 {
2868 unsigned int bus, dev, fn;
2869 int ret, id, i;
2870 u16 devid;
2871
2872 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2873
2874 if (ret != 4) {
2875 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2876 return 1;
2877 }
2878
2879 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2880 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2881 str);
2882 return 1;
2883 }
2884
2885 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2886
2887 cmdline_maps = true;
2888 i = early_ioapic_map_size++;
2889 early_ioapic_map[i].id = id;
2890 early_ioapic_map[i].devid = devid;
2891 early_ioapic_map[i].cmd_line = true;
2892
2893 return 1;
2894 }
2895
2896 static int __init parse_ivrs_hpet(char *str)
2897 {
2898 unsigned int bus, dev, fn;
2899 int ret, id, i;
2900 u16 devid;
2901
2902 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2903
2904 if (ret != 4) {
2905 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2906 return 1;
2907 }
2908
2909 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2910 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2911 str);
2912 return 1;
2913 }
2914
2915 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2916
2917 cmdline_maps = true;
2918 i = early_hpet_map_size++;
2919 early_hpet_map[i].id = id;
2920 early_hpet_map[i].devid = devid;
2921 early_hpet_map[i].cmd_line = true;
2922
2923 return 1;
2924 }
2925
2926 static int __init parse_ivrs_acpihid(char *str)
2927 {
2928 u32 bus, dev, fn;
2929 char *hid, *uid, *p;
2930 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2931 int ret, i;
2932
2933 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2934 if (ret != 4) {
2935 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2936 return 1;
2937 }
2938
2939 p = acpiid;
2940 hid = strsep(&p, ":");
2941 uid = p;
2942
2943 if (!hid || !(*hid) || !uid) {
2944 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2945 return 1;
2946 }
2947
2948 i = early_acpihid_map_size++;
2949 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2950 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2951 early_acpihid_map[i].devid =
2952 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2953 early_acpihid_map[i].cmd_line = true;
2954
2955 return 1;
2956 }
2957
2958 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2959 __setup("amd_iommu=", parse_amd_iommu_options);
2960 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2961 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2962 __setup("ivrs_hpet", parse_ivrs_hpet);
2963 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2964
2965 IOMMU_INIT_FINISH(amd_iommu_detect,
2966 gart_iommu_hole_init,
2967 NULL,
2968 NULL);
2969
2970 bool amd_iommu_v2_supported(void)
2971 {
2972 return amd_iommu_v2_present;
2973 }
2974 EXPORT_SYMBOL(amd_iommu_v2_supported);
2975
2976 struct amd_iommu *get_amd_iommu(unsigned int idx)
2977 {
2978 unsigned int i = 0;
2979 struct amd_iommu *iommu;
2980
2981 for_each_iommu(iommu)
2982 if (i++ == idx)
2983 return iommu;
2984 return NULL;
2985 }
2986 EXPORT_SYMBOL(get_amd_iommu);
2987
2988 /****************************************************************************
2989 *
2990 * IOMMU EFR Performance Counter support functionality. This code allows
2991 * access to the IOMMU PC functionality.
2992 *
2993 ****************************************************************************/
2994
2995 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2996 {
2997 struct amd_iommu *iommu = get_amd_iommu(idx);
2998
2999 if (iommu)
3000 return iommu->max_banks;
3001
3002 return 0;
3003 }
3004 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
3005
3006 bool amd_iommu_pc_supported(void)
3007 {
3008 return amd_iommu_pc_present;
3009 }
3010 EXPORT_SYMBOL(amd_iommu_pc_supported);
3011
3012 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
3013 {
3014 struct amd_iommu *iommu = get_amd_iommu(idx);
3015
3016 if (iommu)
3017 return iommu->max_counters;
3018
3019 return 0;
3020 }
3021 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3022
3023 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3024 u8 fxn, u64 *value, bool is_write)
3025 {
3026 u32 offset;
3027 u32 max_offset_lim;
3028
3029 /* Make sure the IOMMU PC resource is available */
3030 if (!amd_iommu_pc_present)
3031 return -ENODEV;
3032
3033 /* Check for valid iommu and pc register indexing */
3034 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3035 return -ENODEV;
3036
3037 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3038
3039 /* Limit the offset to the hw defined mmio region aperture */
3040 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3041 (iommu->max_counters << 8) | 0x28);
3042 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3043 (offset > max_offset_lim))
3044 return -EINVAL;
3045
3046 if (is_write) {
3047 u64 val = *value & GENMASK_ULL(47, 0);
3048
3049 writel((u32)val, iommu->mmio_base + offset);
3050 writel((val >> 32), iommu->mmio_base + offset + 4);
3051 } else {
3052 *value = readl(iommu->mmio_base + offset + 4);
3053 *value <<= 32;
3054 *value |= readl(iommu->mmio_base + offset);
3055 *value &= GENMASK_ULL(47, 0);
3056 }
3057
3058 return 0;
3059 }
3060
3061 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3062 {
3063 if (!iommu)
3064 return -EINVAL;
3065
3066 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3067 }
3068 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3069
3070 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3071 {
3072 if (!iommu)
3073 return -EINVAL;
3074
3075 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3076 }
3077 EXPORT_SYMBOL(amd_iommu_pc_set_reg);
Linux with added FPC-III support