Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt

   1 * USB2 ChipIdea USB controller for ci13xxx
   2
   3 Required properties:
   4 - compatible: should be one of:
   5         "fsl,imx27-usb"
   6         "lsi,zevio-usb"
   7         "qcom,ci-hdrc"
   8         "chipidea,usb2"
   9 - reg: base address and length of the registers
  10 - interrupts: interrupt for the USB controller
  11
  12 Recommended properies:
  13 - phy_type: the type of the phy connected to the core. Should be one
  14   of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
  15   property the PORTSC register won't be touched.
  16 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
  17
  18 Deprecated properties:
  19 - usb-phy:      phandle for the PHY device. Use "phys" instead.
  20 - fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
  21
  22 Optional properties:
  23 - clocks: reference to the USB clock
  24 - phys: reference to the USB PHY
  25 - phy-names: should be "usb-phy"
  26 - vbus-supply: reference to the VBUS regulator
  27 - maximum-speed: limit the maximum connection speed to "full-speed".
  28 - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
  29 - fsl,usbmisc: (FSL only) phandler of non-core register device, with one
  30   argument that indicate usb controller index
  31 - disable-over-current: (FSL only) disable over current detect
  32 - external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
  33
  34 Example:
  35
  36         usb@f7ed0000 {
  37                 compatible = "chipidea,usb2";
  38                 reg = <0xf7ed0000 0x10000>;
  39                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  40                 clocks = <&chip CLKID_USB0>;
  41                 phys = <&usb_phy0>;
  42                 phy-names = "usb-phy";
  43                 vbus-supply = <&reg_usb0_vbus>;
  44         };