perf tools: Streamline bpf examples and headers installation
[linux/fpc-iii.git] / arch / arm / mach-spear / time.c
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1 /*
2 * arch/arm/plat-spear/time.c
4 * Copyright (C) 2010 ST Microelectronics
5 * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/clk.h>
13 #include <linux/clockchips.h>
14 #include <linux/clocksource.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/time.h>
24 #include <linux/irq.h>
25 #include <asm/mach/time.h>
26 #include "generic.h"
29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
30 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
31 * they share same functional clock. Any change in one's functional clock will
32 * also affect other timer.
35 #define CLKEVT 0 /* gpt0, channel0 as clockevent */
36 #define CLKSRC 1 /* gpt0, channel1 as clocksource */
38 /* Register offsets, x is channel number */
39 #define CR(x) ((x) * 0x80 + 0x80)
40 #define IR(x) ((x) * 0x80 + 0x84)
41 #define LOAD(x) ((x) * 0x80 + 0x88)
42 #define COUNT(x) ((x) * 0x80 + 0x8C)
44 /* Reg bit definitions */
45 #define CTRL_INT_ENABLE 0x0100
46 #define CTRL_ENABLE 0x0020
47 #define CTRL_ONE_SHOT 0x0010
49 #define CTRL_PRESCALER1 0x0
50 #define CTRL_PRESCALER2 0x1
51 #define CTRL_PRESCALER4 0x2
52 #define CTRL_PRESCALER8 0x3
53 #define CTRL_PRESCALER16 0x4
54 #define CTRL_PRESCALER32 0x5
55 #define CTRL_PRESCALER64 0x6
56 #define CTRL_PRESCALER128 0x7
57 #define CTRL_PRESCALER256 0x8
59 #define INT_STATUS 0x1
62 * Minimum clocksource/clockevent timer range in seconds
64 #define SPEAR_MIN_RANGE 4
66 static __iomem void *gpt_base;
67 static struct clk *gpt_clk;
69 static int clockevent_next_event(unsigned long evt,
70 struct clock_event_device *clk_event_dev);
72 static void __init spear_clocksource_init(void)
74 u32 tick_rate;
75 u16 val;
77 /* program the prescaler (/256)*/
78 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
80 /* find out actual clock driving Timer */
81 tick_rate = clk_get_rate(gpt_clk);
82 tick_rate >>= CTRL_PRESCALER256;
84 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
86 val = readw(gpt_base + CR(CLKSRC));
87 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
88 val |= CTRL_ENABLE ;
89 writew(val, gpt_base + CR(CLKSRC));
91 /* register the clocksource */
92 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
93 200, 16, clocksource_mmio_readw_up);
96 static inline void timer_shutdown(struct clock_event_device *evt)
98 u16 val = readw(gpt_base + CR(CLKEVT));
100 /* stop the timer */
101 val &= ~CTRL_ENABLE;
102 writew(val, gpt_base + CR(CLKEVT));
105 static int spear_shutdown(struct clock_event_device *evt)
107 timer_shutdown(evt);
109 return 0;
112 static int spear_set_oneshot(struct clock_event_device *evt)
114 u16 val;
116 /* stop the timer */
117 timer_shutdown(evt);
119 val = readw(gpt_base + CR(CLKEVT));
120 val |= CTRL_ONE_SHOT;
121 writew(val, gpt_base + CR(CLKEVT));
123 return 0;
126 static int spear_set_periodic(struct clock_event_device *evt)
128 u32 period;
129 u16 val;
131 /* stop the timer */
132 timer_shutdown(evt);
134 period = clk_get_rate(gpt_clk) / HZ;
135 period >>= CTRL_PRESCALER16;
136 writew(period, gpt_base + LOAD(CLKEVT));
138 val = readw(gpt_base + CR(CLKEVT));
139 val &= ~CTRL_ONE_SHOT;
140 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
141 writew(val, gpt_base + CR(CLKEVT));
143 return 0;
146 static struct clock_event_device clkevt = {
147 .name = "tmr0",
148 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
149 .set_state_shutdown = spear_shutdown,
150 .set_state_periodic = spear_set_periodic,
151 .set_state_oneshot = spear_set_oneshot,
152 .tick_resume = spear_shutdown,
153 .set_next_event = clockevent_next_event,
154 .shift = 0, /* to be computed */
157 static int clockevent_next_event(unsigned long cycles,
158 struct clock_event_device *clk_event_dev)
160 u16 val = readw(gpt_base + CR(CLKEVT));
162 if (val & CTRL_ENABLE)
163 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
165 writew(cycles, gpt_base + LOAD(CLKEVT));
167 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
168 writew(val, gpt_base + CR(CLKEVT));
170 return 0;
173 static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
175 struct clock_event_device *evt = &clkevt;
177 writew(INT_STATUS, gpt_base + IR(CLKEVT));
179 evt->event_handler(evt);
181 return IRQ_HANDLED;
184 static struct irqaction spear_timer_irq = {
185 .name = "timer",
186 .flags = IRQF_TIMER,
187 .handler = spear_timer_interrupt
190 static void __init spear_clockevent_init(int irq)
192 u32 tick_rate;
194 /* program the prescaler */
195 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
197 tick_rate = clk_get_rate(gpt_clk);
198 tick_rate >>= CTRL_PRESCALER16;
200 clkevt.cpumask = cpumask_of(0);
202 clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
204 setup_irq(irq, &spear_timer_irq);
207 static const struct of_device_id timer_of_match[] __initconst = {
208 { .compatible = "st,spear-timer", },
209 { },
212 void __init spear_setup_of_timer(void)
214 struct device_node *np;
215 int irq, ret;
217 np = of_find_matching_node(NULL, timer_of_match);
218 if (!np) {
219 pr_err("%s: No timer passed via DT\n", __func__);
220 return;
223 irq = irq_of_parse_and_map(np, 0);
224 if (!irq) {
225 pr_err("%s: No irq passed for timer via DT\n", __func__);
226 return;
229 gpt_base = of_iomap(np, 0);
230 if (!gpt_base) {
231 pr_err("%s: of iomap failed\n", __func__);
232 return;
235 gpt_clk = clk_get_sys("gpt0", NULL);
236 if (IS_ERR(gpt_clk)) {
237 pr_err("%s:couldn't get clk for gpt\n", __func__);
238 goto err_iomap;
241 ret = clk_prepare_enable(gpt_clk);
242 if (ret < 0) {
243 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
244 goto err_prepare_enable_clk;
247 spear_clockevent_init(irq);
248 spear_clocksource_init();
250 return;
252 err_prepare_enable_clk:
253 clk_put(gpt_clk);
254 err_iomap:
255 iounmap(gpt_base);