arch/ia64/include/asm/elf.h

   1 #ifndef _ASM_IA64_ELF_H
   2 #define _ASM_IA64_ELF_H
   3
   4 /*
   5  * ELF-specific definitions.
   6  *
   7  * Copyright (C) 1998-1999, 2002-2004 Hewlett-Packard Co
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  */
  10
  11
  12 #include <asm/fpu.h>
  13 #include <asm/page.h>
  14 #include <asm/auxvec.h>
  15
  16 /*
  17  * This is used to ensure we don't load something for the wrong architecture.
  18  */
  19 #define elf_check_arch(x) ((x)->e_machine == EM_IA_64)
  20
  21 /*
  22  * These are used to set parameters in the core dumps.
  23  */
  24 #define ELF_CLASS       ELFCLASS64
  25 #define ELF_DATA        ELFDATA2LSB
  26 #define ELF_ARCH        EM_IA_64
  27
  28 #define CORE_DUMP_USE_REGSET
  29
  30 /* Least-significant four bits of ELF header's e_flags are OS-specific.  The bits are
  31    interpreted as follows by Linux: */
  32 #define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1     /* is stack (& heap) executable by default? */
  33
  34 #define ELF_EXEC_PAGESIZE       PAGE_SIZE
  35
  36 /*
  37  * This is the location that an ET_DYN program is loaded if exec'ed.
  38  * Typical use of this is to invoke "./ld.so someprog" to test out a
  39  * new version of the loader.  We need to make sure that it is out of
  40  * the way of the program that it will "exec", and that there is
  41  * sufficient room for the brk.
  42  */
  43 #define ELF_ET_DYN_BASE         (TASK_UNMAPPED_BASE + 0x800000000UL)
  44
  45 #define PT_IA_64_UNWIND         0x70000001
  46
  47 /* IA-64 relocations: */
  48 #define R_IA64_NONE             0x00    /* none */
  49 #define R_IA64_IMM14            0x21    /* symbol + addend, add imm14 */
  50 #define R_IA64_IMM22            0x22    /* symbol + addend, add imm22 */
  51 #define R_IA64_IMM64            0x23    /* symbol + addend, mov imm64 */
  52 #define R_IA64_DIR32MSB         0x24    /* symbol + addend, data4 MSB */
  53 #define R_IA64_DIR32LSB         0x25    /* symbol + addend, data4 LSB */
  54 #define R_IA64_DIR64MSB         0x26    /* symbol + addend, data8 MSB */
  55 #define R_IA64_DIR64LSB         0x27    /* symbol + addend, data8 LSB */
  56 #define R_IA64_GPREL22          0x2a    /* @gprel(sym+add), add imm22 */
  57 #define R_IA64_GPREL64I         0x2b    /* @gprel(sym+add), mov imm64 */
  58 #define R_IA64_GPREL32MSB       0x2c    /* @gprel(sym+add), data4 MSB */
  59 #define R_IA64_GPREL32LSB       0x2d    /* @gprel(sym+add), data4 LSB */
  60 #define R_IA64_GPREL64MSB       0x2e    /* @gprel(sym+add), data8 MSB */
  61 #define R_IA64_GPREL64LSB       0x2f    /* @gprel(sym+add), data8 LSB */
  62 #define R_IA64_LTOFF22          0x32    /* @ltoff(sym+add), add imm22 */
  63 #define R_IA64_LTOFF64I         0x33    /* @ltoff(sym+add), mov imm64 */
  64 #define R_IA64_PLTOFF22         0x3a    /* @pltoff(sym+add), add imm22 */
  65 #define R_IA64_PLTOFF64I        0x3b    /* @pltoff(sym+add), mov imm64 */
  66 #define R_IA64_PLTOFF64MSB      0x3e    /* @pltoff(sym+add), data8 MSB */
  67 #define R_IA64_PLTOFF64LSB      0x3f    /* @pltoff(sym+add), data8 LSB */
  68 #define R_IA64_FPTR64I          0x43    /* @fptr(sym+add), mov imm64 */
  69 #define R_IA64_FPTR32MSB        0x44    /* @fptr(sym+add), data4 MSB */
  70 #define R_IA64_FPTR32LSB        0x45    /* @fptr(sym+add), data4 LSB */
  71 #define R_IA64_FPTR64MSB        0x46    /* @fptr(sym+add), data8 MSB */
  72 #define R_IA64_FPTR64LSB        0x47    /* @fptr(sym+add), data8 LSB */
  73 #define R_IA64_PCREL60B         0x48    /* @pcrel(sym+add), brl */
  74 #define R_IA64_PCREL21B         0x49    /* @pcrel(sym+add), ptb, call */
  75 #define R_IA64_PCREL21M         0x4a    /* @pcrel(sym+add), chk.s */
  76 #define R_IA64_PCREL21F         0x4b    /* @pcrel(sym+add), fchkf */
  77 #define R_IA64_PCREL32MSB       0x4c    /* @pcrel(sym+add), data4 MSB */
  78 #define R_IA64_PCREL32LSB       0x4d    /* @pcrel(sym+add), data4 LSB */
  79 #define R_IA64_PCREL64MSB       0x4e    /* @pcrel(sym+add), data8 MSB */
  80 #define R_IA64_PCREL64LSB       0x4f    /* @pcrel(sym+add), data8 LSB */
  81 #define R_IA64_LTOFF_FPTR22     0x52    /* @ltoff(@fptr(s+a)), imm22 */
  82 #define R_IA64_LTOFF_FPTR64I    0x53    /* @ltoff(@fptr(s+a)), imm64 */
  83 #define R_IA64_LTOFF_FPTR32MSB  0x54    /* @ltoff(@fptr(s+a)), 4 MSB */
  84 #define R_IA64_LTOFF_FPTR32LSB  0x55    /* @ltoff(@fptr(s+a)), 4 LSB */
  85 #define R_IA64_LTOFF_FPTR64MSB  0x56    /* @ltoff(@fptr(s+a)), 8 MSB */
  86 #define R_IA64_LTOFF_FPTR64LSB  0x57    /* @ltoff(@fptr(s+a)), 8 LSB */
  87 #define R_IA64_SEGREL32MSB      0x5c    /* @segrel(sym+add), data4 MSB */
  88 #define R_IA64_SEGREL32LSB      0x5d    /* @segrel(sym+add), data4 LSB */
  89 #define R_IA64_SEGREL64MSB      0x5e    /* @segrel(sym+add), data8 MSB */
  90 #define R_IA64_SEGREL64LSB      0x5f    /* @segrel(sym+add), data8 LSB */
  91 #define R_IA64_SECREL32MSB      0x64    /* @secrel(sym+add), data4 MSB */
  92 #define R_IA64_SECREL32LSB      0x65    /* @secrel(sym+add), data4 LSB */
  93 #define R_IA64_SECREL64MSB      0x66    /* @secrel(sym+add), data8 MSB */
  94 #define R_IA64_SECREL64LSB      0x67    /* @secrel(sym+add), data8 LSB */
  95 #define R_IA64_REL32MSB         0x6c    /* data 4 + REL */
  96 #define R_IA64_REL32LSB         0x6d    /* data 4 + REL */
  97 #define R_IA64_REL64MSB         0x6e    /* data 8 + REL */
  98 #define R_IA64_REL64LSB         0x6f    /* data 8 + REL */
  99 #define R_IA64_LTV32MSB         0x74    /* symbol + addend, data4 MSB */
 100 #define R_IA64_LTV32LSB         0x75    /* symbol + addend, data4 LSB */
 101 #define R_IA64_LTV64MSB         0x76    /* symbol + addend, data8 MSB */
 102 #define R_IA64_LTV64LSB         0x77    /* symbol + addend, data8 LSB */
 103 #define R_IA64_PCREL21BI        0x79    /* @pcrel(sym+add), ptb, call */
 104 #define R_IA64_PCREL22          0x7a    /* @pcrel(sym+add), imm22 */
 105 #define R_IA64_PCREL64I         0x7b    /* @pcrel(sym+add), imm64 */
 106 #define R_IA64_IPLTMSB          0x80    /* dynamic reloc, imported PLT, MSB */
 107 #define R_IA64_IPLTLSB          0x81    /* dynamic reloc, imported PLT, LSB */
 108 #define R_IA64_COPY             0x84    /* dynamic reloc, data copy */
 109 #define R_IA64_SUB              0x85    /* -symbol + addend, add imm22 */
 110 #define R_IA64_LTOFF22X         0x86    /* LTOFF22, relaxable.  */
 111 #define R_IA64_LDXMOV           0x87    /* Use of LTOFF22X.  */
 112 #define R_IA64_TPREL14          0x91    /* @tprel(sym+add), add imm14 */
 113 #define R_IA64_TPREL22          0x92    /* @tprel(sym+add), add imm22 */
 114 #define R_IA64_TPREL64I         0x93    /* @tprel(sym+add), add imm64 */
 115 #define R_IA64_TPREL64MSB       0x96    /* @tprel(sym+add), data8 MSB */
 116 #define R_IA64_TPREL64LSB       0x97    /* @tprel(sym+add), data8 LSB */
 117 #define R_IA64_LTOFF_TPREL22    0x9a    /* @ltoff(@tprel(s+a)), add imm22 */
 118 #define R_IA64_DTPMOD64MSB      0xa6    /* @dtpmod(sym+add), data8 MSB */
 119 #define R_IA64_DTPMOD64LSB      0xa7    /* @dtpmod(sym+add), data8 LSB */
 120 #define R_IA64_LTOFF_DTPMOD22   0xaa    /* @ltoff(@dtpmod(s+a)), imm22 */
 121 #define R_IA64_DTPREL14         0xb1    /* @dtprel(sym+add), imm14 */
 122 #define R_IA64_DTPREL22         0xb2    /* @dtprel(sym+add), imm22 */
 123 #define R_IA64_DTPREL64I        0xb3    /* @dtprel(sym+add), imm64 */
 124 #define R_IA64_DTPREL32MSB      0xb4    /* @dtprel(sym+add), data4 MSB */
 125 #define R_IA64_DTPREL32LSB      0xb5    /* @dtprel(sym+add), data4 LSB */
 126 #define R_IA64_DTPREL64MSB      0xb6    /* @dtprel(sym+add), data8 MSB */
 127 #define R_IA64_DTPREL64LSB      0xb7    /* @dtprel(sym+add), data8 LSB */
 128 #define R_IA64_LTOFF_DTPREL22   0xba    /* @ltoff(@dtprel(s+a)), imm22 */
 129
 130 /* IA-64 specific section flags: */
 131 #define SHF_IA_64_SHORT         0x10000000      /* section near gp */
 132
 133 /*
 134  * We use (abuse?) this macro to insert the (empty) vm_area that is
 135  * used to map the register backing store.  I don't see any better
 136  * place to do this, but we should discuss this with Linus once we can
 137  * talk to him...
 138  */
 139 extern void ia64_init_addr_space (void);
 140 #define ELF_PLAT_INIT(_r, load_addr)    ia64_init_addr_space()
 141
 142 /* ELF register definitions.  This is needed for core dump support.  */
 143
 144 /*
 145  * elf_gregset_t contains the application-level state in the following order:
 146  *      r0-r31
 147  *      NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
 148  *      predicate registers (p0-p63)
 149  *      b0-b7
 150  *      ip cfm psr
 151  *      ar.rsc ar.bsp ar.bspstore ar.rnat
 152  *      ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
 153  */
 154 #define ELF_NGREG       128     /* we really need just 72 but let's leave some headroom... */
 155 #define ELF_NFPREG      128     /* f0 and f1 could be omitted, but so what... */
 156
 157 /* elf_gregset_t register offsets */
 158 #define ELF_GR_0_OFFSET     0
 159 #define ELF_NAT_OFFSET     (32 * sizeof(elf_greg_t))
 160 #define ELF_PR_OFFSET      (33 * sizeof(elf_greg_t))
 161 #define ELF_BR_0_OFFSET    (34 * sizeof(elf_greg_t))
 162 #define ELF_CR_IIP_OFFSET  (42 * sizeof(elf_greg_t))
 163 #define ELF_CFM_OFFSET     (43 * sizeof(elf_greg_t))
 164 #define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t))
 165 #define ELF_GR_OFFSET(i)   (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t))
 166 #define ELF_BR_OFFSET(i)   (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t))
 167 #define ELF_AR_RSC_OFFSET  (45 * sizeof(elf_greg_t))
 168 #define ELF_AR_BSP_OFFSET  (46 * sizeof(elf_greg_t))
 169 #define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t))
 170 #define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t))
 171 #define ELF_AR_CCV_OFFSET  (49 * sizeof(elf_greg_t))
 172 #define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t))
 173 #define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t))
 174 #define ELF_AR_PFS_OFFSET  (52 * sizeof(elf_greg_t))
 175 #define ELF_AR_LC_OFFSET   (53 * sizeof(elf_greg_t))
 176 #define ELF_AR_EC_OFFSET   (54 * sizeof(elf_greg_t))
 177 #define ELF_AR_CSD_OFFSET  (55 * sizeof(elf_greg_t))
 178 #define ELF_AR_SSD_OFFSET  (56 * sizeof(elf_greg_t))
 179 #define ELF_AR_END_OFFSET  (57 * sizeof(elf_greg_t))
 180
 181 typedef unsigned long elf_fpxregset_t;
 182
 183 typedef unsigned long elf_greg_t;
 184 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 185
 186 typedef struct ia64_fpreg elf_fpreg_t;
 187 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 188
 189
 190
 191 struct pt_regs; /* forward declaration... */
 192 extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
 193 #define ELF_CORE_COPY_REGS(_dest,_regs) ia64_elf_core_copy_regs(_regs, _dest);
 194
 195 /* This macro yields a bitmask that programs can use to figure out
 196    what instruction set this CPU supports.  */
 197 #define ELF_HWCAP       0
 198
 199 /* This macro yields a string that ld.so will use to load
 200    implementation specific libraries for optimization.  Not terribly
 201    relevant until we have real hardware to play with... */
 202 #define ELF_PLATFORM    NULL
 203
 204 #define elf_read_implies_exec(ex, executable_stack)                                     \
 205         ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
 206
 207 struct task_struct;
 208
 209 #define GATE_EHDR       ((const struct elfhdr *) GATE_ADDR)
 210
 211 /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
 212 #define ARCH_DLINFO                                                             \
 213 do {                                                                            \
 214         extern char __kernel_syscall_via_epc[];                                 \
 215         NEW_AUX_ENT(AT_SYSINFO, (unsigned long) __kernel_syscall_via_epc);      \
 216         NEW_AUX_ENT(AT_SYSINFO_EHDR, (unsigned long) GATE_EHDR);                \
 217 } while (0)
 218
 219 /*
 220  * format for entries in the Global Offset Table
 221  */
 222 struct got_entry {
 223         uint64_t val;
 224 };
 225
 226 /*
 227  * Layout of the Function Descriptor
 228  */
 229 struct fdesc {
 230         uint64_t ip;
 231         uint64_t gp;
 232 };
 233
 234 #endif /* _ASM_IA64_ELF_H */