arch/sh/include/asm/processor.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_SH_PROCESSOR_H
   3 #define __ASM_SH_PROCESSOR_H
   4
   5 #include <asm/cpu-features.h>
   6 #include <asm/segment.h>
   7 #include <asm/cache.h>
   8
   9 #ifndef __ASSEMBLY__
  10 /*
  11  *  CPU type and hardware bug flags. Kept separately for each CPU.
  12  *
  13  *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
  14  *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
  15  *  for parsing the subtype in get_cpu_subtype().
  16  */
  17 enum cpu_type {
  18         /* SH-2 types */
  19         CPU_SH7619, CPU_J2,
  20
  21         /* SH-2A types */
  22         CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
  23         CPU_MXG,
  24
  25         /* SH-3 types */
  26         CPU_SH7705, CPU_SH7706, CPU_SH7707,
  27         CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
  28         CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
  29         CPU_SH7720, CPU_SH7721, CPU_SH7729,
  30
  31         /* SH-4 types */
  32         CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
  33         CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
  34
  35         /* SH-4A types */
  36         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
  37         CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
  38
  39         /* SH4AL-DSP types */
  40         CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
  41
  42         /* SH-5 types */
  43         CPU_SH5_101, CPU_SH5_103,
  44
  45         /* Unknown subtype */
  46         CPU_SH_NONE
  47 };
  48
  49 enum cpu_family {
  50         CPU_FAMILY_SH2,
  51         CPU_FAMILY_SH2A,
  52         CPU_FAMILY_SH3,
  53         CPU_FAMILY_SH4,
  54         CPU_FAMILY_SH4A,
  55         CPU_FAMILY_SH4AL_DSP,
  56         CPU_FAMILY_SH5,
  57         CPU_FAMILY_UNKNOWN,
  58 };
  59
  60 /*
  61  * TLB information structure
  62  *
  63  * Defined for both I and D tlb, per-processor.
  64  */
  65 struct tlb_info {
  66         unsigned long long next;
  67         unsigned long long first;
  68         unsigned long long last;
  69
  70         unsigned int entries;
  71         unsigned int step;
  72
  73         unsigned long flags;
  74 };
  75
  76 struct sh_cpuinfo {
  77         unsigned int type, family;
  78         int cut_major, cut_minor;
  79         unsigned long loops_per_jiffy;
  80         unsigned long asid_cache;
  81
  82         struct cache_info icache;       /* Primary I-cache */
  83         struct cache_info dcache;       /* Primary D-cache */
  84         struct cache_info scache;       /* Secondary cache */
  85
  86         /* TLB info */
  87         struct tlb_info itlb;
  88         struct tlb_info dtlb;
  89
  90         unsigned int phys_bits;
  91         unsigned long flags;
  92 } __attribute__ ((aligned(L1_CACHE_BYTES)));
  93
  94 extern struct sh_cpuinfo cpu_data[];
  95 #define boot_cpu_data cpu_data[0]
  96 #define current_cpu_data cpu_data[smp_processor_id()]
  97 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
  98
  99 #define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
 100 #define cpu_relax()     barrier()
 101
 102 void default_idle(void);
 103 void stop_this_cpu(void *);
 104
 105 /* Forward decl */
 106 struct seq_operations;
 107 struct task_struct;
 108
 109 extern struct pt_regs fake_swapper_regs;
 110
 111 extern void cpu_init(void);
 112 extern void cpu_probe(void);
 113
 114 /* arch/sh/kernel/process.c */
 115 extern unsigned int xstate_size;
 116 extern void free_thread_xstate(struct task_struct *);
 117 extern struct kmem_cache *task_xstate_cachep;
 118
 119 /* arch/sh/mm/alignment.c */
 120 extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
 121 extern int set_unalign_ctl(struct task_struct *, unsigned int val);
 122
 123 #define GET_UNALIGN_CTL(tsk, addr)      get_unalign_ctl((tsk), (addr))
 124 #define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 125
 126 /* arch/sh/mm/init.c */
 127 extern unsigned int mem_init_done;
 128
 129 /* arch/sh/kernel/setup.c */
 130 const char *get_cpu_subtype(struct sh_cpuinfo *c);
 131 extern const struct seq_operations cpuinfo_op;
 132
 133 /* thread_struct flags */
 134 #define SH_THREAD_UAC_NOPRINT   (1 << 0)
 135 #define SH_THREAD_UAC_SIGBUS    (1 << 1)
 136 #define SH_THREAD_UAC_MASK      (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
 137
 138 /* processor boot mode configuration */
 139 #define MODE_PIN0 (1 << 0)
 140 #define MODE_PIN1 (1 << 1)
 141 #define MODE_PIN2 (1 << 2)
 142 #define MODE_PIN3 (1 << 3)
 143 #define MODE_PIN4 (1 << 4)
 144 #define MODE_PIN5 (1 << 5)
 145 #define MODE_PIN6 (1 << 6)
 146 #define MODE_PIN7 (1 << 7)
 147 #define MODE_PIN8 (1 << 8)
 148 #define MODE_PIN9 (1 << 9)
 149 #define MODE_PIN10 (1 << 10)
 150 #define MODE_PIN11 (1 << 11)
 151 #define MODE_PIN12 (1 << 12)
 152 #define MODE_PIN13 (1 << 13)
 153 #define MODE_PIN14 (1 << 14)
 154 #define MODE_PIN15 (1 << 15)
 155
 156 int generic_mode_pins(void);
 157 int test_mode_pin(int pin);
 158
 159 #ifdef CONFIG_VSYSCALL
 160 int vsyscall_init(void);
 161 #else
 162 #define vsyscall_init() do { } while (0)
 163 #endif
 164
 165 /*
 166  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
 167  */
 168 #ifdef CONFIG_CPU_SH2A
 169 extern unsigned int instruction_size(unsigned int insn);
 170 #elif defined(CONFIG_SUPERH32)
 171 #define instruction_size(insn)  (2)
 172 #else
 173 #define instruction_size(insn)  (4)
 174 #endif
 175
 176 #endif /* __ASSEMBLY__ */
 177
 178 #ifdef CONFIG_SUPERH32
 179 # include <asm/processor_32.h>
 180 #else
 181 # include <asm/processor_64.h>
 182 #endif
 183
 184 #endif /* __ASM_SH_PROCESSOR_H */