arch/sh/include/asm/watchdog.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  * include/asm-sh/watchdog.h
   4  *
   5  * Copyright (C) 2002, 2003 Paul Mundt
   6  * Copyright (C) 2009 Siemens AG
   7  * Copyright (C) 2009 Valentin Sitdikov
   8  */
   9 #ifndef __ASM_SH_WATCHDOG_H
  10 #define __ASM_SH_WATCHDOG_H
  11 #ifdef __KERNEL__
  12
  13 #include <linux/types.h>
  14 #include <linux/io.h>
  15
  16 #define WTCNT_HIGH      0x5a
  17 #define WTCSR_HIGH      0xa5
  18
  19 #define WTCSR_CKS2      0x04
  20 #define WTCSR_CKS1      0x02
  21 #define WTCSR_CKS0      0x01
  22
  23 #include <cpu/watchdog.h>
  24
  25 /*
  26  * See cpu-sh2/watchdog.h for explanation of this stupidity..
  27  */
  28 #ifndef WTCNT_R
  29 #  define WTCNT_R       WTCNT
  30 #endif
  31
  32 #ifndef WTCSR_R
  33 #  define WTCSR_R       WTCSR
  34 #endif
  35
  36 /*
  37  * CKS0-2 supports a number of clock division ratios. At the time the watchdog
  38  * is enabled, it defaults to a 41 usec overflow period .. we overload this to
  39  * something a little more reasonable, and really can't deal with anything
  40  * lower than WTCSR_CKS_1024, else we drop back into the usec range.
  41  *
  42  * Clock Division Ratio         Overflow Period
  43  * --------------------------------------------
  44  *     1/32 (initial value)       41 usecs
  45  *     1/64                       82 usecs
  46  *     1/128                     164 usecs
  47  *     1/256                     328 usecs
  48  *     1/512                     656 usecs
  49  *     1/1024                   1.31 msecs
  50  *     1/2048                   2.62 msecs
  51  *     1/4096                   5.25 msecs
  52  */
  53 #define WTCSR_CKS_32    0x00
  54 #define WTCSR_CKS_64    0x01
  55 #define WTCSR_CKS_128   0x02
  56 #define WTCSR_CKS_256   0x03
  57 #define WTCSR_CKS_512   0x04
  58 #define WTCSR_CKS_1024  0x05
  59 #define WTCSR_CKS_2048  0x06
  60 #define WTCSR_CKS_4096  0x07
  61
  62 #if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
  63 /**
  64  *      sh_wdt_read_cnt - Read from Counter
  65  *      Reads back the WTCNT value.
  66  */
  67 static inline __u32 sh_wdt_read_cnt(void)
  68 {
  69         return __raw_readl(WTCNT_R);
  70 }
  71
  72 /**
  73  *      sh_wdt_write_cnt - Write to Counter
  74  *      @val: Value to write
  75  *
  76  *      Writes the given value @val to the lower byte of the timer counter.
  77  *      The upper byte is set manually on each write.
  78  */
  79 static inline void sh_wdt_write_cnt(__u32 val)
  80 {
  81         __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
  82 }
  83
  84 /**
  85  *      sh_wdt_write_bst - Write to Counter
  86  *      @val: Value to write
  87  *
  88  *      Writes the given value @val to the lower byte of the timer counter.
  89  *      The upper byte is set manually on each write.
  90  */
  91 static inline void sh_wdt_write_bst(__u32 val)
  92 {
  93         __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
  94 }
  95 /**
  96  *      sh_wdt_read_csr - Read from Control/Status Register
  97  *
  98  *      Reads back the WTCSR value.
  99  */
 100 static inline __u32 sh_wdt_read_csr(void)
 101 {
 102         return __raw_readl(WTCSR_R);
 103 }
 104
 105 /**
 106  *      sh_wdt_write_csr - Write to Control/Status Register
 107  *      @val: Value to write
 108  *
 109  *      Writes the given value @val to the lower byte of the control/status
 110  *      register. The upper byte is set manually on each write.
 111  */
 112 static inline void sh_wdt_write_csr(__u32 val)
 113 {
 114         __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
 115 }
 116 #else
 117 /**
 118  *      sh_wdt_read_cnt - Read from Counter
 119  *      Reads back the WTCNT value.
 120  */
 121 static inline __u8 sh_wdt_read_cnt(void)
 122 {
 123         return __raw_readb(WTCNT_R);
 124 }
 125
 126 /**
 127  *      sh_wdt_write_cnt - Write to Counter
 128  *      @val: Value to write
 129  *
 130  *      Writes the given value @val to the lower byte of the timer counter.
 131  *      The upper byte is set manually on each write.
 132  */
 133 static inline void sh_wdt_write_cnt(__u8 val)
 134 {
 135         __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
 136 }
 137
 138 /**
 139  *      sh_wdt_read_csr - Read from Control/Status Register
 140  *
 141  *      Reads back the WTCSR value.
 142  */
 143 static inline __u8 sh_wdt_read_csr(void)
 144 {
 145         return __raw_readb(WTCSR_R);
 146 }
 147
 148 /**
 149  *      sh_wdt_write_csr - Write to Control/Status Register
 150  *      @val: Value to write
 151  *
 152  *      Writes the given value @val to the lower byte of the control/status
 153  *      register. The upper byte is set manually on each write.
 154  */
 155 static inline void sh_wdt_write_csr(__u8 val)
 156 {
 157         __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
 158 }
 159 #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
 160 #endif /* __KERNEL__ */
 161 #endif /* __ASM_SH_WATCHDOG_H */