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drm/panfrost: Move gpu_{write, read}() macros to panfrost_regs.h
[linux/fpc-iii.git] / drivers / soc / tegra / pmc.c
blob5648e5c09ef5476a92d5ed2613c20b9b9777a348
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #define pr_fmt(fmt) "tegra-pmc: " fmt
22
23 #include <linux/arm-smccc.h>
24 #include <linux/clk.h>
25 #include <linux/clk/tegra.h>
26 #include <linux/debugfs.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/export.h>
30 #include <linux/init.h>
31 #include <linux/io.h>
32 #include <linux/iopoll.h>
33 #include <linux/irqdomain.h>
34 #include <linux/irq.h>
35 #include <linux/kernel.h>
36 #include <linux/of_address.h>
37 #include <linux/of_clk.h>
38 #include <linux/of.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_platform.h>
41 #include <linux/pinctrl/pinconf-generic.h>
42 #include <linux/pinctrl/pinconf.h>
43 #include <linux/pinctrl/pinctrl.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_domain.h>
46 #include <linux/reboot.h>
47 #include <linux/reset.h>
48 #include <linux/seq_file.h>
49 #include <linux/slab.h>
50 #include <linux/spinlock.h>
51
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
54 #include <soc/tegra/pmc.h>
55
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60
61 #define PMC_CNTRL 0x0
62 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
63 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
64 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
65 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
66 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
67 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
68 #define PMC_CNTRL_MAIN_RST BIT(4)
69
70 #define DPD_SAMPLE 0x020
71 #define DPD_SAMPLE_ENABLE BIT(0)
72 #define DPD_SAMPLE_DISABLE (0 << 0)
73
74 #define PWRGATE_TOGGLE 0x30
75 #define PWRGATE_TOGGLE_START BIT(8)
76
77 #define REMOVE_CLAMPING 0x34
78
79 #define PWRGATE_STATUS 0x38
80
81 #define PMC_IMPL_E_33V_PWR 0x40
82
83 #define PMC_PWR_DET 0x48
84
85 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
86 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
87 #define PMC_SCRATCH0_MODE_RCM BIT(1)
88 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
89 PMC_SCRATCH0_MODE_BOOTLOADER | \
90 PMC_SCRATCH0_MODE_RCM)
91
92 #define PMC_CPUPWRGOOD_TIMER 0xc8
93 #define PMC_CPUPWROFF_TIMER 0xcc
94
95 #define PMC_PWR_DET_VALUE 0xe4
96
97 #define PMC_SCRATCH41 0x140
98
99 #define PMC_SENSOR_CTRL 0x1b0
100 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
101 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
102
103 #define PMC_RST_STATUS_POR 0
104 #define PMC_RST_STATUS_WATCHDOG 1
105 #define PMC_RST_STATUS_SENSOR 2
106 #define PMC_RST_STATUS_SW_MAIN 3
107 #define PMC_RST_STATUS_LP0 4
108 #define PMC_RST_STATUS_AOTAG 5
109
110 #define IO_DPD_REQ 0x1b8
111 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
112 #define IO_DPD_REQ_CODE_OFF (1U << 30)
113 #define IO_DPD_REQ_CODE_ON (2U << 30)
114 #define IO_DPD_REQ_CODE_MASK (3U << 30)
115
116 #define IO_DPD_STATUS 0x1bc
117 #define IO_DPD2_REQ 0x1c0
118 #define IO_DPD2_STATUS 0x1c4
119 #define SEL_DPD_TIM 0x1c8
120
121 #define PMC_SCRATCH54 0x258
122 #define PMC_SCRATCH54_DATA_SHIFT 8
123 #define PMC_SCRATCH54_ADDR_SHIFT 0
124
125 #define PMC_SCRATCH55 0x25c
126 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
127 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
128 #define PMC_SCRATCH55_PINMUX_SHIFT 24
129 #define PMC_SCRATCH55_16BITOP BIT(15)
130 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
131 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
132
133 #define GPU_RG_CNTRL 0x2d4
134
135 /* Tegra186 and later */
136 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
137 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
138 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
139 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
140 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
141 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
142 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
143 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
144 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
145
146 #define WAKE_AOWAKE_CTRL 0x4f4
147 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
148
149 /* for secure PMC */
150 #define TEGRA_SMC_PMC 0xc2fffe00
151 #define TEGRA_SMC_PMC_READ 0xaa
152 #define TEGRA_SMC_PMC_WRITE 0xbb
153
154 struct tegra_powergate {
155 struct generic_pm_domain genpd;
156 struct tegra_pmc *pmc;
157 unsigned int id;
158 struct clk **clks;
159 unsigned int num_clks;
160 struct reset_control *reset;
161 };
162
163 struct tegra_io_pad_soc {
164 enum tegra_io_pad id;
165 unsigned int dpd;
166 unsigned int voltage;
167 const char *name;
168 };
169
170 struct tegra_pmc_regs {
171 unsigned int scratch0;
172 unsigned int dpd_req;
173 unsigned int dpd_status;
174 unsigned int dpd2_req;
175 unsigned int dpd2_status;
176 unsigned int rst_status;
177 unsigned int rst_source_shift;
178 unsigned int rst_source_mask;
179 unsigned int rst_level_shift;
180 unsigned int rst_level_mask;
181 };
182
183 struct tegra_wake_event {
184 const char *name;
185 unsigned int id;
186 unsigned int irq;
187 struct {
188 unsigned int instance;
189 unsigned int pin;
190 } gpio;
191 };
192
193 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
194 { \
195 .name = _name, \
196 .id = _id, \
197 .irq = _irq, \
198 .gpio = { \
199 .instance = UINT_MAX, \
200 .pin = UINT_MAX, \
201 }, \
202 }
203
204 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
205 { \
206 .name = _name, \
207 .id = _id, \
208 .irq = 0, \
209 .gpio = { \
210 .instance = _instance, \
211 .pin = _pin, \
212 }, \
213 }
214
215 struct tegra_pmc_soc {
216 unsigned int num_powergates;
217 const char *const *powergates;
218 unsigned int num_cpu_powergates;
219 const u8 *cpu_powergates;
220
221 bool has_tsense_reset;
222 bool has_gpu_clamps;
223 bool needs_mbist_war;
224 bool has_impl_33v_pwr;
225 bool maybe_tz_only;
226
227 const struct tegra_io_pad_soc *io_pads;
228 unsigned int num_io_pads;
229
230 const struct pinctrl_pin_desc *pin_descs;
231 unsigned int num_pin_descs;
232
233 const struct tegra_pmc_regs *regs;
234 void (*init)(struct tegra_pmc *pmc);
235 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
236 struct device_node *np,
237 bool invert);
238
239 const char * const *reset_sources;
240 unsigned int num_reset_sources;
241 const char * const *reset_levels;
242 unsigned int num_reset_levels;
243
244 const struct tegra_wake_event *wake_events;
245 unsigned int num_wake_events;
246 };
247
248 static const char * const tegra186_reset_sources[] = {
249 "SYS_RESET",
250 "AOWDT",
251 "MCCPLEXWDT",
252 "BPMPWDT",
253 "SCEWDT",
254 "SPEWDT",
255 "APEWDT",
256 "BCCPLEXWDT",
257 "SENSOR",
258 "AOTAG",
259 "VFSENSOR",
260 "SWREST",
261 "SC7",
262 "HSM",
263 "CORESIGHT"
264 };
265
266 static const char * const tegra186_reset_levels[] = {
267 "L0", "L1", "L2", "WARM"
268 };
269
270 static const char * const tegra30_reset_sources[] = {
271 "POWER_ON_RESET",
272 "WATCHDOG",
273 "SENSOR",
274 "SW_MAIN",
275 "LP0"
276 };
277
278 static const char * const tegra210_reset_sources[] = {
279 "POWER_ON_RESET",
280 "WATCHDOG",
281 "SENSOR",
282 "SW_MAIN",
283 "LP0",
284 "AOTAG"
285 };
286
287 /**
288 * struct tegra_pmc - NVIDIA Tegra PMC
289 * @dev: pointer to PMC device structure
290 * @base: pointer to I/O remapped register region
291 * @wake: pointer to I/O remapped region for WAKE registers
292 * @aotag: pointer to I/O remapped region for AOTAG registers
293 * @scratch: pointer to I/O remapped region for scratch registers
294 * @clk: pointer to pclk clock
295 * @soc: pointer to SoC data structure
296 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
297 * @debugfs: pointer to debugfs entry
298 * @rate: currently configured rate of pclk
299 * @suspend_mode: lowest suspend mode available
300 * @cpu_good_time: CPU power good time (in microseconds)
301 * @cpu_off_time: CPU power off time (in microsecends)
302 * @core_osc_time: core power good OSC time (in microseconds)
303 * @core_pmu_time: core power good PMU time (in microseconds)
304 * @core_off_time: core power off time (in microseconds)
305 * @corereq_high: core power request is active-high
306 * @sysclkreq_high: system clock request is active-high
307 * @combined_req: combined power request for CPU & core
308 * @cpu_pwr_good_en: CPU power good signal is enabled
309 * @lp0_vec_phys: physical base address of the LP0 warm boot code
310 * @lp0_vec_size: size of the LP0 warm boot code
311 * @powergates_available: Bitmap of available power gates
312 * @powergates_lock: mutex for power gate register access
313 * @pctl_dev: pin controller exposed by the PMC
314 * @domain: IRQ domain provided by the PMC
315 * @irq: chip implementation for the IRQ domain
316 */
317 struct tegra_pmc {
318 struct device *dev;
319 void __iomem *base;
320 void __iomem *wake;
321 void __iomem *aotag;
322 void __iomem *scratch;
323 struct clk *clk;
324 struct dentry *debugfs;
325
326 const struct tegra_pmc_soc *soc;
327 bool tz_only;
328
329 unsigned long rate;
330
331 enum tegra_suspend_mode suspend_mode;
332 u32 cpu_good_time;
333 u32 cpu_off_time;
334 u32 core_osc_time;
335 u32 core_pmu_time;
336 u32 core_off_time;
337 bool corereq_high;
338 bool sysclkreq_high;
339 bool combined_req;
340 bool cpu_pwr_good_en;
341 u32 lp0_vec_phys;
342 u32 lp0_vec_size;
343 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
344
345 struct mutex powergates_lock;
346
347 struct pinctrl_dev *pctl_dev;
348
349 struct irq_domain *domain;
350 struct irq_chip irq;
351 };
352
353 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
354 .base = NULL,
355 .suspend_mode = TEGRA_SUSPEND_NONE,
356 };
357
358 static inline struct tegra_powergate *
359 to_powergate(struct generic_pm_domain *domain)
360 {
361 return container_of(domain, struct tegra_powergate, genpd);
362 }
363
364 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
365 {
366 struct arm_smccc_res res;
367
368 if (pmc->tz_only) {
369 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
370 0, 0, 0, &res);
371 if (res.a0) {
372 if (pmc->dev)
373 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
374 __func__, res.a0);
375 else
376 pr_warn("%s(): SMC failed: %lu\n", __func__,
377 res.a0);
378 }
379
380 return res.a1;
381 }
382
383 return readl(pmc->base + offset);
384 }
385
386 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
387 unsigned long offset)
388 {
389 struct arm_smccc_res res;
390
391 if (pmc->tz_only) {
392 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
393 value, 0, 0, 0, 0, &res);
394 if (res.a0) {
395 if (pmc->dev)
396 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
397 __func__, res.a0);
398 else
399 pr_warn("%s(): SMC failed: %lu\n", __func__,
400 res.a0);
401 }
402 } else {
403 writel(value, pmc->base + offset);
404 }
405 }
406
407 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
408 {
409 if (pmc->tz_only)
410 return tegra_pmc_readl(pmc, offset);
411
412 return readl(pmc->scratch + offset);
413 }
414
415 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
416 unsigned long offset)
417 {
418 if (pmc->tz_only)
419 tegra_pmc_writel(pmc, value, offset);
420 else
421 writel(value, pmc->scratch + offset);
422 }
423
424 /*
425 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
426 * This currently doesn't work because readx_poll_timeout() can only operate
427 * on functions that take a single argument.
428 */
429 static inline bool tegra_powergate_state(int id)
430 {
431 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
432 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
433 else
434 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
435 }
436
437 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
438 {
439 return (pmc->soc && pmc->soc->powergates[id]);
440 }
441
442 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
443 {
444 return test_bit(id, pmc->powergates_available);
445 }
446
447 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
448 {
449 unsigned int i;
450
451 if (!pmc || !pmc->soc || !name)
452 return -EINVAL;
453
454 for (i = 0; i < pmc->soc->num_powergates; i++) {
455 if (!tegra_powergate_is_valid(pmc, i))
456 continue;
457
458 if (!strcmp(name, pmc->soc->powergates[i]))
459 return i;
460 }
461
462 return -ENODEV;
463 }
464
465 /**
466 * tegra_powergate_set() - set the state of a partition
467 * @pmc: power management controller
468 * @id: partition ID
469 * @new_state: new state of the partition
470 */
471 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
472 bool new_state)
473 {
474 bool status;
475 int err;
476
477 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
478 return -EINVAL;
479
480 mutex_lock(&pmc->powergates_lock);
481
482 if (tegra_powergate_state(id) == new_state) {
483 mutex_unlock(&pmc->powergates_lock);
484 return 0;
485 }
486
487 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
488
489 err = readx_poll_timeout(tegra_powergate_state, id, status,
490 status == new_state, 10, 100000);
491
492 mutex_unlock(&pmc->powergates_lock);
493
494 return err;
495 }
496
497 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
498 unsigned int id)
499 {
500 u32 mask;
501
502 mutex_lock(&pmc->powergates_lock);
503
504 /*
505 * On Tegra124 and later, the clamps for the GPU are controlled by a
506 * separate register (with different semantics).
507 */
508 if (id == TEGRA_POWERGATE_3D) {
509 if (pmc->soc->has_gpu_clamps) {
510 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
511 goto out;
512 }
513 }
514
515 /*
516 * Tegra 2 has a bug where PCIE and VDE clamping masks are
517 * swapped relatively to the partition ids
518 */
519 if (id == TEGRA_POWERGATE_VDEC)
520 mask = (1 << TEGRA_POWERGATE_PCIE);
521 else if (id == TEGRA_POWERGATE_PCIE)
522 mask = (1 << TEGRA_POWERGATE_VDEC);
523 else
524 mask = (1 << id);
525
526 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
527
528 out:
529 mutex_unlock(&pmc->powergates_lock);
530
531 return 0;
532 }
533
534 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
535 {
536 unsigned int i;
537
538 for (i = 0; i < pg->num_clks; i++)
539 clk_disable_unprepare(pg->clks[i]);
540 }
541
542 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
543 {
544 unsigned int i;
545 int err;
546
547 for (i = 0; i < pg->num_clks; i++) {
548 err = clk_prepare_enable(pg->clks[i]);
549 if (err)
550 goto out;
551 }
552
553 return 0;
554
555 out:
556 while (i--)
557 clk_disable_unprepare(pg->clks[i]);
558
559 return err;
560 }
561
562 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
563 {
564 return 0;
565 }
566
567 static int tegra_powergate_power_up(struct tegra_powergate *pg,
568 bool disable_clocks)
569 {
570 int err;
571
572 err = reset_control_assert(pg->reset);
573 if (err)
574 return err;
575
576 usleep_range(10, 20);
577
578 err = tegra_powergate_set(pg->pmc, pg->id, true);
579 if (err < 0)
580 return err;
581
582 usleep_range(10, 20);
583
584 err = tegra_powergate_enable_clocks(pg);
585 if (err)
586 goto disable_clks;
587
588 usleep_range(10, 20);
589
590 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
591 if (err)
592 goto disable_clks;
593
594 usleep_range(10, 20);
595
596 err = reset_control_deassert(pg->reset);
597 if (err)
598 goto powergate_off;
599
600 usleep_range(10, 20);
601
602 if (pg->pmc->soc->needs_mbist_war)
603 err = tegra210_clk_handle_mbist_war(pg->id);
604 if (err)
605 goto disable_clks;
606
607 if (disable_clocks)
608 tegra_powergate_disable_clocks(pg);
609
610 return 0;
611
612 disable_clks:
613 tegra_powergate_disable_clocks(pg);
614 usleep_range(10, 20);
615
616 powergate_off:
617 tegra_powergate_set(pg->pmc, pg->id, false);
618
619 return err;
620 }
621
622 static int tegra_powergate_power_down(struct tegra_powergate *pg)
623 {
624 int err;
625
626 err = tegra_powergate_enable_clocks(pg);
627 if (err)
628 return err;
629
630 usleep_range(10, 20);
631
632 err = reset_control_assert(pg->reset);
633 if (err)
634 goto disable_clks;
635
636 usleep_range(10, 20);
637
638 tegra_powergate_disable_clocks(pg);
639
640 usleep_range(10, 20);
641
642 err = tegra_powergate_set(pg->pmc, pg->id, false);
643 if (err)
644 goto assert_resets;
645
646 return 0;
647
648 assert_resets:
649 tegra_powergate_enable_clocks(pg);
650 usleep_range(10, 20);
651 reset_control_deassert(pg->reset);
652 usleep_range(10, 20);
653
654 disable_clks:
655 tegra_powergate_disable_clocks(pg);
656
657 return err;
658 }
659
660 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
661 {
662 struct tegra_powergate *pg = to_powergate(domain);
663 struct device *dev = pg->pmc->dev;
664 int err;
665
666 err = tegra_powergate_power_up(pg, true);
667 if (err) {
668 dev_err(dev, "failed to turn on PM domain %s: %d\n",
669 pg->genpd.name, err);
670 goto out;
671 }
672
673 reset_control_release(pg->reset);
674
675 out:
676 return err;
677 }
678
679 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
680 {
681 struct tegra_powergate *pg = to_powergate(domain);
682 struct device *dev = pg->pmc->dev;
683 int err;
684
685 err = reset_control_acquire(pg->reset);
686 if (err < 0) {
687 pr_err("failed to acquire resets: %d\n", err);
688 return err;
689 }
690
691 err = tegra_powergate_power_down(pg);
692 if (err) {
693 dev_err(dev, "failed to turn off PM domain %s: %d\n",
694 pg->genpd.name, err);
695 reset_control_release(pg->reset);
696 }
697
698 return err;
699 }
700
701 /**
702 * tegra_powergate_power_on() - power on partition
703 * @id: partition ID
704 */
705 int tegra_powergate_power_on(unsigned int id)
706 {
707 if (!tegra_powergate_is_available(pmc, id))
708 return -EINVAL;
709
710 return tegra_powergate_set(pmc, id, true);
711 }
712
713 /**
714 * tegra_powergate_power_off() - power off partition
715 * @id: partition ID
716 */
717 int tegra_powergate_power_off(unsigned int id)
718 {
719 if (!tegra_powergate_is_available(pmc, id))
720 return -EINVAL;
721
722 return tegra_powergate_set(pmc, id, false);
723 }
724 EXPORT_SYMBOL(tegra_powergate_power_off);
725
726 /**
727 * tegra_powergate_is_powered() - check if partition is powered
728 * @pmc: power management controller
729 * @id: partition ID
730 */
731 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
732 {
733 if (!tegra_powergate_is_valid(pmc, id))
734 return -EINVAL;
735
736 return tegra_powergate_state(id);
737 }
738
739 /**
740 * tegra_powergate_remove_clamping() - remove power clamps for partition
741 * @id: partition ID
742 */
743 int tegra_powergate_remove_clamping(unsigned int id)
744 {
745 if (!tegra_powergate_is_available(pmc, id))
746 return -EINVAL;
747
748 return __tegra_powergate_remove_clamping(pmc, id);
749 }
750 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
751
752 /**
753 * tegra_powergate_sequence_power_up() - power up partition
754 * @id: partition ID
755 * @clk: clock for partition
756 * @rst: reset for partition
757 *
758 * Must be called with clk disabled, and returns with clk enabled.
759 */
760 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
761 struct reset_control *rst)
762 {
763 struct tegra_powergate *pg;
764 int err;
765
766 if (!tegra_powergate_is_available(pmc, id))
767 return -EINVAL;
768
769 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
770 if (!pg)
771 return -ENOMEM;
772
773 pg->id = id;
774 pg->clks = &clk;
775 pg->num_clks = 1;
776 pg->reset = rst;
777 pg->pmc = pmc;
778
779 err = tegra_powergate_power_up(pg, false);
780 if (err)
781 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
782 err);
783
784 kfree(pg);
785
786 return err;
787 }
788 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
789
790 /**
791 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
792 * @pmc: power management controller
793 * @cpuid: CPU partition ID
794 *
795 * Returns the partition ID corresponding to the CPU partition ID or a
796 * negative error code on failure.
797 */
798 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
799 unsigned int cpuid)
800 {
801 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
802 return pmc->soc->cpu_powergates[cpuid];
803
804 return -EINVAL;
805 }
806
807 /**
808 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
809 * @cpuid: CPU partition ID
810 */
811 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
812 {
813 int id;
814
815 id = tegra_get_cpu_powergate_id(pmc, cpuid);
816 if (id < 0)
817 return false;
818
819 return tegra_powergate_is_powered(pmc, id);
820 }
821
822 /**
823 * tegra_pmc_cpu_power_on() - power on CPU partition
824 * @cpuid: CPU partition ID
825 */
826 int tegra_pmc_cpu_power_on(unsigned int cpuid)
827 {
828 int id;
829
830 id = tegra_get_cpu_powergate_id(pmc, cpuid);
831 if (id < 0)
832 return id;
833
834 return tegra_powergate_set(pmc, id, true);
835 }
836
837 /**
838 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
839 * @cpuid: CPU partition ID
840 */
841 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
842 {
843 int id;
844
845 id = tegra_get_cpu_powergate_id(pmc, cpuid);
846 if (id < 0)
847 return id;
848
849 return tegra_powergate_remove_clamping(id);
850 }
851
852 static int tegra_pmc_restart_notify(struct notifier_block *this,
853 unsigned long action, void *data)
854 {
855 const char *cmd = data;
856 u32 value;
857
858 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
859 value &= ~PMC_SCRATCH0_MODE_MASK;
860
861 if (cmd) {
862 if (strcmp(cmd, "recovery") == 0)
863 value |= PMC_SCRATCH0_MODE_RECOVERY;
864
865 if (strcmp(cmd, "bootloader") == 0)
866 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
867
868 if (strcmp(cmd, "forced-recovery") == 0)
869 value |= PMC_SCRATCH0_MODE_RCM;
870 }
871
872 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
873
874 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
875 value = tegra_pmc_readl(pmc, PMC_CNTRL);
876 value |= PMC_CNTRL_MAIN_RST;
877 tegra_pmc_writel(pmc, value, PMC_CNTRL);
878
879 return NOTIFY_DONE;
880 }
881
882 static struct notifier_block tegra_pmc_restart_handler = {
883 .notifier_call = tegra_pmc_restart_notify,
884 .priority = 128,
885 };
886
887 static int powergate_show(struct seq_file *s, void *data)
888 {
889 unsigned int i;
890 int status;
891
892 seq_printf(s, " powergate powered\n");
893 seq_printf(s, "------------------\n");
894
895 for (i = 0; i < pmc->soc->num_powergates; i++) {
896 status = tegra_powergate_is_powered(pmc, i);
897 if (status < 0)
898 continue;
899
900 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
901 status ? "yes" : "no");
902 }
903
904 return 0;
905 }
906
907 DEFINE_SHOW_ATTRIBUTE(powergate);
908
909 static int tegra_powergate_debugfs_init(void)
910 {
911 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
912 &powergate_fops);
913 if (!pmc->debugfs)
914 return -ENOMEM;
915
916 return 0;
917 }
918
919 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
920 struct device_node *np)
921 {
922 struct clk *clk;
923 unsigned int i, count;
924 int err;
925
926 count = of_clk_get_parent_count(np);
927 if (count == 0)
928 return -ENODEV;
929
930 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
931 if (!pg->clks)
932 return -ENOMEM;
933
934 for (i = 0; i < count; i++) {
935 pg->clks[i] = of_clk_get(np, i);
936 if (IS_ERR(pg->clks[i])) {
937 err = PTR_ERR(pg->clks[i]);
938 goto err;
939 }
940 }
941
942 pg->num_clks = count;
943
944 return 0;
945
946 err:
947 while (i--)
948 clk_put(pg->clks[i]);
949
950 kfree(pg->clks);
951
952 return err;
953 }
954
955 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
956 struct device_node *np, bool off)
957 {
958 struct device *dev = pg->pmc->dev;
959 int err;
960
961 pg->reset = of_reset_control_array_get_exclusive_released(np);
962 if (IS_ERR(pg->reset)) {
963 err = PTR_ERR(pg->reset);
964 dev_err(dev, "failed to get device resets: %d\n", err);
965 return err;
966 }
967
968 err = reset_control_acquire(pg->reset);
969 if (err < 0) {
970 pr_err("failed to acquire resets: %d\n", err);
971 goto out;
972 }
973
974 if (off) {
975 err = reset_control_assert(pg->reset);
976 } else {
977 err = reset_control_deassert(pg->reset);
978 if (err < 0)
979 goto out;
980
981 reset_control_release(pg->reset);
982 }
983
984 out:
985 if (err) {
986 reset_control_release(pg->reset);
987 reset_control_put(pg->reset);
988 }
989
990 return err;
991 }
992
993 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
994 {
995 struct device *dev = pmc->dev;
996 struct tegra_powergate *pg;
997 int id, err = 0;
998 bool off;
999
1000 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1001 if (!pg)
1002 return -ENOMEM;
1003
1004 id = tegra_powergate_lookup(pmc, np->name);
1005 if (id < 0) {
1006 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1007 err = -ENODEV;
1008 goto free_mem;
1009 }
1010
1011 /*
1012 * Clear the bit for this powergate so it cannot be managed
1013 * directly via the legacy APIs for controlling powergates.
1014 */
1015 clear_bit(id, pmc->powergates_available);
1016
1017 pg->id = id;
1018 pg->genpd.name = np->name;
1019 pg->genpd.power_off = tegra_genpd_power_off;
1020 pg->genpd.power_on = tegra_genpd_power_on;
1021 pg->pmc = pmc;
1022
1023 off = !tegra_powergate_is_powered(pmc, pg->id);
1024
1025 err = tegra_powergate_of_get_clks(pg, np);
1026 if (err < 0) {
1027 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1028 goto set_available;
1029 }
1030
1031 err = tegra_powergate_of_get_resets(pg, np, off);
1032 if (err < 0) {
1033 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1034 goto remove_clks;
1035 }
1036
1037 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1038 if (off)
1039 WARN_ON(tegra_powergate_power_up(pg, true));
1040
1041 goto remove_resets;
1042 }
1043
1044 err = pm_genpd_init(&pg->genpd, NULL, off);
1045 if (err < 0) {
1046 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1047 err);
1048 goto remove_resets;
1049 }
1050
1051 err = of_genpd_add_provider_simple(np, &pg->genpd);
1052 if (err < 0) {
1053 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1054 np, err);
1055 goto remove_genpd;
1056 }
1057
1058 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1059
1060 return 0;
1061
1062 remove_genpd:
1063 pm_genpd_remove(&pg->genpd);
1064
1065 remove_resets:
1066 reset_control_put(pg->reset);
1067
1068 remove_clks:
1069 while (pg->num_clks--)
1070 clk_put(pg->clks[pg->num_clks]);
1071
1072 kfree(pg->clks);
1073
1074 set_available:
1075 set_bit(id, pmc->powergates_available);
1076
1077 free_mem:
1078 kfree(pg);
1079
1080 return err;
1081 }
1082
1083 static int tegra_powergate_init(struct tegra_pmc *pmc,
1084 struct device_node *parent)
1085 {
1086 struct device_node *np, *child;
1087 int err = 0;
1088
1089 np = of_get_child_by_name(parent, "powergates");
1090 if (!np)
1091 return 0;
1092
1093 for_each_child_of_node(np, child) {
1094 err = tegra_powergate_add(pmc, child);
1095 if (err < 0) {
1096 of_node_put(child);
1097 break;
1098 }
1099 }
1100
1101 of_node_put(np);
1102
1103 return err;
1104 }
1105
1106 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1107 {
1108 struct tegra_powergate *pg = to_powergate(genpd);
1109
1110 reset_control_put(pg->reset);
1111
1112 while (pg->num_clks--)
1113 clk_put(pg->clks[pg->num_clks]);
1114
1115 kfree(pg->clks);
1116
1117 set_bit(pg->id, pmc->powergates_available);
1118
1119 kfree(pg);
1120 }
1121
1122 static void tegra_powergate_remove_all(struct device_node *parent)
1123 {
1124 struct generic_pm_domain *genpd;
1125 struct device_node *np, *child;
1126
1127 np = of_get_child_by_name(parent, "powergates");
1128 if (!np)
1129 return;
1130
1131 for_each_child_of_node(np, child) {
1132 of_genpd_del_provider(child);
1133
1134 genpd = of_genpd_remove_last(child);
1135 if (IS_ERR(genpd))
1136 continue;
1137
1138 tegra_powergate_remove(genpd);
1139 }
1140
1141 of_node_put(np);
1142 }
1143
1144 static const struct tegra_io_pad_soc *
1145 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1146 {
1147 unsigned int i;
1148
1149 for (i = 0; i < pmc->soc->num_io_pads; i++)
1150 if (pmc->soc->io_pads[i].id == id)
1151 return &pmc->soc->io_pads[i];
1152
1153 return NULL;
1154 }
1155
1156 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1157 enum tegra_io_pad id,
1158 unsigned long *request,
1159 unsigned long *status,
1160 u32 *mask)
1161 {
1162 const struct tegra_io_pad_soc *pad;
1163
1164 pad = tegra_io_pad_find(pmc, id);
1165 if (!pad) {
1166 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1167 return -ENOENT;
1168 }
1169
1170 if (pad->dpd == UINT_MAX)
1171 return -ENOTSUPP;
1172
1173 *mask = BIT(pad->dpd % 32);
1174
1175 if (pad->dpd < 32) {
1176 *status = pmc->soc->regs->dpd_status;
1177 *request = pmc->soc->regs->dpd_req;
1178 } else {
1179 *status = pmc->soc->regs->dpd2_status;
1180 *request = pmc->soc->regs->dpd2_req;
1181 }
1182
1183 return 0;
1184 }
1185
1186 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1187 unsigned long *request, unsigned long *status,
1188 u32 *mask)
1189 {
1190 unsigned long rate, value;
1191 int err;
1192
1193 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1194 if (err)
1195 return err;
1196
1197 if (pmc->clk) {
1198 rate = clk_get_rate(pmc->clk);
1199 if (!rate) {
1200 dev_err(pmc->dev, "failed to get clock rate\n");
1201 return -ENODEV;
1202 }
1203
1204 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1205
1206 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1207 value = DIV_ROUND_UP(1000000000, rate);
1208 value = DIV_ROUND_UP(200, value);
1209 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1210 }
1211
1212 return 0;
1213 }
1214
1215 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1216 u32 mask, u32 val, unsigned long timeout)
1217 {
1218 u32 value;
1219
1220 timeout = jiffies + msecs_to_jiffies(timeout);
1221
1222 while (time_after(timeout, jiffies)) {
1223 value = tegra_pmc_readl(pmc, offset);
1224 if ((value & mask) == val)
1225 return 0;
1226
1227 usleep_range(250, 1000);
1228 }
1229
1230 return -ETIMEDOUT;
1231 }
1232
1233 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1234 {
1235 if (pmc->clk)
1236 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1237 }
1238
1239 /**
1240 * tegra_io_pad_power_enable() - enable power to I/O pad
1241 * @id: Tegra I/O pad ID for which to enable power
1242 *
1243 * Returns: 0 on success or a negative error code on failure.
1244 */
1245 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1246 {
1247 unsigned long request, status;
1248 u32 mask;
1249 int err;
1250
1251 mutex_lock(&pmc->powergates_lock);
1252
1253 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1254 if (err < 0) {
1255 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1256 goto unlock;
1257 }
1258
1259 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1260
1261 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1262 if (err < 0) {
1263 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1264 goto unlock;
1265 }
1266
1267 tegra_io_pad_unprepare(pmc);
1268
1269 unlock:
1270 mutex_unlock(&pmc->powergates_lock);
1271 return err;
1272 }
1273 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1274
1275 /**
1276 * tegra_io_pad_power_disable() - disable power to I/O pad
1277 * @id: Tegra I/O pad ID for which to disable power
1278 *
1279 * Returns: 0 on success or a negative error code on failure.
1280 */
1281 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1282 {
1283 unsigned long request, status;
1284 u32 mask;
1285 int err;
1286
1287 mutex_lock(&pmc->powergates_lock);
1288
1289 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1290 if (err < 0) {
1291 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1292 goto unlock;
1293 }
1294
1295 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1296
1297 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1298 if (err < 0) {
1299 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1300 goto unlock;
1301 }
1302
1303 tegra_io_pad_unprepare(pmc);
1304
1305 unlock:
1306 mutex_unlock(&pmc->powergates_lock);
1307 return err;
1308 }
1309 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1310
1311 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1312 {
1313 unsigned long request, status;
1314 u32 mask, value;
1315 int err;
1316
1317 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1318 &mask);
1319 if (err)
1320 return err;
1321
1322 value = tegra_pmc_readl(pmc, status);
1323
1324 return !(value & mask);
1325 }
1326
1327 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1328 int voltage)
1329 {
1330 const struct tegra_io_pad_soc *pad;
1331 u32 value;
1332
1333 pad = tegra_io_pad_find(pmc, id);
1334 if (!pad)
1335 return -ENOENT;
1336
1337 if (pad->voltage == UINT_MAX)
1338 return -ENOTSUPP;
1339
1340 mutex_lock(&pmc->powergates_lock);
1341
1342 if (pmc->soc->has_impl_33v_pwr) {
1343 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1344
1345 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1346 value &= ~BIT(pad->voltage);
1347 else
1348 value |= BIT(pad->voltage);
1349
1350 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1351 } else {
1352 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1353 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1354 value |= BIT(pad->voltage);
1355 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1356
1357 /* update I/O voltage */
1358 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1359
1360 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1361 value &= ~BIT(pad->voltage);
1362 else
1363 value |= BIT(pad->voltage);
1364
1365 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1366 }
1367
1368 mutex_unlock(&pmc->powergates_lock);
1369
1370 usleep_range(100, 250);
1371
1372 return 0;
1373 }
1374
1375 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1376 {
1377 const struct tegra_io_pad_soc *pad;
1378 u32 value;
1379
1380 pad = tegra_io_pad_find(pmc, id);
1381 if (!pad)
1382 return -ENOENT;
1383
1384 if (pad->voltage == UINT_MAX)
1385 return -ENOTSUPP;
1386
1387 if (pmc->soc->has_impl_33v_pwr)
1388 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1389 else
1390 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1391
1392 if ((value & BIT(pad->voltage)) == 0)
1393 return TEGRA_IO_PAD_VOLTAGE_1V8;
1394
1395 return TEGRA_IO_PAD_VOLTAGE_3V3;
1396 }
1397
1398 /**
1399 * tegra_io_rail_power_on() - enable power to I/O rail
1400 * @id: Tegra I/O pad ID for which to enable power
1401 *
1402 * See also: tegra_io_pad_power_enable()
1403 */
1404 int tegra_io_rail_power_on(unsigned int id)
1405 {
1406 return tegra_io_pad_power_enable(id);
1407 }
1408 EXPORT_SYMBOL(tegra_io_rail_power_on);
1409
1410 /**
1411 * tegra_io_rail_power_off() - disable power to I/O rail
1412 * @id: Tegra I/O pad ID for which to disable power
1413 *
1414 * See also: tegra_io_pad_power_disable()
1415 */
1416 int tegra_io_rail_power_off(unsigned int id)
1417 {
1418 return tegra_io_pad_power_disable(id);
1419 }
1420 EXPORT_SYMBOL(tegra_io_rail_power_off);
1421
1422 #ifdef CONFIG_PM_SLEEP
1423 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1424 {
1425 return pmc->suspend_mode;
1426 }
1427
1428 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1429 {
1430 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1431 return;
1432
1433 pmc->suspend_mode = mode;
1434 }
1435
1436 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1437 {
1438 unsigned long long rate = 0;
1439 u32 value;
1440
1441 switch (mode) {
1442 case TEGRA_SUSPEND_LP1:
1443 rate = 32768;
1444 break;
1445
1446 case TEGRA_SUSPEND_LP2:
1447 rate = clk_get_rate(pmc->clk);
1448 break;
1449
1450 default:
1451 break;
1452 }
1453
1454 if (WARN_ON_ONCE(rate == 0))
1455 rate = 100000000;
1456
1457 if (rate != pmc->rate) {
1458 u64 ticks;
1459
1460 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1461 do_div(ticks, USEC_PER_SEC);
1462 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1463
1464 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1465 do_div(ticks, USEC_PER_SEC);
1466 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1467
1468 wmb();
1469
1470 pmc->rate = rate;
1471 }
1472
1473 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1474 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1475 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1476 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1477 }
1478 #endif
1479
1480 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1481 {
1482 u32 value, values[2];
1483
1484 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1485 } else {
1486 switch (value) {
1487 case 0:
1488 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1489 break;
1490
1491 case 1:
1492 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1493 break;
1494
1495 case 2:
1496 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1497 break;
1498
1499 default:
1500 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1501 break;
1502 }
1503 }
1504
1505 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1506
1507 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1508 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1509
1510 pmc->cpu_good_time = value;
1511
1512 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1513 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1514
1515 pmc->cpu_off_time = value;
1516
1517 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1518 values, ARRAY_SIZE(values)))
1519 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1520
1521 pmc->core_osc_time = values[0];
1522 pmc->core_pmu_time = values[1];
1523
1524 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1525 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1526
1527 pmc->core_off_time = value;
1528
1529 pmc->corereq_high = of_property_read_bool(np,
1530 "nvidia,core-power-req-active-high");
1531
1532 pmc->sysclkreq_high = of_property_read_bool(np,
1533 "nvidia,sys-clock-req-active-high");
1534
1535 pmc->combined_req = of_property_read_bool(np,
1536 "nvidia,combined-power-req");
1537
1538 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1539 "nvidia,cpu-pwr-good-en");
1540
1541 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1542 ARRAY_SIZE(values)))
1543 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1544 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1545
1546 pmc->lp0_vec_phys = values[0];
1547 pmc->lp0_vec_size = values[1];
1548
1549 return 0;
1550 }
1551
1552 static void tegra_pmc_init(struct tegra_pmc *pmc)
1553 {
1554 if (pmc->soc->init)
1555 pmc->soc->init(pmc);
1556 }
1557
1558 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1559 {
1560 static const char disabled[] = "emergency thermal reset disabled";
1561 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1562 struct device *dev = pmc->dev;
1563 struct device_node *np;
1564 u32 value, checksum;
1565
1566 if (!pmc->soc->has_tsense_reset)
1567 return;
1568
1569 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1570 if (!np) {
1571 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1572 return;
1573 }
1574
1575 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1576 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1577 goto out;
1578 }
1579
1580 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1581 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1582 goto out;
1583 }
1584
1585 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1586 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1587 goto out;
1588 }
1589
1590 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1591 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1592 goto out;
1593 }
1594
1595 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1596 pinmux = 0;
1597
1598 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1599 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1600 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1601
1602 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1603 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1604 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1605
1606 value = PMC_SCRATCH55_RESET_TEGRA;
1607 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1608 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1609 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1610
1611 /*
1612 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1613 * contain the checksum and are currently zero, so they are not added.
1614 */
1615 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1616 + ((value >> 24) & 0xff);
1617 checksum &= 0xff;
1618 checksum = 0x100 - checksum;
1619
1620 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1621
1622 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1623
1624 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1625 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1626 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1627
1628 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1629
1630 out:
1631 of_node_put(np);
1632 }
1633
1634 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1635 {
1636 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1637
1638 return pmc->soc->num_io_pads;
1639 }
1640
1641 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1642 unsigned int group)
1643 {
1644 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1645
1646 return pmc->soc->io_pads[group].name;
1647 }
1648
1649 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1650 unsigned int group,
1651 const unsigned int **pins,
1652 unsigned int *num_pins)
1653 {
1654 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1655
1656 *pins = &pmc->soc->io_pads[group].id;
1657 *num_pins = 1;
1658
1659 return 0;
1660 }
1661
1662 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1663 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1664 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1665 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1666 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1667 .dt_free_map = pinconf_generic_dt_free_map,
1668 };
1669
1670 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1671 unsigned int pin, unsigned long *config)
1672 {
1673 enum pin_config_param param = pinconf_to_config_param(*config);
1674 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1675 const struct tegra_io_pad_soc *pad;
1676 int ret;
1677 u32 arg;
1678
1679 pad = tegra_io_pad_find(pmc, pin);
1680 if (!pad)
1681 return -EINVAL;
1682
1683 switch (param) {
1684 case PIN_CONFIG_POWER_SOURCE:
1685 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1686 if (ret < 0)
1687 return ret;
1688
1689 arg = ret;
1690 break;
1691
1692 case PIN_CONFIG_LOW_POWER_MODE:
1693 ret = tegra_io_pad_is_powered(pmc, pad->id);
1694 if (ret < 0)
1695 return ret;
1696
1697 arg = !ret;
1698 break;
1699
1700 default:
1701 return -EINVAL;
1702 }
1703
1704 *config = pinconf_to_config_packed(param, arg);
1705
1706 return 0;
1707 }
1708
1709 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1710 unsigned int pin, unsigned long *configs,
1711 unsigned int num_configs)
1712 {
1713 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1714 const struct tegra_io_pad_soc *pad;
1715 enum pin_config_param param;
1716 unsigned int i;
1717 int err;
1718 u32 arg;
1719
1720 pad = tegra_io_pad_find(pmc, pin);
1721 if (!pad)
1722 return -EINVAL;
1723
1724 for (i = 0; i < num_configs; ++i) {
1725 param = pinconf_to_config_param(configs[i]);
1726 arg = pinconf_to_config_argument(configs[i]);
1727
1728 switch (param) {
1729 case PIN_CONFIG_LOW_POWER_MODE:
1730 if (arg)
1731 err = tegra_io_pad_power_disable(pad->id);
1732 else
1733 err = tegra_io_pad_power_enable(pad->id);
1734 if (err)
1735 return err;
1736 break;
1737 case PIN_CONFIG_POWER_SOURCE:
1738 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1739 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1740 return -EINVAL;
1741 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1742 if (err)
1743 return err;
1744 break;
1745 default:
1746 return -EINVAL;
1747 }
1748 }
1749
1750 return 0;
1751 }
1752
1753 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1754 .pin_config_get = tegra_io_pad_pinconf_get,
1755 .pin_config_set = tegra_io_pad_pinconf_set,
1756 .is_generic = true,
1757 };
1758
1759 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1760 .pctlops = &tegra_io_pad_pinctrl_ops,
1761 .confops = &tegra_io_pad_pinconf_ops,
1762 };
1763
1764 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1765 {
1766 int err;
1767
1768 if (!pmc->soc->num_pin_descs)
1769 return 0;
1770
1771 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1772 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1773 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1774
1775 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1776 pmc);
1777 if (IS_ERR(pmc->pctl_dev)) {
1778 err = PTR_ERR(pmc->pctl_dev);
1779 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1780 err);
1781 return err;
1782 }
1783
1784 return 0;
1785 }
1786
1787 static ssize_t reset_reason_show(struct device *dev,
1788 struct device_attribute *attr, char *buf)
1789 {
1790 u32 value;
1791
1792 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1793 value &= pmc->soc->regs->rst_source_mask;
1794 value >>= pmc->soc->regs->rst_source_shift;
1795
1796 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1797 return sprintf(buf, "%s\n", "UNKNOWN");
1798
1799 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1800 }
1801
1802 static DEVICE_ATTR_RO(reset_reason);
1803
1804 static ssize_t reset_level_show(struct device *dev,
1805 struct device_attribute *attr, char *buf)
1806 {
1807 u32 value;
1808
1809 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1810 value &= pmc->soc->regs->rst_level_mask;
1811 value >>= pmc->soc->regs->rst_level_shift;
1812
1813 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1814 return sprintf(buf, "%s\n", "UNKNOWN");
1815
1816 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1817 }
1818
1819 static DEVICE_ATTR_RO(reset_level);
1820
1821 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1822 {
1823 struct device *dev = pmc->dev;
1824 int err = 0;
1825
1826 if (pmc->soc->reset_sources) {
1827 err = device_create_file(dev, &dev_attr_reset_reason);
1828 if (err < 0)
1829 dev_warn(dev,
1830 "failed to create attr \"reset_reason\": %d\n",
1831 err);
1832 }
1833
1834 if (pmc->soc->reset_levels) {
1835 err = device_create_file(dev, &dev_attr_reset_level);
1836 if (err < 0)
1837 dev_warn(dev,
1838 "failed to create attr \"reset_level\": %d\n",
1839 err);
1840 }
1841 }
1842
1843 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1844 struct irq_fwspec *fwspec,
1845 unsigned long *hwirq,
1846 unsigned int *type)
1847 {
1848 if (WARN_ON(fwspec->param_count < 2))
1849 return -EINVAL;
1850
1851 *hwirq = fwspec->param[0];
1852 *type = fwspec->param[1];
1853
1854 return 0;
1855 }
1856
1857 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1858 unsigned int num_irqs, void *data)
1859 {
1860 struct tegra_pmc *pmc = domain->host_data;
1861 const struct tegra_pmc_soc *soc = pmc->soc;
1862 struct irq_fwspec *fwspec = data;
1863 unsigned int i;
1864 int err = 0;
1865
1866 for (i = 0; i < soc->num_wake_events; i++) {
1867 const struct tegra_wake_event *event = &soc->wake_events[i];
1868
1869 if (fwspec->param_count == 2) {
1870 struct irq_fwspec spec;
1871
1872 if (event->id != fwspec->param[0])
1873 continue;
1874
1875 err = irq_domain_set_hwirq_and_chip(domain, virq,
1876 event->id,
1877 &pmc->irq, pmc);
1878 if (err < 0)
1879 break;
1880
1881 spec.fwnode = &pmc->dev->of_node->fwnode;
1882 spec.param_count = 3;
1883 spec.param[0] = GIC_SPI;
1884 spec.param[1] = event->irq;
1885 spec.param[2] = fwspec->param[1];
1886
1887 err = irq_domain_alloc_irqs_parent(domain, virq,
1888 num_irqs, &spec);
1889
1890 break;
1891 }
1892
1893 if (fwspec->param_count == 3) {
1894 if (event->gpio.instance != fwspec->param[0] ||
1895 event->gpio.pin != fwspec->param[1])
1896 continue;
1897
1898 err = irq_domain_set_hwirq_and_chip(domain, virq,
1899 event->id,
1900 &pmc->irq, pmc);
1901
1902 break;
1903 }
1904 }
1905
1906 if (i == soc->num_wake_events)
1907 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
1908 &pmc->irq, pmc);
1909
1910 return err;
1911 }
1912
1913 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1914 .translate = tegra_pmc_irq_translate,
1915 .alloc = tegra_pmc_irq_alloc,
1916 };
1917
1918 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1919 {
1920 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1921 unsigned int offset, bit;
1922 u32 value;
1923
1924 offset = data->hwirq / 32;
1925 bit = data->hwirq % 32;
1926
1927 /* clear wake status */
1928 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
1929
1930 /* route wake to tier 2 */
1931 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1932
1933 if (!on)
1934 value &= ~(1 << bit);
1935 else
1936 value |= 1 << bit;
1937
1938 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1939
1940 /* enable wakeup event */
1941 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
1942
1943 return 0;
1944 }
1945
1946 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)
1947 {
1948 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1949 u32 value;
1950
1951 if (data->hwirq == ULONG_MAX)
1952 return 0;
1953
1954 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1955
1956 switch (type) {
1957 case IRQ_TYPE_EDGE_RISING:
1958 case IRQ_TYPE_LEVEL_HIGH:
1959 value |= WAKE_AOWAKE_CNTRL_LEVEL;
1960 break;
1961
1962 case IRQ_TYPE_EDGE_FALLING:
1963 case IRQ_TYPE_LEVEL_LOW:
1964 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
1965 break;
1966
1967 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
1968 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
1969 break;
1970
1971 default:
1972 return -EINVAL;
1973 }
1974
1975 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1976
1977 return 0;
1978 }
1979
1980 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
1981 {
1982 struct irq_domain *parent = NULL;
1983 struct device_node *np;
1984
1985 np = of_irq_find_parent(pmc->dev->of_node);
1986 if (np) {
1987 parent = irq_find_host(np);
1988 of_node_put(np);
1989 }
1990
1991 if (!parent)
1992 return 0;
1993
1994 pmc->irq.name = dev_name(pmc->dev);
1995 pmc->irq.irq_mask = irq_chip_mask_parent;
1996 pmc->irq.irq_unmask = irq_chip_unmask_parent;
1997 pmc->irq.irq_eoi = irq_chip_eoi_parent;
1998 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
1999 pmc->irq.irq_set_type = tegra_pmc_irq_set_type;
2000 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;
2001
2002 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2003 &tegra_pmc_irq_domain_ops, pmc);
2004 if (!pmc->domain) {
2005 dev_err(pmc->dev, "failed to allocate domain\n");
2006 return -ENOMEM;
2007 }
2008
2009 return 0;
2010 }
2011
2012 static int tegra_pmc_probe(struct platform_device *pdev)
2013 {
2014 void __iomem *base;
2015 struct resource *res;
2016 int err;
2017
2018 /*
2019 * Early initialisation should have configured an initial
2020 * register mapping and setup the soc data pointer. If these
2021 * are not valid then something went badly wrong!
2022 */
2023 if (WARN_ON(!pmc->base || !pmc->soc))
2024 return -ENODEV;
2025
2026 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2027 if (err < 0)
2028 return err;
2029
2030 /* take over the memory region from the early initialization */
2031 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2032 base = devm_ioremap_resource(&pdev->dev, res);
2033 if (IS_ERR(base))
2034 return PTR_ERR(base);
2035
2036 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2037 if (res) {
2038 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2039 if (IS_ERR(pmc->wake))
2040 return PTR_ERR(pmc->wake);
2041 } else {
2042 pmc->wake = base;
2043 }
2044
2045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2046 if (res) {
2047 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2048 if (IS_ERR(pmc->aotag))
2049 return PTR_ERR(pmc->aotag);
2050 } else {
2051 pmc->aotag = base;
2052 }
2053
2054 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2055 if (res) {
2056 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2057 if (IS_ERR(pmc->scratch))
2058 return PTR_ERR(pmc->scratch);
2059 } else {
2060 pmc->scratch = base;
2061 }
2062
2063 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2064 if (IS_ERR(pmc->clk)) {
2065 err = PTR_ERR(pmc->clk);
2066
2067 if (err != -ENOENT) {
2068 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2069 return err;
2070 }
2071
2072 pmc->clk = NULL;
2073 }
2074
2075 pmc->dev = &pdev->dev;
2076
2077 tegra_pmc_init(pmc);
2078
2079 tegra_pmc_init_tsense_reset(pmc);
2080
2081 tegra_pmc_reset_sysfs_init(pmc);
2082
2083 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2084 err = tegra_powergate_debugfs_init();
2085 if (err < 0)
2086 goto cleanup_sysfs;
2087 }
2088
2089 err = register_restart_handler(&tegra_pmc_restart_handler);
2090 if (err) {
2091 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2092 err);
2093 goto cleanup_debugfs;
2094 }
2095
2096 err = tegra_pmc_pinctrl_init(pmc);
2097 if (err)
2098 goto cleanup_restart_handler;
2099
2100 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2101 if (err < 0)
2102 goto cleanup_powergates;
2103
2104 err = tegra_pmc_irq_init(pmc);
2105 if (err < 0)
2106 goto cleanup_powergates;
2107
2108 mutex_lock(&pmc->powergates_lock);
2109 iounmap(pmc->base);
2110 pmc->base = base;
2111 mutex_unlock(&pmc->powergates_lock);
2112
2113 platform_set_drvdata(pdev, pmc);
2114
2115 return 0;
2116
2117 cleanup_powergates:
2118 tegra_powergate_remove_all(pdev->dev.of_node);
2119 cleanup_restart_handler:
2120 unregister_restart_handler(&tegra_pmc_restart_handler);
2121 cleanup_debugfs:
2122 debugfs_remove(pmc->debugfs);
2123 cleanup_sysfs:
2124 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2125 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2126 return err;
2127 }
2128
2129 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2130 static int tegra_pmc_suspend(struct device *dev)
2131 {
2132 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2133
2134 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2135
2136 return 0;
2137 }
2138
2139 static int tegra_pmc_resume(struct device *dev)
2140 {
2141 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2142
2143 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2144
2145 return 0;
2146 }
2147
2148 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2149
2150 #endif
2151
2152 static const char * const tegra20_powergates[] = {
2153 [TEGRA_POWERGATE_CPU] = "cpu",
2154 [TEGRA_POWERGATE_3D] = "3d",
2155 [TEGRA_POWERGATE_VENC] = "venc",
2156 [TEGRA_POWERGATE_VDEC] = "vdec",
2157 [TEGRA_POWERGATE_PCIE] = "pcie",
2158 [TEGRA_POWERGATE_L2] = "l2",
2159 [TEGRA_POWERGATE_MPE] = "mpe",
2160 };
2161
2162 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2163 .scratch0 = 0x50,
2164 .dpd_req = 0x1b8,
2165 .dpd_status = 0x1bc,
2166 .dpd2_req = 0x1c0,
2167 .dpd2_status = 0x1c4,
2168 .rst_status = 0x1b4,
2169 .rst_source_shift = 0x0,
2170 .rst_source_mask = 0x7,
2171 .rst_level_shift = 0x0,
2172 .rst_level_mask = 0x0,
2173 };
2174
2175 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2176 {
2177 u32 value;
2178
2179 /* Always enable CPU power request */
2180 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2181 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2182 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2183
2184 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2185
2186 if (pmc->sysclkreq_high)
2187 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2188 else
2189 value |= PMC_CNTRL_SYSCLK_POLARITY;
2190
2191 /* configure the output polarity while the request is tristated */
2192 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2193
2194 /* now enable the request */
2195 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2196 value |= PMC_CNTRL_SYSCLK_OE;
2197 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2198 }
2199
2200 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2201 struct device_node *np,
2202 bool invert)
2203 {
2204 u32 value;
2205
2206 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2207
2208 if (invert)
2209 value |= PMC_CNTRL_INTR_POLARITY;
2210 else
2211 value &= ~PMC_CNTRL_INTR_POLARITY;
2212
2213 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2214 }
2215
2216 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2217 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2218 .powergates = tegra20_powergates,
2219 .num_cpu_powergates = 0,
2220 .cpu_powergates = NULL,
2221 .has_tsense_reset = false,
2222 .has_gpu_clamps = false,
2223 .needs_mbist_war = false,
2224 .has_impl_33v_pwr = false,
2225 .maybe_tz_only = false,
2226 .num_io_pads = 0,
2227 .io_pads = NULL,
2228 .num_pin_descs = 0,
2229 .pin_descs = NULL,
2230 .regs = &tegra20_pmc_regs,
2231 .init = tegra20_pmc_init,
2232 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2233 .reset_sources = NULL,
2234 .num_reset_sources = 0,
2235 .reset_levels = NULL,
2236 .num_reset_levels = 0,
2237 };
2238
2239 static const char * const tegra30_powergates[] = {
2240 [TEGRA_POWERGATE_CPU] = "cpu0",
2241 [TEGRA_POWERGATE_3D] = "3d0",
2242 [TEGRA_POWERGATE_VENC] = "venc",
2243 [TEGRA_POWERGATE_VDEC] = "vdec",
2244 [TEGRA_POWERGATE_PCIE] = "pcie",
2245 [TEGRA_POWERGATE_L2] = "l2",
2246 [TEGRA_POWERGATE_MPE] = "mpe",
2247 [TEGRA_POWERGATE_HEG] = "heg",
2248 [TEGRA_POWERGATE_SATA] = "sata",
2249 [TEGRA_POWERGATE_CPU1] = "cpu1",
2250 [TEGRA_POWERGATE_CPU2] = "cpu2",
2251 [TEGRA_POWERGATE_CPU3] = "cpu3",
2252 [TEGRA_POWERGATE_CELP] = "celp",
2253 [TEGRA_POWERGATE_3D1] = "3d1",
2254 };
2255
2256 static const u8 tegra30_cpu_powergates[] = {
2257 TEGRA_POWERGATE_CPU,
2258 TEGRA_POWERGATE_CPU1,
2259 TEGRA_POWERGATE_CPU2,
2260 TEGRA_POWERGATE_CPU3,
2261 };
2262
2263 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2264 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2265 .powergates = tegra30_powergates,
2266 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2267 .cpu_powergates = tegra30_cpu_powergates,
2268 .has_tsense_reset = true,
2269 .has_gpu_clamps = false,
2270 .needs_mbist_war = false,
2271 .has_impl_33v_pwr = false,
2272 .maybe_tz_only = false,
2273 .num_io_pads = 0,
2274 .io_pads = NULL,
2275 .num_pin_descs = 0,
2276 .pin_descs = NULL,
2277 .regs = &tegra20_pmc_regs,
2278 .init = tegra20_pmc_init,
2279 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2280 .reset_sources = tegra30_reset_sources,
2281 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2282 .reset_levels = NULL,
2283 .num_reset_levels = 0,
2284 };
2285
2286 static const char * const tegra114_powergates[] = {
2287 [TEGRA_POWERGATE_CPU] = "crail",
2288 [TEGRA_POWERGATE_3D] = "3d",
2289 [TEGRA_POWERGATE_VENC] = "venc",
2290 [TEGRA_POWERGATE_VDEC] = "vdec",
2291 [TEGRA_POWERGATE_MPE] = "mpe",
2292 [TEGRA_POWERGATE_HEG] = "heg",
2293 [TEGRA_POWERGATE_CPU1] = "cpu1",
2294 [TEGRA_POWERGATE_CPU2] = "cpu2",
2295 [TEGRA_POWERGATE_CPU3] = "cpu3",
2296 [TEGRA_POWERGATE_CELP] = "celp",
2297 [TEGRA_POWERGATE_CPU0] = "cpu0",
2298 [TEGRA_POWERGATE_C0NC] = "c0nc",
2299 [TEGRA_POWERGATE_C1NC] = "c1nc",
2300 [TEGRA_POWERGATE_DIS] = "dis",
2301 [TEGRA_POWERGATE_DISB] = "disb",
2302 [TEGRA_POWERGATE_XUSBA] = "xusba",
2303 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2304 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2305 };
2306
2307 static const u8 tegra114_cpu_powergates[] = {
2308 TEGRA_POWERGATE_CPU0,
2309 TEGRA_POWERGATE_CPU1,
2310 TEGRA_POWERGATE_CPU2,
2311 TEGRA_POWERGATE_CPU3,
2312 };
2313
2314 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2315 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2316 .powergates = tegra114_powergates,
2317 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2318 .cpu_powergates = tegra114_cpu_powergates,
2319 .has_tsense_reset = true,
2320 .has_gpu_clamps = false,
2321 .needs_mbist_war = false,
2322 .has_impl_33v_pwr = false,
2323 .maybe_tz_only = false,
2324 .num_io_pads = 0,
2325 .io_pads = NULL,
2326 .num_pin_descs = 0,
2327 .pin_descs = NULL,
2328 .regs = &tegra20_pmc_regs,
2329 .init = tegra20_pmc_init,
2330 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2331 .reset_sources = tegra30_reset_sources,
2332 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2333 .reset_levels = NULL,
2334 .num_reset_levels = 0,
2335 };
2336
2337 static const char * const tegra124_powergates[] = {
2338 [TEGRA_POWERGATE_CPU] = "crail",
2339 [TEGRA_POWERGATE_3D] = "3d",
2340 [TEGRA_POWERGATE_VENC] = "venc",
2341 [TEGRA_POWERGATE_PCIE] = "pcie",
2342 [TEGRA_POWERGATE_VDEC] = "vdec",
2343 [TEGRA_POWERGATE_MPE] = "mpe",
2344 [TEGRA_POWERGATE_HEG] = "heg",
2345 [TEGRA_POWERGATE_SATA] = "sata",
2346 [TEGRA_POWERGATE_CPU1] = "cpu1",
2347 [TEGRA_POWERGATE_CPU2] = "cpu2",
2348 [TEGRA_POWERGATE_CPU3] = "cpu3",
2349 [TEGRA_POWERGATE_CELP] = "celp",
2350 [TEGRA_POWERGATE_CPU0] = "cpu0",
2351 [TEGRA_POWERGATE_C0NC] = "c0nc",
2352 [TEGRA_POWERGATE_C1NC] = "c1nc",
2353 [TEGRA_POWERGATE_SOR] = "sor",
2354 [TEGRA_POWERGATE_DIS] = "dis",
2355 [TEGRA_POWERGATE_DISB] = "disb",
2356 [TEGRA_POWERGATE_XUSBA] = "xusba",
2357 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2358 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2359 [TEGRA_POWERGATE_VIC] = "vic",
2360 [TEGRA_POWERGATE_IRAM] = "iram",
2361 };
2362
2363 static const u8 tegra124_cpu_powergates[] = {
2364 TEGRA_POWERGATE_CPU0,
2365 TEGRA_POWERGATE_CPU1,
2366 TEGRA_POWERGATE_CPU2,
2367 TEGRA_POWERGATE_CPU3,
2368 };
2369
2370 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2371 ((struct tegra_io_pad_soc) { \
2372 .id = (_id), \
2373 .dpd = (_dpd), \
2374 .voltage = (_voltage), \
2375 .name = (_name), \
2376 })
2377
2378 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2379 ((struct pinctrl_pin_desc) { \
2380 .number = (_id), \
2381 .name = (_name) \
2382 })
2383
2384 #define TEGRA124_IO_PAD_TABLE(_pad) \
2385 /* .id .dpd .voltage .name */ \
2386 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2387 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2388 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2389 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2390 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2391 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2392 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2393 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2394 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2395 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2396 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2397 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2398 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2399 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2400 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2401 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2402 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2403 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2404 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2405 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2406 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2407 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2408 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2409 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2410 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2411 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2412 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2413 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2414 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2415 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2416
2417 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2418 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2419 };
2420
2421 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2422 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2423 };
2424
2425 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2426 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2427 .powergates = tegra124_powergates,
2428 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2429 .cpu_powergates = tegra124_cpu_powergates,
2430 .has_tsense_reset = true,
2431 .has_gpu_clamps = true,
2432 .needs_mbist_war = false,
2433 .has_impl_33v_pwr = false,
2434 .maybe_tz_only = false,
2435 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2436 .io_pads = tegra124_io_pads,
2437 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2438 .pin_descs = tegra124_pin_descs,
2439 .regs = &tegra20_pmc_regs,
2440 .init = tegra20_pmc_init,
2441 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2442 .reset_sources = tegra30_reset_sources,
2443 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2444 .reset_levels = NULL,
2445 .num_reset_levels = 0,
2446 };
2447
2448 static const char * const tegra210_powergates[] = {
2449 [TEGRA_POWERGATE_CPU] = "crail",
2450 [TEGRA_POWERGATE_3D] = "3d",
2451 [TEGRA_POWERGATE_VENC] = "venc",
2452 [TEGRA_POWERGATE_PCIE] = "pcie",
2453 [TEGRA_POWERGATE_MPE] = "mpe",
2454 [TEGRA_POWERGATE_SATA] = "sata",
2455 [TEGRA_POWERGATE_CPU1] = "cpu1",
2456 [TEGRA_POWERGATE_CPU2] = "cpu2",
2457 [TEGRA_POWERGATE_CPU3] = "cpu3",
2458 [TEGRA_POWERGATE_CPU0] = "cpu0",
2459 [TEGRA_POWERGATE_C0NC] = "c0nc",
2460 [TEGRA_POWERGATE_SOR] = "sor",
2461 [TEGRA_POWERGATE_DIS] = "dis",
2462 [TEGRA_POWERGATE_DISB] = "disb",
2463 [TEGRA_POWERGATE_XUSBA] = "xusba",
2464 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2465 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2466 [TEGRA_POWERGATE_VIC] = "vic",
2467 [TEGRA_POWERGATE_IRAM] = "iram",
2468 [TEGRA_POWERGATE_NVDEC] = "nvdec",
2469 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
2470 [TEGRA_POWERGATE_AUD] = "aud",
2471 [TEGRA_POWERGATE_DFD] = "dfd",
2472 [TEGRA_POWERGATE_VE2] = "ve2",
2473 };
2474
2475 static const u8 tegra210_cpu_powergates[] = {
2476 TEGRA_POWERGATE_CPU0,
2477 TEGRA_POWERGATE_CPU1,
2478 TEGRA_POWERGATE_CPU2,
2479 TEGRA_POWERGATE_CPU3,
2480 };
2481
2482 #define TEGRA210_IO_PAD_TABLE(_pad) \
2483 /* .id .dpd .voltage .name */ \
2484 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
2485 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2486 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
2487 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2488 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2489 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
2490 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
2491 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
2492 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
2493 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
2494 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2495 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
2496 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
2497 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2498 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2499 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2500 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2501 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
2502 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
2503 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
2504 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2505 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2506 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2507 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2508 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2509 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2510 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2511 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
2512 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
2513 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
2514 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
2515 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
2516 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
2517 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2518 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2519 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2520 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
2521 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
2522
2523 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
2524 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
2525 };
2526
2527 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
2528 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2529 };
2530
2531 static const struct tegra_pmc_soc tegra210_pmc_soc = {
2532 .num_powergates = ARRAY_SIZE(tegra210_powergates),
2533 .powergates = tegra210_powergates,
2534 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
2535 .cpu_powergates = tegra210_cpu_powergates,
2536 .has_tsense_reset = true,
2537 .has_gpu_clamps = true,
2538 .needs_mbist_war = true,
2539 .has_impl_33v_pwr = false,
2540 .maybe_tz_only = true,
2541 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
2542 .io_pads = tegra210_io_pads,
2543 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
2544 .pin_descs = tegra210_pin_descs,
2545 .regs = &tegra20_pmc_regs,
2546 .init = tegra20_pmc_init,
2547 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2548 .reset_sources = tegra210_reset_sources,
2549 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2550 .reset_levels = NULL,
2551 .num_reset_levels = 0,
2552 };
2553
2554 #define TEGRA186_IO_PAD_TABLE(_pad) \
2555 /* .id .dpd .voltage .name */ \
2556 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2557 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2558 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2559 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2560 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
2561 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
2562 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2563 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
2564 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2565 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2566 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2567 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
2568 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2569 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2570 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2571 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
2572 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
2573 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
2574 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2575 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
2576 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
2577 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
2578 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
2579 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
2580 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
2581 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
2582 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
2583 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
2584 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
2585 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
2586 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
2587 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
2588 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
2589 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
2590 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
2591 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
2592 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
2593 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
2594
2595 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
2596 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
2597 };
2598
2599 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
2600 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2601 };
2602
2603 static const struct tegra_pmc_regs tegra186_pmc_regs = {
2604 .scratch0 = 0x2000,
2605 .dpd_req = 0x74,
2606 .dpd_status = 0x78,
2607 .dpd2_req = 0x7c,
2608 .dpd2_status = 0x80,
2609 .rst_status = 0x70,
2610 .rst_source_shift = 0x2,
2611 .rst_source_mask = 0x3C,
2612 .rst_level_shift = 0x0,
2613 .rst_level_mask = 0x3,
2614 };
2615
2616 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2617 struct device_node *np,
2618 bool invert)
2619 {
2620 struct resource regs;
2621 void __iomem *wake;
2622 u32 value;
2623 int index;
2624
2625 index = of_property_match_string(np, "reg-names", "wake");
2626 if (index < 0) {
2627 dev_err(pmc->dev, "failed to find PMC wake registers\n");
2628 return;
2629 }
2630
2631 of_address_to_resource(np, index, &regs);
2632
2633 wake = ioremap_nocache(regs.start, resource_size(&regs));
2634 if (!wake) {
2635 dev_err(pmc->dev, "failed to map PMC wake registers\n");
2636 return;
2637 }
2638
2639 value = readl(wake + WAKE_AOWAKE_CTRL);
2640
2641 if (invert)
2642 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
2643 else
2644 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
2645
2646 writel(value, wake + WAKE_AOWAKE_CTRL);
2647
2648 iounmap(wake);
2649 }
2650
2651 static const struct tegra_wake_event tegra186_wake_events[] = {
2652 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
2653 TEGRA_WAKE_IRQ("rtc", 73, 10),
2654 };
2655
2656 static const struct tegra_pmc_soc tegra186_pmc_soc = {
2657 .num_powergates = 0,
2658 .powergates = NULL,
2659 .num_cpu_powergates = 0,
2660 .cpu_powergates = NULL,
2661 .has_tsense_reset = false,
2662 .has_gpu_clamps = false,
2663 .needs_mbist_war = false,
2664 .has_impl_33v_pwr = true,
2665 .maybe_tz_only = false,
2666 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
2667 .io_pads = tegra186_io_pads,
2668 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
2669 .pin_descs = tegra186_pin_descs,
2670 .regs = &tegra186_pmc_regs,
2671 .init = NULL,
2672 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2673 .reset_sources = tegra186_reset_sources,
2674 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2675 .reset_levels = tegra186_reset_levels,
2676 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2677 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2678 .wake_events = tegra186_wake_events,
2679 };
2680
2681 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2682 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2683 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2684 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2685 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2686 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2687 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2688 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2689 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2690 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2691 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2692 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2693 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2694 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2695 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2696 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2697 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2698 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2699 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2700 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2701 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2702 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2703 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2704 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2705 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2706 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2707 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2708 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2709 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2710 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2711 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2712 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2713 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2714 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2715 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2716 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2717 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2718 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2719 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2720 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2721 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2722 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2723 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2724 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2725 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2726 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2727 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2728 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2729 };
2730
2731 static const struct tegra_wake_event tegra194_wake_events[] = {
2732 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
2733 TEGRA_WAKE_IRQ("rtc", 73, 10),
2734 };
2735
2736 static const struct tegra_pmc_soc tegra194_pmc_soc = {
2737 .num_powergates = 0,
2738 .powergates = NULL,
2739 .num_cpu_powergates = 0,
2740 .cpu_powergates = NULL,
2741 .has_tsense_reset = false,
2742 .has_gpu_clamps = false,
2743 .needs_mbist_war = false,
2744 .has_impl_33v_pwr = false,
2745 .maybe_tz_only = false,
2746 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2747 .io_pads = tegra194_io_pads,
2748 .regs = &tegra186_pmc_regs,
2749 .init = NULL,
2750 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2751 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
2752 .wake_events = tegra194_wake_events,
2753 };
2754
2755 static const struct of_device_id tegra_pmc_match[] = {
2756 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2757 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2758 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2759 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2760 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2761 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2762 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2763 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2764 { }
2765 };
2766
2767 static struct platform_driver tegra_pmc_driver = {
2768 .driver = {
2769 .name = "tegra-pmc",
2770 .suppress_bind_attrs = true,
2771 .of_match_table = tegra_pmc_match,
2772 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2773 .pm = &tegra_pmc_pm_ops,
2774 #endif
2775 },
2776 .probe = tegra_pmc_probe,
2777 };
2778 builtin_platform_driver(tegra_pmc_driver);
2779
2780 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
2781 {
2782 u32 value, saved;
2783
2784 saved = readl(pmc->base + pmc->soc->regs->scratch0);
2785 value = saved ^ 0xffffffff;
2786
2787 if (value == 0xffffffff)
2788 value = 0xdeadbeef;
2789
2790 /* write pattern and read it back */
2791 writel(value, pmc->base + pmc->soc->regs->scratch0);
2792 value = readl(pmc->base + pmc->soc->regs->scratch0);
2793
2794 /* if we read all-zeroes, access is restricted to TZ only */
2795 if (value == 0) {
2796 pr_info("access to PMC is restricted to TZ\n");
2797 return true;
2798 }
2799
2800 /* restore original value */
2801 writel(saved, pmc->base + pmc->soc->regs->scratch0);
2802
2803 return false;
2804 }
2805
2806 /*
2807 * Early initialization to allow access to registers in the very early boot
2808 * process.
2809 */
2810 static int __init tegra_pmc_early_init(void)
2811 {
2812 const struct of_device_id *match;
2813 struct device_node *np;
2814 struct resource regs;
2815 unsigned int i;
2816 bool invert;
2817
2818 mutex_init(&pmc->powergates_lock);
2819
2820 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
2821 if (!np) {
2822 /*
2823 * Fall back to legacy initialization for 32-bit ARM only. All
2824 * 64-bit ARM device tree files for Tegra are required to have
2825 * a PMC node.
2826 *
2827 * This is for backwards-compatibility with old device trees
2828 * that didn't contain a PMC node. Note that in this case the
2829 * SoC data can't be matched and therefore powergating is
2830 * disabled.
2831 */
2832 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
2833 pr_warn("DT node not found, powergating disabled\n");
2834
2835 regs.start = 0x7000e400;
2836 regs.end = 0x7000e7ff;
2837 regs.flags = IORESOURCE_MEM;
2838
2839 pr_warn("Using memory region %pR\n", &regs);
2840 } else {
2841 /*
2842 * At this point we're not running on Tegra, so play
2843 * nice with multi-platform kernels.
2844 */
2845 return 0;
2846 }
2847 } else {
2848 /*
2849 * Extract information from the device tree if we've found a
2850 * matching node.
2851 */
2852 if (of_address_to_resource(np, 0, &regs) < 0) {
2853 pr_err("failed to get PMC registers\n");
2854 of_node_put(np);
2855 return -ENXIO;
2856 }
2857 }
2858
2859 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
2860 if (!pmc->base) {
2861 pr_err("failed to map PMC registers\n");
2862 of_node_put(np);
2863 return -ENXIO;
2864 }
2865
2866 if (np) {
2867 pmc->soc = match->data;
2868
2869 if (pmc->soc->maybe_tz_only)
2870 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
2871
2872 /* Create a bitmap of the available and valid partitions */
2873 for (i = 0; i < pmc->soc->num_powergates; i++)
2874 if (pmc->soc->powergates[i])
2875 set_bit(i, pmc->powergates_available);
2876
2877 /*
2878 * Invert the interrupt polarity if a PMC device tree node
2879 * exists and contains the nvidia,invert-interrupt property.
2880 */
2881 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
2882
2883 pmc->soc->setup_irq_polarity(pmc, np, invert);
2884
2885 of_node_put(np);
2886 }
2887
2888 return 0;
2889 }
2890 early_initcall(tegra_pmc_early_init);
Linux with added FPC-III support