arch/mips/ralink/rt288x.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <john@phrozen.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15
  16 #include <asm/mipsregs.h>
  17 #include <asm/mach-ralink/ralink_regs.h>
  18 #include <asm/mach-ralink/rt288x.h>
  19 #include <asm/mach-ralink/pinmux.h>
  20
  21 #include "common.h"
  22
  23 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
  24 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  25 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
  26 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  27 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  28 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  29 static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
  30
  31 static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
  32         GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
  33         GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
  34         GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
  35         GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
  36         GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
  37         GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
  38         GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
  39         { 0 }
  40 };
  41
  42 void __init ralink_clk_init(void)
  43 {
  44         unsigned long cpu_rate, wmac_rate = 40000000;
  45         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  46         t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  47
  48         switch (t) {
  49         case SYSTEM_CONFIG_CPUCLK_250:
  50                 cpu_rate = 250000000;
  51                 break;
  52         case SYSTEM_CONFIG_CPUCLK_266:
  53                 cpu_rate = 266666667;
  54                 break;
  55         case SYSTEM_CONFIG_CPUCLK_280:
  56                 cpu_rate = 280000000;
  57                 break;
  58         case SYSTEM_CONFIG_CPUCLK_300:
  59                 cpu_rate = 300000000;
  60                 break;
  61         }
  62
  63         ralink_clk_add("cpu", cpu_rate);
  64         ralink_clk_add("300100.timer", cpu_rate / 2);
  65         ralink_clk_add("300120.watchdog", cpu_rate / 2);
  66         ralink_clk_add("300500.uart", cpu_rate / 2);
  67         ralink_clk_add("300900.i2c", cpu_rate / 2);
  68         ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  69         ralink_clk_add("400000.ethernet", cpu_rate / 2);
  70         ralink_clk_add("480000.wmac", wmac_rate);
  71 }
  72
  73 void __init ralink_of_remap(void)
  74 {
  75         rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
  76         rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
  77
  78         if (!rt_sysc_membase || !rt_memc_membase)
  79                 panic("Failed to remap core resources");
  80 }
  81
  82 void prom_soc_init(struct ralink_soc_info *soc_info)
  83 {
  84         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
  85         const char *name;
  86         u32 n0;
  87         u32 n1;
  88         u32 id;
  89
  90         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  91         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  92         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  93
  94         if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
  95                 soc_info->compatible = "ralink,r2880-soc";
  96                 name = "RT2880";
  97         } else {
  98                 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  99         }
 100
 101         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 102                 "Ralink %s id:%u rev:%u",
 103                 name,
 104                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 105                 (id & CHIP_ID_REV_MASK));
 106
 107         soc_info->mem_base = RT2880_SDRAM_BASE;
 108         soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
 109         soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
 110
 111         rt2880_pinmux_data = rt2880_pinmux_data_act;
 112         ralink_soc = RT2880_SOC;
 113 }