| blob | 04c62acaf5a906fef0e30850449632e0bf51b24f |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a7";
26 device_type = "cpu";
27 reg = <1>;
28 };
29 };
31 psci {
32 compatible = "arm,psci";
33 method = "smc";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
36 };
38 aliases {
39 gpio0 = &gpioa;
40 gpio1 = &gpiob;
41 gpio2 = &gpioc;
42 gpio3 = &gpiod;
43 gpio4 = &gpioe;
44 gpio5 = &gpiof;
45 gpio6 = &gpiog;
46 gpio7 = &gpioh;
47 gpio8 = &gpioi;
48 gpio9 = &gpioj;
49 gpio10 = &gpiok;
50 };
52 intc: interrupt-controller@a0021000 {
53 compatible = "arm,cortex-a7-gic";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0xa0021000 0x1000>,
57 <0xa0022000 0x2000>;
58 };
60 timer {
61 compatible = "arm,armv7-timer";
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
66 interrupt-parent = <&intc>;
67 };
69 clocks {
70 clk_hse: clk-hse {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <24000000>;
74 };
76 clk_hsi: clk-hsi {
77 #clock-cells = <0>;
78 compatible = "fixed-clock";
79 clock-frequency = <64000000>;
80 };
82 clk_lse: clk-lse {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 };
88 clk_lsi: clk-lsi {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <32000>;
92 };
94 clk_csi: clk-csi {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 clock-frequency = <4000000>;
98 };
99 };
101 soc {
102 compatible = "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 interrupt-parent = <&intc>;
106 ranges;
108 timers2: timer@40000000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "st,stm32-timers";
112 reg = <0x40000000 0x400>;
113 clocks = <&rcc TIM2_K>;
114 clock-names = "int";
115 status = "disabled";
117 pwm {
118 compatible = "st,stm32-pwm";
119 status = "disabled";
120 };
122 timer@1 {
123 compatible = "st,stm32h7-timer-trigger";
124 reg = <1>;
125 status = "disabled";
126 };
127 };
129 timers3: timer@40001000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "st,stm32-timers";
133 reg = <0x40001000 0x400>;
134 clocks = <&rcc TIM3_K>;
135 clock-names = "int";
136 status = "disabled";
138 pwm {
139 compatible = "st,stm32-pwm";
140 status = "disabled";
141 };
143 timer@2 {
144 compatible = "st,stm32h7-timer-trigger";
145 reg = <2>;
146 status = "disabled";
147 };
148 };
150 timers4: timer@40002000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "st,stm32-timers";
154 reg = <0x40002000 0x400>;
155 clocks = <&rcc TIM4_K>;
156 clock-names = "int";
157 status = "disabled";
159 pwm {
160 compatible = "st,stm32-pwm";
161 status = "disabled";
162 };
164 timer@3 {
165 compatible = "st,stm32h7-timer-trigger";
166 reg = <3>;
167 status = "disabled";
168 };
169 };
171 timers5: timer@40003000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "st,stm32-timers";
175 reg = <0x40003000 0x400>;
176 clocks = <&rcc TIM5_K>;
177 clock-names = "int";
178 status = "disabled";
180 pwm {
181 compatible = "st,stm32-pwm";
182 status = "disabled";
183 };
185 timer@4 {
186 compatible = "st,stm32h7-timer-trigger";
187 reg = <4>;
188 status = "disabled";
189 };
190 };
192 timers6: timer@40004000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "st,stm32-timers";
196 reg = <0x40004000 0x400>;
197 clocks = <&rcc TIM6_K>;
198 clock-names = "int";
199 status = "disabled";
201 timer@5 {
202 compatible = "st,stm32h7-timer-trigger";
203 reg = <5>;
204 status = "disabled";
205 };
206 };
208 timers7: timer@40005000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "st,stm32-timers";
212 reg = <0x40005000 0x400>;
213 clocks = <&rcc TIM7_K>;
214 clock-names = "int";
215 status = "disabled";
217 timer@6 {
218 compatible = "st,stm32h7-timer-trigger";
219 reg = <6>;
220 status = "disabled";
221 };
222 };
224 timers12: timer@40006000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "st,stm32-timers";
228 reg = <0x40006000 0x400>;
229 clocks = <&rcc TIM12_K>;
230 clock-names = "int";
231 status = "disabled";
233 pwm {
234 compatible = "st,stm32-pwm";
235 status = "disabled";
236 };
238 timer@11 {
239 compatible = "st,stm32h7-timer-trigger";
240 reg = <11>;
241 status = "disabled";
242 };
243 };
245 timers13: timer@40007000 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
249 reg = <0x40007000 0x400>;
250 clocks = <&rcc TIM13_K>;
251 clock-names = "int";
252 status = "disabled";
254 pwm {
255 compatible = "st,stm32-pwm";
256 status = "disabled";
257 };
259 timer@12 {
260 compatible = "st,stm32h7-timer-trigger";
261 reg = <12>;
262 status = "disabled";
263 };
264 };
266 timers14: timer@40008000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "st,stm32-timers";
270 reg = <0x40008000 0x400>;
271 clocks = <&rcc TIM14_K>;
272 clock-names = "int";
273 status = "disabled";
275 pwm {
276 compatible = "st,stm32-pwm";
277 status = "disabled";
278 };
280 timer@13 {
281 compatible = "st,stm32h7-timer-trigger";
282 reg = <13>;
283 status = "disabled";
284 };
285 };
287 lptimer1: timer@40009000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "st,stm32-lptimer";
291 reg = <0x40009000 0x400>;
292 clocks = <&rcc LPTIM1_K>;
293 clock-names = "mux";
294 status = "disabled";
296 pwm {
297 compatible = "st,stm32-pwm-lp";
298 #pwm-cells = <3>;
299 status = "disabled";
300 };
302 trigger@0 {
303 compatible = "st,stm32-lptimer-trigger";
304 reg = <0>;
305 status = "disabled";
306 };
308 counter {
309 compatible = "st,stm32-lptimer-counter";
310 status = "disabled";
311 };
312 };
314 usart2: serial@4000e000 {
315 compatible = "st,stm32h7-uart";
316 reg = <0x4000e000 0x400>;
317 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&rcc USART2_K>;
319 status = "disabled";
320 };
322 usart3: serial@4000f000 {
323 compatible = "st,stm32h7-uart";
324 reg = <0x4000f000 0x400>;
325 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&rcc USART3_K>;
327 status = "disabled";
328 };
330 uart4: serial@40010000 {
331 compatible = "st,stm32h7-uart";
332 reg = <0x40010000 0x400>;
333 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&rcc UART4_K>;
335 status = "disabled";
336 };
338 uart5: serial@40011000 {
339 compatible = "st,stm32h7-uart";
340 reg = <0x40011000 0x400>;
341 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&rcc UART5_K>;
343 status = "disabled";
344 };
346 i2c1: i2c@40012000 {
347 compatible = "st,stm32f7-i2c";
348 reg = <0x40012000 0x400>;
349 interrupt-names = "event", "error";
350 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&rcc I2C1_K>;
353 resets = <&rcc I2C1_R>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 status = "disabled";
357 };
359 i2c2: i2c@40013000 {
360 compatible = "st,stm32f7-i2c";
361 reg = <0x40013000 0x400>;
362 interrupt-names = "event", "error";
363 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&rcc I2C2_K>;
366 resets = <&rcc I2C2_R>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 status = "disabled";
370 };
372 i2c3: i2c@40014000 {
373 compatible = "st,stm32f7-i2c";
374 reg = <0x40014000 0x400>;
375 interrupt-names = "event", "error";
376 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&rcc I2C3_K>;
379 resets = <&rcc I2C3_R>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
385 i2c5: i2c@40015000 {
386 compatible = "st,stm32f7-i2c";
387 reg = <0x40015000 0x400>;
388 interrupt-names = "event", "error";
389 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&rcc I2C5_K>;
392 resets = <&rcc I2C5_R>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395 status = "disabled";
396 };
398 cec: cec@40016000 {
399 compatible = "st,stm32-cec";
400 reg = <0x40016000 0x400>;
401 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&rcc CEC_K>, <&clk_lse>;
403 clock-names = "cec", "hdmi-cec";
404 status = "disabled";
405 };
407 dac: dac@40017000 {
408 compatible = "st,stm32h7-dac-core";
409 reg = <0x40017000 0x400>;
410 clocks = <&rcc DAC12>;
411 clock-names = "pclk";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 status = "disabled";
416 dac1: dac@1 {
417 compatible = "st,stm32-dac";
418 #io-channels-cells = <1>;
419 reg = <1>;
420 status = "disabled";
421 };
423 dac2: dac@2 {
424 compatible = "st,stm32-dac";
425 #io-channels-cells = <1>;
426 reg = <2>;
427 status = "disabled";
428 };
429 };
431 uart7: serial@40018000 {
432 compatible = "st,stm32h7-uart";
433 reg = <0x40018000 0x400>;
434 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&rcc UART7_K>;
436 status = "disabled";
437 };
439 uart8: serial@40019000 {
440 compatible = "st,stm32h7-uart";
441 reg = <0x40019000 0x400>;
442 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&rcc UART8_K>;
444 status = "disabled";
445 };
447 timers1: timer@44000000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "st,stm32-timers";
451 reg = <0x44000000 0x400>;
452 clocks = <&rcc TIM1_K>;
453 clock-names = "int";
454 status = "disabled";
456 pwm {
457 compatible = "st,stm32-pwm";
458 status = "disabled";
459 };
461 timer@0 {
462 compatible = "st,stm32h7-timer-trigger";
463 reg = <0>;
464 status = "disabled";
465 };
466 };
468 timers8: timer@44001000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "st,stm32-timers";
472 reg = <0x44001000 0x400>;
473 clocks = <&rcc TIM8_K>;
474 clock-names = "int";
475 status = "disabled";
477 pwm {
478 compatible = "st,stm32-pwm";
479 status = "disabled";
480 };
482 timer@7 {
483 compatible = "st,stm32h7-timer-trigger";
484 reg = <7>;
485 status = "disabled";
486 };
487 };
489 usart6: serial@44003000 {
490 compatible = "st,stm32h7-uart";
491 reg = <0x44003000 0x400>;
492 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&rcc USART6_K>;
494 status = "disabled";
495 };
497 timers15: timer@44006000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "st,stm32-timers";
501 reg = <0x44006000 0x400>;
502 clocks = <&rcc TIM15_K>;
503 clock-names = "int";
504 status = "disabled";
506 pwm {
507 compatible = "st,stm32-pwm";
508 status = "disabled";
509 };
511 timer@14 {
512 compatible = "st,stm32h7-timer-trigger";
513 reg = <14>;
514 status = "disabled";
515 };
516 };
518 timers16: timer@44007000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "st,stm32-timers";
522 reg = <0x44007000 0x400>;
523 clocks = <&rcc TIM16_K>;
524 clock-names = "int";
525 status = "disabled";
527 pwm {
528 compatible = "st,stm32-pwm";
529 status = "disabled";
530 };
531 timer@15 {
532 compatible = "st,stm32h7-timer-trigger";
533 reg = <15>;
534 status = "disabled";
535 };
536 };
538 timers17: timer@44008000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "st,stm32-timers";
542 reg = <0x44008000 0x400>;
543 clocks = <&rcc TIM17_K>;
544 clock-names = "int";
545 status = "disabled";
547 pwm {
548 compatible = "st,stm32-pwm";
549 status = "disabled";
550 };
552 timer@16 {
553 compatible = "st,stm32h7-timer-trigger";
554 reg = <16>;
555 status = "disabled";
556 };
557 };
559 m_can1: can@4400e000 {
560 compatible = "bosch,m_can";
561 reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
562 reg-names = "m_can", "message_ram";
563 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "int0", "int1";
566 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
567 clock-names = "hclk", "cclk";
568 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
569 status = "disabled";
570 };
572 m_can2: can@4400f000 {
573 compatible = "bosch,m_can";
574 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
575 reg-names = "m_can", "message_ram";
576 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-names = "int0", "int1";
579 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
580 clock-names = "hclk", "cclk";
581 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
582 status = "disabled";
583 };
585 dma1: dma@48000000 {
586 compatible = "st,stm32-dma";
587 reg = <0x48000000 0x400>;
588 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&rcc DMA1>;
597 #dma-cells = <4>;
598 st,mem2mem;
599 dma-requests = <8>;
600 };
602 dma2: dma@48001000 {
603 compatible = "st,stm32-dma";
604 reg = <0x48001000 0x400>;
605 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&rcc DMA2>;
614 #dma-cells = <4>;
615 st,mem2mem;
616 dma-requests = <8>;
617 };
619 dmamux1: dma-router@48002000 {
620 compatible = "st,stm32h7-dmamux";
621 reg = <0x48002000 0x1c>;
622 #dma-cells = <3>;
623 dma-requests = <128>;
624 dma-masters = <&dma1 &dma2>;
625 dma-channels = <16>;
626 clocks = <&rcc DMAMUX>;
627 };
629 usbotg_hs: usb-otg@49000000 {
630 compatible = "snps,dwc2";
631 reg = <0x49000000 0x10000>;
632 clocks = <&rcc USBO_K>;
633 clock-names = "otg";
634 resets = <&rcc USBO_R>;
635 reset-names = "dwc2";
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
637 g-rx-fifo-size = <256>;
638 g-np-tx-fifo-size = <32>;
639 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
640 dr_mode = "otg";
641 status = "disabled";
642 };
644 rcc: rcc@50000000 {
645 compatible = "st,stm32mp1-rcc", "syscon";
646 reg = <0x50000000 0x1000>;
647 #clock-cells = <1>;
648 #reset-cells = <1>;
649 };
651 exti: interrupt-controller@5000d000 {
652 compatible = "st,stm32mp1-exti", "syscon";
653 interrupt-controller;
654 #interrupt-cells = <2>;
655 reg = <0x5000d000 0x400>;
656 };
658 lptimer2: timer@50021000 {
659 #address-cells = <1>;
660 #size-cells = <0>;
661 compatible = "st,stm32-lptimer";
662 reg = <0x50021000 0x400>;
663 clocks = <&rcc LPTIM2_K>;
664 clock-names = "mux";
665 status = "disabled";
667 pwm {
668 compatible = "st,stm32-pwm-lp";
669 #pwm-cells = <3>;
670 status = "disabled";
671 };
673 trigger@1 {
674 compatible = "st,stm32-lptimer-trigger";
675 reg = <1>;
676 status = "disabled";
677 };
679 counter {
680 compatible = "st,stm32-lptimer-counter";
681 status = "disabled";
682 };
683 };
685 lptimer3: timer@50022000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "st,stm32-lptimer";
689 reg = <0x50022000 0x400>;
690 clocks = <&rcc LPTIM3_K>;
691 clock-names = "mux";
692 status = "disabled";
694 pwm {
695 compatible = "st,stm32-pwm-lp";
696 #pwm-cells = <3>;
697 status = "disabled";
698 };
700 trigger@2 {
701 compatible = "st,stm32-lptimer-trigger";
702 reg = <2>;
703 status = "disabled";
704 };
705 };
707 lptimer4: timer@50023000 {
708 compatible = "st,stm32-lptimer";
709 reg = <0x50023000 0x400>;
710 clocks = <&rcc LPTIM4_K>;
711 clock-names = "mux";
712 status = "disabled";
714 pwm {
715 compatible = "st,stm32-pwm-lp";
716 #pwm-cells = <3>;
717 status = "disabled";
718 };
719 };
721 lptimer5: timer@50024000 {
722 compatible = "st,stm32-lptimer";
723 reg = <0x50024000 0x400>;
724 clocks = <&rcc LPTIM5_K>;
725 clock-names = "mux";
726 status = "disabled";
728 pwm {
729 compatible = "st,stm32-pwm-lp";
730 #pwm-cells = <3>;
731 status = "disabled";
732 };
733 };
735 vrefbuf: vrefbuf@50025000 {
736 compatible = "st,stm32-vrefbuf";
737 reg = <0x50025000 0x8>;
738 regulator-min-microvolt = <1500000>;
739 regulator-max-microvolt = <2500000>;
740 clocks = <&rcc VREF>;
741 status = "disabled";
742 };
744 cryp1: cryp@54001000 {
745 compatible = "st,stm32mp1-cryp";
746 reg = <0x54001000 0x400>;
747 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&rcc CRYP1>;
749 resets = <&rcc CRYP1_R>;
750 status = "disabled";
751 };
753 hash1: hash@54002000 {
754 compatible = "st,stm32f756-hash";
755 reg = <0x54002000 0x400>;
756 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&rcc HASH1>;
758 resets = <&rcc HASH1_R>;
759 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
760 dma-names = "in";
761 dma-maxburst = <2>;
762 status = "disabled";
763 };
765 rng1: rng@54003000 {
766 compatible = "st,stm32-rng";
767 reg = <0x54003000 0x400>;
768 clocks = <&rcc RNG1_K>;
769 resets = <&rcc RNG1_R>;
770 status = "disabled";
771 };
773 mdma1: dma@58000000 {
774 compatible = "st,stm32h7-mdma";
775 reg = <0x58000000 0x1000>;
776 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&rcc MDMA>;
778 #dma-cells = <5>;
779 dma-channels = <32>;
780 dma-requests = <48>;
781 };
783 qspi: qspi@58003000 {
784 compatible = "st,stm32f469-qspi";
785 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
786 reg-names = "qspi", "qspi_mm";
787 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&rcc QSPI_K>;
789 resets = <&rcc QSPI_R>;
790 status = "disabled";
791 };
793 crc1: crc@58009000 {
794 compatible = "st,stm32f7-crc";
795 reg = <0x58009000 0x400>;
796 clocks = <&rcc CRC1>;
797 status = "disabled";
798 };
800 usbh_ohci: usbh-ohci@5800c000 {
801 compatible = "generic-ohci";
802 reg = <0x5800c000 0x1000>;
803 clocks = <&rcc USBH>;
804 resets = <&rcc USBH_R>;
805 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
806 status = "disabled";
807 };
809 usbh_ehci: usbh-ehci@5800d000 {
810 compatible = "generic-ehci";
811 reg = <0x5800d000 0x1000>;
812 clocks = <&rcc USBH>;
813 resets = <&rcc USBH_R>;
814 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
815 companion = <&usbh_ohci>;
816 status = "disabled";
817 };
819 dsi: dsi@5a000000 {
820 compatible = "st,stm32-dsi";
821 reg = <0x5a000000 0x800>;
822 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
823 clock-names = "pclk", "ref", "px_clk";
824 resets = <&rcc DSI_R>;
825 reset-names = "apb";
826 status = "disabled";
827 };
829 ltdc: display-controller@5a001000 {
830 compatible = "st,stm32-ltdc";
831 reg = <0x5a001000 0x400>;
832 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&rcc LTDC_PX>;
835 clock-names = "lcd";
836 resets = <&rcc LTDC_R>;
837 status = "disabled";
838 };
840 usbphyc: usbphyc@5a006000 {
841 #address-cells = <1>;
842 #size-cells = <0>;
843 compatible = "st,stm32mp1-usbphyc";
844 reg = <0x5a006000 0x1000>;
845 clocks = <&rcc USBPHY_K>;
846 resets = <&rcc USBPHY_R>;
847 status = "disabled";
849 usbphyc_port0: usb-phy@0 {
850 #phy-cells = <0>;
851 reg = <0>;
852 };
854 usbphyc_port1: usb-phy@1 {
855 #phy-cells = <1>;
856 reg = <1>;
857 };
858 };
860 usart1: serial@5c000000 {
861 compatible = "st,stm32h7-uart";
862 reg = <0x5c000000 0x400>;
863 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&rcc USART1_K>;
865 status = "disabled";
866 };
868 i2c4: i2c@5c002000 {
869 compatible = "st,stm32f7-i2c";
870 reg = <0x5c002000 0x400>;
871 interrupt-names = "event", "error";
872 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&rcc I2C4_K>;
875 resets = <&rcc I2C4_R>;
876 #address-cells = <1>;
877 #size-cells = <0>;
878 status = "disabled";
879 };
881 rtc: rtc@5c004000 {
882 compatible = "st,stm32mp1-rtc";
883 reg = <0x5c004000 0x400>;
884 clocks = <&rcc RTCAPB>, <&rcc RTC>;
885 clock-names = "pclk", "rtc_ck";
886 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
887 status = "disabled";
888 };
890 i2c6: i2c@5c009000 {
891 compatible = "st,stm32f7-i2c";
892 reg = <0x5c009000 0x400>;
893 interrupt-names = "event", "error";
894 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&rcc I2C6_K>;
897 resets = <&rcc I2C6_R>;
898 #address-cells = <1>;
899 #size-cells = <0>;
900 status = "disabled";
901 };
902 };
903 };