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netxen: fix netxen_nic_poll() logic
[linux/fpc-iii.git] / sound / firewire / dice.c
blobe3a04d69c85363dfffdc6bebf5400b95cff401fa
1 /*
2 * TC Applied Technologies Digital Interface Communications Engine driver
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
6 */
7
8 #include <linux/compat.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firewire.h>
13 #include <linux/firewire-constants.h>
14 #include <linux/jiffies.h>
15 #include <linux/module.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/mutex.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/wait.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/firewire.h>
24 #include <sound/hwdep.h>
25 #include <sound/info.h>
26 #include <sound/initval.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include "amdtp.h"
30 #include "iso-resources.h"
31 #include "lib.h"
32 #include "dice-interface.h"
33
34
35 struct dice {
36 struct snd_card *card;
37 struct fw_unit *unit;
38 spinlock_t lock;
39 struct mutex mutex;
40 unsigned int global_offset;
41 unsigned int rx_offset;
42 unsigned int clock_caps;
43 unsigned int rx_channels[3];
44 unsigned int rx_midi_ports[3];
45 struct fw_address_handler notification_handler;
46 int owner_generation;
47 int dev_lock_count; /* > 0 driver, < 0 userspace */
48 bool dev_lock_changed;
49 bool global_enabled;
50 struct completion clock_accepted;
51 wait_queue_head_t hwdep_wait;
52 u32 notification_bits;
53 struct fw_iso_resources resources;
54 struct amdtp_stream stream;
55 };
56
57 MODULE_DESCRIPTION("DICE driver");
58 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
59 MODULE_LICENSE("GPL v2");
60
61 static const unsigned int dice_rates[] = {
62 /* mode 0 */
63 [0] = 32000,
64 [1] = 44100,
65 [2] = 48000,
66 /* mode 1 */
67 [3] = 88200,
68 [4] = 96000,
69 /* mode 2 */
70 [5] = 176400,
71 [6] = 192000,
72 };
73
74 static unsigned int rate_to_index(unsigned int rate)
75 {
76 unsigned int i;
77
78 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
79 if (dice_rates[i] == rate)
80 return i;
81
82 return 0;
83 }
84
85 static unsigned int rate_index_to_mode(unsigned int rate_index)
86 {
87 return ((int)rate_index - 1) / 2;
88 }
89
90 static void dice_lock_changed(struct dice *dice)
91 {
92 dice->dev_lock_changed = true;
93 wake_up(&dice->hwdep_wait);
94 }
95
96 static int dice_try_lock(struct dice *dice)
97 {
98 int err;
99
100 spin_lock_irq(&dice->lock);
101
102 if (dice->dev_lock_count < 0) {
103 err = -EBUSY;
104 goto out;
105 }
106
107 if (dice->dev_lock_count++ == 0)
108 dice_lock_changed(dice);
109 err = 0;
110
111 out:
112 spin_unlock_irq(&dice->lock);
113
114 return err;
115 }
116
117 static void dice_unlock(struct dice *dice)
118 {
119 spin_lock_irq(&dice->lock);
120
121 if (WARN_ON(dice->dev_lock_count <= 0))
122 goto out;
123
124 if (--dice->dev_lock_count == 0)
125 dice_lock_changed(dice);
126
127 out:
128 spin_unlock_irq(&dice->lock);
129 }
130
131 static inline u64 global_address(struct dice *dice, unsigned int offset)
132 {
133 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
134 }
135
136 // TODO: rx index
137 static inline u64 rx_address(struct dice *dice, unsigned int offset)
138 {
139 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
140 }
141
142 static int dice_owner_set(struct dice *dice)
143 {
144 struct fw_device *device = fw_parent_device(dice->unit);
145 __be64 *buffer;
146 int err, errors = 0;
147
148 buffer = kmalloc(2 * 8, GFP_KERNEL);
149 if (!buffer)
150 return -ENOMEM;
151
152 for (;;) {
153 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
154 buffer[1] = cpu_to_be64(
155 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
156 dice->notification_handler.offset);
157
158 dice->owner_generation = device->generation;
159 smp_rmb(); /* node_id vs. generation */
160 err = snd_fw_transaction(dice->unit,
161 TCODE_LOCK_COMPARE_SWAP,
162 global_address(dice, GLOBAL_OWNER),
163 buffer, 2 * 8,
164 FW_FIXED_GENERATION |
165 dice->owner_generation);
166
167 if (err == 0) {
168 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
169 dev_err(&dice->unit->device,
170 "device is already in use\n");
171 err = -EBUSY;
172 }
173 break;
174 }
175 if (err != -EAGAIN || ++errors >= 3)
176 break;
177
178 msleep(20);
179 }
180
181 kfree(buffer);
182
183 return err;
184 }
185
186 static int dice_owner_update(struct dice *dice)
187 {
188 struct fw_device *device = fw_parent_device(dice->unit);
189 __be64 *buffer;
190 int err;
191
192 if (dice->owner_generation == -1)
193 return 0;
194
195 buffer = kmalloc(2 * 8, GFP_KERNEL);
196 if (!buffer)
197 return -ENOMEM;
198
199 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
200 buffer[1] = cpu_to_be64(
201 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
202 dice->notification_handler.offset);
203
204 dice->owner_generation = device->generation;
205 smp_rmb(); /* node_id vs. generation */
206 err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
207 global_address(dice, GLOBAL_OWNER),
208 buffer, 2 * 8,
209 FW_FIXED_GENERATION | dice->owner_generation);
210
211 if (err == 0) {
212 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
213 dev_err(&dice->unit->device,
214 "device is already in use\n");
215 err = -EBUSY;
216 }
217 } else if (err == -EAGAIN) {
218 err = 0; /* try again later */
219 }
220
221 kfree(buffer);
222
223 if (err < 0)
224 dice->owner_generation = -1;
225
226 return err;
227 }
228
229 static void dice_owner_clear(struct dice *dice)
230 {
231 struct fw_device *device = fw_parent_device(dice->unit);
232 __be64 *buffer;
233
234 buffer = kmalloc(2 * 8, GFP_KERNEL);
235 if (!buffer)
236 return;
237
238 buffer[0] = cpu_to_be64(
239 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
240 dice->notification_handler.offset);
241 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
242 snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
243 global_address(dice, GLOBAL_OWNER),
244 buffer, 2 * 8, FW_QUIET |
245 FW_FIXED_GENERATION | dice->owner_generation);
246
247 kfree(buffer);
248
249 dice->owner_generation = -1;
250 }
251
252 static int dice_enable_set(struct dice *dice)
253 {
254 __be32 value;
255 int err;
256
257 value = cpu_to_be32(1);
258 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
259 global_address(dice, GLOBAL_ENABLE),
260 &value, 4,
261 FW_FIXED_GENERATION | dice->owner_generation);
262 if (err < 0)
263 return err;
264
265 dice->global_enabled = true;
266
267 return 0;
268 }
269
270 static void dice_enable_clear(struct dice *dice)
271 {
272 __be32 value;
273
274 if (!dice->global_enabled)
275 return;
276
277 value = 0;
278 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
279 global_address(dice, GLOBAL_ENABLE),
280 &value, 4, FW_QUIET |
281 FW_FIXED_GENERATION | dice->owner_generation);
282
283 dice->global_enabled = false;
284 }
285
286 static void dice_notification(struct fw_card *card, struct fw_request *request,
287 int tcode, int destination, int source,
288 int generation, unsigned long long offset,
289 void *data, size_t length, void *callback_data)
290 {
291 struct dice *dice = callback_data;
292 u32 bits;
293 unsigned long flags;
294
295 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
296 fw_send_response(card, request, RCODE_TYPE_ERROR);
297 return;
298 }
299 if ((offset & 3) != 0) {
300 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
301 return;
302 }
303
304 bits = be32_to_cpup(data);
305
306 spin_lock_irqsave(&dice->lock, flags);
307 dice->notification_bits |= bits;
308 spin_unlock_irqrestore(&dice->lock, flags);
309
310 fw_send_response(card, request, RCODE_COMPLETE);
311
312 if (bits & NOTIFY_CLOCK_ACCEPTED)
313 complete(&dice->clock_accepted);
314 wake_up(&dice->hwdep_wait);
315 }
316
317 static int dice_rate_constraint(struct snd_pcm_hw_params *params,
318 struct snd_pcm_hw_rule *rule)
319 {
320 struct dice *dice = rule->private;
321 const struct snd_interval *channels =
322 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
323 struct snd_interval *rate =
324 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
325 struct snd_interval allowed_rates = {
326 .min = UINT_MAX, .max = 0, .integer = 1
327 };
328 unsigned int i, mode;
329
330 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
331 mode = rate_index_to_mode(i);
332 if ((dice->clock_caps & (1 << i)) &&
333 snd_interval_test(channels, dice->rx_channels[mode])) {
334 allowed_rates.min = min(allowed_rates.min,
335 dice_rates[i]);
336 allowed_rates.max = max(allowed_rates.max,
337 dice_rates[i]);
338 }
339 }
340
341 return snd_interval_refine(rate, &allowed_rates);
342 }
343
344 static int dice_channels_constraint(struct snd_pcm_hw_params *params,
345 struct snd_pcm_hw_rule *rule)
346 {
347 struct dice *dice = rule->private;
348 const struct snd_interval *rate =
349 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
350 struct snd_interval *channels =
351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
352 struct snd_interval allowed_channels = {
353 .min = UINT_MAX, .max = 0, .integer = 1
354 };
355 unsigned int i, mode;
356
357 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
358 if ((dice->clock_caps & (1 << i)) &&
359 snd_interval_test(rate, dice_rates[i])) {
360 mode = rate_index_to_mode(i);
361 allowed_channels.min = min(allowed_channels.min,
362 dice->rx_channels[mode]);
363 allowed_channels.max = max(allowed_channels.max,
364 dice->rx_channels[mode]);
365 }
366
367 return snd_interval_refine(channels, &allowed_channels);
368 }
369
370 static int dice_open(struct snd_pcm_substream *substream)
371 {
372 static const struct snd_pcm_hardware hardware = {
373 .info = SNDRV_PCM_INFO_MMAP |
374 SNDRV_PCM_INFO_MMAP_VALID |
375 SNDRV_PCM_INFO_BATCH |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_BLOCK_TRANSFER,
378 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
379 .channels_min = UINT_MAX,
380 .channels_max = 0,
381 .buffer_bytes_max = 16 * 1024 * 1024,
382 .period_bytes_min = 1,
383 .period_bytes_max = UINT_MAX,
384 .periods_min = 1,
385 .periods_max = UINT_MAX,
386 };
387 struct dice *dice = substream->private_data;
388 struct snd_pcm_runtime *runtime = substream->runtime;
389 unsigned int i;
390 int err;
391
392 err = dice_try_lock(dice);
393 if (err < 0)
394 goto error;
395
396 runtime->hw = hardware;
397
398 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
399 if (dice->clock_caps & (1 << i))
400 runtime->hw.rates |=
401 snd_pcm_rate_to_rate_bit(dice_rates[i]);
402 snd_pcm_limit_hw_rates(runtime);
403
404 for (i = 0; i < 3; ++i)
405 if (dice->rx_channels[i]) {
406 runtime->hw.channels_min = min(runtime->hw.channels_min,
407 dice->rx_channels[i]);
408 runtime->hw.channels_max = max(runtime->hw.channels_max,
409 dice->rx_channels[i]);
410 }
411
412 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
413 dice_rate_constraint, dice,
414 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
415 if (err < 0)
416 goto err_lock;
417 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
418 dice_channels_constraint, dice,
419 SNDRV_PCM_HW_PARAM_RATE, -1);
420 if (err < 0)
421 goto err_lock;
422
423 err = amdtp_stream_add_pcm_hw_constraints(&dice->stream, runtime);
424 if (err < 0)
425 goto err_lock;
426
427 return 0;
428
429 err_lock:
430 dice_unlock(dice);
431 error:
432 return err;
433 }
434
435 static int dice_close(struct snd_pcm_substream *substream)
436 {
437 struct dice *dice = substream->private_data;
438
439 dice_unlock(dice);
440
441 return 0;
442 }
443
444 static int dice_stream_start_packets(struct dice *dice)
445 {
446 int err;
447
448 if (amdtp_stream_running(&dice->stream))
449 return 0;
450
451 err = amdtp_stream_start(&dice->stream, dice->resources.channel,
452 fw_parent_device(dice->unit)->max_speed);
453 if (err < 0)
454 return err;
455
456 err = dice_enable_set(dice);
457 if (err < 0) {
458 amdtp_stream_stop(&dice->stream);
459 return err;
460 }
461
462 return 0;
463 }
464
465 static int dice_stream_start(struct dice *dice)
466 {
467 __be32 channel;
468 int err;
469
470 if (!dice->resources.allocated) {
471 err = fw_iso_resources_allocate(&dice->resources,
472 amdtp_stream_get_max_payload(&dice->stream),
473 fw_parent_device(dice->unit)->max_speed);
474 if (err < 0)
475 goto error;
476
477 channel = cpu_to_be32(dice->resources.channel);
478 err = snd_fw_transaction(dice->unit,
479 TCODE_WRITE_QUADLET_REQUEST,
480 rx_address(dice, RX_ISOCHRONOUS),
481 &channel, 4, 0);
482 if (err < 0)
483 goto err_resources;
484 }
485
486 err = dice_stream_start_packets(dice);
487 if (err < 0)
488 goto err_rx_channel;
489
490 return 0;
491
492 err_rx_channel:
493 channel = cpu_to_be32((u32)-1);
494 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
495 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
496 err_resources:
497 fw_iso_resources_free(&dice->resources);
498 error:
499 return err;
500 }
501
502 static void dice_stream_stop_packets(struct dice *dice)
503 {
504 if (amdtp_stream_running(&dice->stream)) {
505 dice_enable_clear(dice);
506 amdtp_stream_stop(&dice->stream);
507 }
508 }
509
510 static void dice_stream_stop(struct dice *dice)
511 {
512 __be32 channel;
513
514 dice_stream_stop_packets(dice);
515
516 if (!dice->resources.allocated)
517 return;
518
519 channel = cpu_to_be32((u32)-1);
520 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
521 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
522
523 fw_iso_resources_free(&dice->resources);
524 }
525
526 static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
527 {
528 __be32 value;
529 int err;
530
531 reinit_completion(&dice->clock_accepted);
532
533 value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
534 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
535 global_address(dice, GLOBAL_CLOCK_SELECT),
536 &value, 4, 0);
537 if (err < 0)
538 return err;
539
540 if (!wait_for_completion_timeout(&dice->clock_accepted,
541 msecs_to_jiffies(100)))
542 dev_warn(&dice->unit->device, "clock change timed out\n");
543
544 return 0;
545 }
546
547 static int dice_hw_params(struct snd_pcm_substream *substream,
548 struct snd_pcm_hw_params *hw_params)
549 {
550 struct dice *dice = substream->private_data;
551 unsigned int rate_index, mode, rate, channels, i;
552 int err;
553
554 mutex_lock(&dice->mutex);
555 dice_stream_stop(dice);
556 mutex_unlock(&dice->mutex);
557
558 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
559 params_buffer_bytes(hw_params));
560 if (err < 0)
561 return err;
562
563 rate = params_rate(hw_params);
564 rate_index = rate_to_index(rate);
565 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
566 if (err < 0)
567 return err;
568
569 /*
570 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
571 * one data block of AMDTP packet. Thus sampling transfer frequency is
572 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
573 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
574 * channel are stored consecutively in the packet. This quirk is called
575 * as 'Dual Wire'.
576 * For this quirk, blocking mode is required and PCM buffer size should
577 * be aligned to SYT_INTERVAL.
578 */
579 channels = params_channels(hw_params);
580 if (rate_index > 4) {
581 if (channels > AMDTP_MAX_CHANNELS_FOR_PCM / 2) {
582 err = -ENOSYS;
583 return err;
584 }
585
586 rate /= 2;
587 channels *= 2;
588 dice->stream.double_pcm_frames = true;
589 } else {
590 dice->stream.double_pcm_frames = false;
591 }
592
593 mode = rate_index_to_mode(rate_index);
594 amdtp_stream_set_parameters(&dice->stream, rate, channels,
595 dice->rx_midi_ports[mode]);
596 if (rate_index > 4) {
597 channels /= 2;
598
599 for (i = 0; i < channels; i++) {
600 dice->stream.pcm_positions[i] = i * 2;
601 dice->stream.pcm_positions[i + channels] = i * 2 + 1;
602 }
603 }
604
605 amdtp_stream_set_pcm_format(&dice->stream,
606 params_format(hw_params));
607
608 return 0;
609 }
610
611 static int dice_hw_free(struct snd_pcm_substream *substream)
612 {
613 struct dice *dice = substream->private_data;
614
615 mutex_lock(&dice->mutex);
616 dice_stream_stop(dice);
617 mutex_unlock(&dice->mutex);
618
619 return snd_pcm_lib_free_vmalloc_buffer(substream);
620 }
621
622 static int dice_prepare(struct snd_pcm_substream *substream)
623 {
624 struct dice *dice = substream->private_data;
625 int err;
626
627 mutex_lock(&dice->mutex);
628
629 if (amdtp_streaming_error(&dice->stream))
630 dice_stream_stop_packets(dice);
631
632 err = dice_stream_start(dice);
633 if (err < 0) {
634 mutex_unlock(&dice->mutex);
635 return err;
636 }
637
638 mutex_unlock(&dice->mutex);
639
640 amdtp_stream_pcm_prepare(&dice->stream);
641
642 return 0;
643 }
644
645 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
646 {
647 struct dice *dice = substream->private_data;
648 struct snd_pcm_substream *pcm;
649
650 switch (cmd) {
651 case SNDRV_PCM_TRIGGER_START:
652 pcm = substream;
653 break;
654 case SNDRV_PCM_TRIGGER_STOP:
655 pcm = NULL;
656 break;
657 default:
658 return -EINVAL;
659 }
660 amdtp_stream_pcm_trigger(&dice->stream, pcm);
661
662 return 0;
663 }
664
665 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
666 {
667 struct dice *dice = substream->private_data;
668
669 return amdtp_stream_pcm_pointer(&dice->stream);
670 }
671
672 static int dice_create_pcm(struct dice *dice)
673 {
674 static struct snd_pcm_ops ops = {
675 .open = dice_open,
676 .close = dice_close,
677 .ioctl = snd_pcm_lib_ioctl,
678 .hw_params = dice_hw_params,
679 .hw_free = dice_hw_free,
680 .prepare = dice_prepare,
681 .trigger = dice_trigger,
682 .pointer = dice_pointer,
683 .page = snd_pcm_lib_get_vmalloc_page,
684 .mmap = snd_pcm_lib_mmap_vmalloc,
685 };
686 struct snd_pcm *pcm;
687 int err;
688
689 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
690 if (err < 0)
691 return err;
692 pcm->private_data = dice;
693 strcpy(pcm->name, dice->card->shortname);
694 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
695
696 return 0;
697 }
698
699 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
700 long count, loff_t *offset)
701 {
702 struct dice *dice = hwdep->private_data;
703 DEFINE_WAIT(wait);
704 union snd_firewire_event event;
705
706 spin_lock_irq(&dice->lock);
707
708 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
709 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
710 spin_unlock_irq(&dice->lock);
711 schedule();
712 finish_wait(&dice->hwdep_wait, &wait);
713 if (signal_pending(current))
714 return -ERESTARTSYS;
715 spin_lock_irq(&dice->lock);
716 }
717
718 memset(&event, 0, sizeof(event));
719 if (dice->dev_lock_changed) {
720 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
721 event.lock_status.status = dice->dev_lock_count > 0;
722 dice->dev_lock_changed = false;
723
724 count = min(count, (long)sizeof(event.lock_status));
725 } else {
726 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
727 event.dice_notification.notification = dice->notification_bits;
728 dice->notification_bits = 0;
729
730 count = min(count, (long)sizeof(event.dice_notification));
731 }
732
733 spin_unlock_irq(&dice->lock);
734
735 if (copy_to_user(buf, &event, count))
736 return -EFAULT;
737
738 return count;
739 }
740
741 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
742 poll_table *wait)
743 {
744 struct dice *dice = hwdep->private_data;
745 unsigned int events;
746
747 poll_wait(file, &dice->hwdep_wait, wait);
748
749 spin_lock_irq(&dice->lock);
750 if (dice->dev_lock_changed || dice->notification_bits != 0)
751 events = POLLIN | POLLRDNORM;
752 else
753 events = 0;
754 spin_unlock_irq(&dice->lock);
755
756 return events;
757 }
758
759 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
760 {
761 struct fw_device *dev = fw_parent_device(dice->unit);
762 struct snd_firewire_get_info info;
763
764 memset(&info, 0, sizeof(info));
765 info.type = SNDRV_FIREWIRE_TYPE_DICE;
766 info.card = dev->card->index;
767 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
768 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
769 strlcpy(info.device_name, dev_name(&dev->device),
770 sizeof(info.device_name));
771
772 if (copy_to_user(arg, &info, sizeof(info)))
773 return -EFAULT;
774
775 return 0;
776 }
777
778 static int dice_hwdep_lock(struct dice *dice)
779 {
780 int err;
781
782 spin_lock_irq(&dice->lock);
783
784 if (dice->dev_lock_count == 0) {
785 dice->dev_lock_count = -1;
786 err = 0;
787 } else {
788 err = -EBUSY;
789 }
790
791 spin_unlock_irq(&dice->lock);
792
793 return err;
794 }
795
796 static int dice_hwdep_unlock(struct dice *dice)
797 {
798 int err;
799
800 spin_lock_irq(&dice->lock);
801
802 if (dice->dev_lock_count == -1) {
803 dice->dev_lock_count = 0;
804 err = 0;
805 } else {
806 err = -EBADFD;
807 }
808
809 spin_unlock_irq(&dice->lock);
810
811 return err;
812 }
813
814 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
815 {
816 struct dice *dice = hwdep->private_data;
817
818 spin_lock_irq(&dice->lock);
819 if (dice->dev_lock_count == -1)
820 dice->dev_lock_count = 0;
821 spin_unlock_irq(&dice->lock);
822
823 return 0;
824 }
825
826 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
827 unsigned int cmd, unsigned long arg)
828 {
829 struct dice *dice = hwdep->private_data;
830
831 switch (cmd) {
832 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
833 return dice_hwdep_get_info(dice, (void __user *)arg);
834 case SNDRV_FIREWIRE_IOCTL_LOCK:
835 return dice_hwdep_lock(dice);
836 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
837 return dice_hwdep_unlock(dice);
838 default:
839 return -ENOIOCTLCMD;
840 }
841 }
842
843 #ifdef CONFIG_COMPAT
844 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
845 unsigned int cmd, unsigned long arg)
846 {
847 return dice_hwdep_ioctl(hwdep, file, cmd,
848 (unsigned long)compat_ptr(arg));
849 }
850 #else
851 #define dice_hwdep_compat_ioctl NULL
852 #endif
853
854 static int dice_create_hwdep(struct dice *dice)
855 {
856 static const struct snd_hwdep_ops ops = {
857 .read = dice_hwdep_read,
858 .release = dice_hwdep_release,
859 .poll = dice_hwdep_poll,
860 .ioctl = dice_hwdep_ioctl,
861 .ioctl_compat = dice_hwdep_compat_ioctl,
862 };
863 struct snd_hwdep *hwdep;
864 int err;
865
866 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
867 if (err < 0)
868 return err;
869 strcpy(hwdep->name, "DICE");
870 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
871 hwdep->ops = ops;
872 hwdep->private_data = dice;
873 hwdep->exclusive = true;
874
875 return 0;
876 }
877
878 static int dice_proc_read_mem(struct dice *dice, void *buffer,
879 unsigned int offset_q, unsigned int quadlets)
880 {
881 unsigned int i;
882 int err;
883
884 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
885 DICE_PRIVATE_SPACE + 4 * offset_q,
886 buffer, 4 * quadlets, 0);
887 if (err < 0)
888 return err;
889
890 for (i = 0; i < quadlets; ++i)
891 be32_to_cpus(&((u32 *)buffer)[i]);
892
893 return 0;
894 }
895
896 static const char *str_from_array(const char *const strs[], unsigned int count,
897 unsigned int i)
898 {
899 if (i < count)
900 return strs[i];
901 else
902 return "(unknown)";
903 }
904
905 static void dice_proc_fixup_string(char *s, unsigned int size)
906 {
907 unsigned int i;
908
909 for (i = 0; i < size; i += 4)
910 cpu_to_le32s((u32 *)(s + i));
911
912 for (i = 0; i < size - 2; ++i) {
913 if (s[i] == '\0')
914 return;
915 if (s[i] == '\\' && s[i + 1] == '\\') {
916 s[i + 2] = '\0';
917 return;
918 }
919 }
920 s[size - 1] = '\0';
921 }
922
923 static void dice_proc_read(struct snd_info_entry *entry,
924 struct snd_info_buffer *buffer)
925 {
926 static const char *const section_names[5] = {
927 "global", "tx", "rx", "ext_sync", "unused2"
928 };
929 static const char *const clock_sources[] = {
930 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
931 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
932 };
933 static const char *const rates[] = {
934 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
935 "any low", "any mid", "any high", "none"
936 };
937 struct dice *dice = entry->private_data;
938 u32 sections[ARRAY_SIZE(section_names) * 2];
939 struct {
940 u32 number;
941 u32 size;
942 } tx_rx_header;
943 union {
944 struct {
945 u32 owner_hi, owner_lo;
946 u32 notification;
947 char nick_name[NICK_NAME_SIZE];
948 u32 clock_select;
949 u32 enable;
950 u32 status;
951 u32 extended_status;
952 u32 sample_rate;
953 u32 version;
954 u32 clock_caps;
955 char clock_source_names[CLOCK_SOURCE_NAMES_SIZE];
956 } global;
957 struct {
958 u32 iso;
959 u32 number_audio;
960 u32 number_midi;
961 u32 speed;
962 char names[TX_NAMES_SIZE];
963 u32 ac3_caps;
964 u32 ac3_enable;
965 } tx;
966 struct {
967 u32 iso;
968 u32 seq_start;
969 u32 number_audio;
970 u32 number_midi;
971 char names[RX_NAMES_SIZE];
972 u32 ac3_caps;
973 u32 ac3_enable;
974 } rx;
975 struct {
976 u32 clock_source;
977 u32 locked;
978 u32 rate;
979 u32 adat_user_data;
980 } ext_sync;
981 } buf;
982 unsigned int quadlets, stream, i;
983
984 if (dice_proc_read_mem(dice, sections, 0, ARRAY_SIZE(sections)) < 0)
985 return;
986 snd_iprintf(buffer, "sections:\n");
987 for (i = 0; i < ARRAY_SIZE(section_names); ++i)
988 snd_iprintf(buffer, " %s: offset %u, size %u\n",
989 section_names[i],
990 sections[i * 2], sections[i * 2 + 1]);
991
992 quadlets = min_t(u32, sections[1], sizeof(buf.global) / 4);
993 if (dice_proc_read_mem(dice, &buf.global, sections[0], quadlets) < 0)
994 return;
995 snd_iprintf(buffer, "global:\n");
996 snd_iprintf(buffer, " owner: %04x:%04x%08x\n",
997 buf.global.owner_hi >> 16,
998 buf.global.owner_hi & 0xffff, buf.global.owner_lo);
999 snd_iprintf(buffer, " notification: %08x\n", buf.global.notification);
1000 dice_proc_fixup_string(buf.global.nick_name, NICK_NAME_SIZE);
1001 snd_iprintf(buffer, " nick name: %s\n", buf.global.nick_name);
1002 snd_iprintf(buffer, " clock select: %s %s\n",
1003 str_from_array(clock_sources, ARRAY_SIZE(clock_sources),
1004 buf.global.clock_select & CLOCK_SOURCE_MASK),
1005 str_from_array(rates, ARRAY_SIZE(rates),
1006 (buf.global.clock_select & CLOCK_RATE_MASK)
1007 >> CLOCK_RATE_SHIFT));
1008 snd_iprintf(buffer, " enable: %u\n", buf.global.enable);
1009 snd_iprintf(buffer, " status: %slocked %s\n",
1010 buf.global.status & STATUS_SOURCE_LOCKED ? "" : "un",
1011 str_from_array(rates, ARRAY_SIZE(rates),
1012 (buf.global.status &
1013 STATUS_NOMINAL_RATE_MASK)
1014 >> CLOCK_RATE_SHIFT));
1015 snd_iprintf(buffer, " ext status: %08x\n", buf.global.extended_status);
1016 snd_iprintf(buffer, " sample rate: %u\n", buf.global.sample_rate);
1017 snd_iprintf(buffer, " version: %u.%u.%u.%u\n",
1018 (buf.global.version >> 24) & 0xff,
1019 (buf.global.version >> 16) & 0xff,
1020 (buf.global.version >> 8) & 0xff,
1021 (buf.global.version >> 0) & 0xff);
1022 if (quadlets >= 90) {
1023 snd_iprintf(buffer, " clock caps:");
1024 for (i = 0; i <= 6; ++i)
1025 if (buf.global.clock_caps & (1 << i))
1026 snd_iprintf(buffer, " %s", rates[i]);
1027 for (i = 0; i <= 12; ++i)
1028 if (buf.global.clock_caps & (1 << (16 + i)))
1029 snd_iprintf(buffer, " %s", clock_sources[i]);
1030 snd_iprintf(buffer, "\n");
1031 dice_proc_fixup_string(buf.global.clock_source_names,
1032 CLOCK_SOURCE_NAMES_SIZE);
1033 snd_iprintf(buffer, " clock source names: %s\n",
1034 buf.global.clock_source_names);
1035 }
1036
1037 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
1038 return;
1039 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx) / 4);
1040 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1041 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
1042 stream * tx_rx_header.size,
1043 quadlets) < 0)
1044 break;
1045 snd_iprintf(buffer, "tx %u:\n", stream);
1046 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.tx.iso);
1047 snd_iprintf(buffer, " audio channels: %u\n",
1048 buf.tx.number_audio);
1049 snd_iprintf(buffer, " midi ports: %u\n", buf.tx.number_midi);
1050 snd_iprintf(buffer, " speed: S%u\n", 100u << buf.tx.speed);
1051 if (quadlets >= 68) {
1052 dice_proc_fixup_string(buf.tx.names, TX_NAMES_SIZE);
1053 snd_iprintf(buffer, " names: %s\n", buf.tx.names);
1054 }
1055 if (quadlets >= 70) {
1056 snd_iprintf(buffer, " ac3 caps: %08x\n",
1057 buf.tx.ac3_caps);
1058 snd_iprintf(buffer, " ac3 enable: %08x\n",
1059 buf.tx.ac3_enable);
1060 }
1061 }
1062
1063 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
1064 return;
1065 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx) / 4);
1066 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1067 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
1068 stream * tx_rx_header.size,
1069 quadlets) < 0)
1070 break;
1071 snd_iprintf(buffer, "rx %u:\n", stream);
1072 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.rx.iso);
1073 snd_iprintf(buffer, " sequence start: %u\n", buf.rx.seq_start);
1074 snd_iprintf(buffer, " audio channels: %u\n",
1075 buf.rx.number_audio);
1076 snd_iprintf(buffer, " midi ports: %u\n", buf.rx.number_midi);
1077 if (quadlets >= 68) {
1078 dice_proc_fixup_string(buf.rx.names, RX_NAMES_SIZE);
1079 snd_iprintf(buffer, " names: %s\n", buf.rx.names);
1080 }
1081 if (quadlets >= 70) {
1082 snd_iprintf(buffer, " ac3 caps: %08x\n",
1083 buf.rx.ac3_caps);
1084 snd_iprintf(buffer, " ac3 enable: %08x\n",
1085 buf.rx.ac3_enable);
1086 }
1087 }
1088
1089 quadlets = min_t(u32, sections[7], sizeof(buf.ext_sync) / 4);
1090 if (quadlets >= 4) {
1091 if (dice_proc_read_mem(dice, &buf.ext_sync,
1092 sections[6], 4) < 0)
1093 return;
1094 snd_iprintf(buffer, "ext status:\n");
1095 snd_iprintf(buffer, " clock source: %s\n",
1096 str_from_array(clock_sources,
1097 ARRAY_SIZE(clock_sources),
1098 buf.ext_sync.clock_source));
1099 snd_iprintf(buffer, " locked: %u\n", buf.ext_sync.locked);
1100 snd_iprintf(buffer, " rate: %s\n",
1101 str_from_array(rates, ARRAY_SIZE(rates),
1102 buf.ext_sync.rate));
1103 snd_iprintf(buffer, " adat user data: ");
1104 if (buf.ext_sync.adat_user_data & ADAT_USER_DATA_NO_DATA)
1105 snd_iprintf(buffer, "-\n");
1106 else
1107 snd_iprintf(buffer, "%x\n",
1108 buf.ext_sync.adat_user_data);
1109 }
1110 }
1111
1112 static void dice_create_proc(struct dice *dice)
1113 {
1114 struct snd_info_entry *entry;
1115
1116 if (!snd_card_proc_new(dice->card, "dice", &entry))
1117 snd_info_set_text_ops(entry, dice, dice_proc_read);
1118 }
1119
1120 static void dice_card_free(struct snd_card *card)
1121 {
1122 struct dice *dice = card->private_data;
1123
1124 amdtp_stream_destroy(&dice->stream);
1125 fw_core_remove_address_handler(&dice->notification_handler);
1126 mutex_destroy(&dice->mutex);
1127 }
1128
1129 #define OUI_WEISS 0x001c6a
1130
1131 #define DICE_CATEGORY_ID 0x04
1132 #define WEISS_CATEGORY_ID 0x00
1133
1134 static int dice_interface_check(struct fw_unit *unit)
1135 {
1136 static const int min_values[10] = {
1137 10, 0x64 / 4,
1138 10, 0x18 / 4,
1139 10, 0x18 / 4,
1140 0, 0,
1141 0, 0,
1142 };
1143 struct fw_device *device = fw_parent_device(unit);
1144 struct fw_csr_iterator it;
1145 int key, value, vendor = -1, model = -1, err;
1146 unsigned int category, i;
1147 __be32 pointers[ARRAY_SIZE(min_values)];
1148 __be32 tx_data[4];
1149 __be32 version;
1150
1151 /*
1152 * Check that GUID and unit directory are constructed according to DICE
1153 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
1154 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
1155 * ID, and a 22-bit serial number.
1156 */
1157 fw_csr_iterator_init(&it, unit->directory);
1158 while (fw_csr_iterator_next(&it, &key, &value)) {
1159 switch (key) {
1160 case CSR_SPECIFIER_ID:
1161 vendor = value;
1162 break;
1163 case CSR_MODEL:
1164 model = value;
1165 break;
1166 }
1167 }
1168 if (vendor == OUI_WEISS)
1169 category = WEISS_CATEGORY_ID;
1170 else
1171 category = DICE_CATEGORY_ID;
1172 if (device->config_rom[3] != ((vendor << 8) | category) ||
1173 device->config_rom[4] >> 22 != model)
1174 return -ENODEV;
1175
1176 /*
1177 * Check that the sub address spaces exist and are located inside the
1178 * private address space. The minimum values are chosen so that all
1179 * minimally required registers are included.
1180 */
1181 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1182 DICE_PRIVATE_SPACE,
1183 pointers, sizeof(pointers), 0);
1184 if (err < 0)
1185 return -ENODEV;
1186 for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
1187 value = be32_to_cpu(pointers[i]);
1188 if (value < min_values[i] || value >= 0x40000)
1189 return -ENODEV;
1190 }
1191
1192 /* We support playback only. Let capture devices be handled by FFADO. */
1193 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1194 DICE_PRIVATE_SPACE +
1195 be32_to_cpu(pointers[2]) * 4,
1196 tx_data, sizeof(tx_data), 0);
1197 if (err < 0 || (tx_data[0] && tx_data[3]))
1198 return -ENODEV;
1199
1200 /*
1201 * Check that the implemented DICE driver specification major version
1202 * number matches.
1203 */
1204 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1205 DICE_PRIVATE_SPACE +
1206 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
1207 &version, 4, 0);
1208 if (err < 0)
1209 return -ENODEV;
1210 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
1211 dev_err(&unit->device,
1212 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
1213 return -ENODEV;
1214 }
1215
1216 return 0;
1217 }
1218
1219 static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
1220 {
1221 int i;
1222
1223 for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
1224 if ((dice->clock_caps & (1 << i)) &&
1225 rate_index_to_mode(i) == mode)
1226 return i;
1227
1228 return -1;
1229 }
1230
1231 static int dice_read_mode_params(struct dice *dice, unsigned int mode)
1232 {
1233 __be32 values[2];
1234 int rate_index, err;
1235
1236 rate_index = highest_supported_mode_rate(dice, mode);
1237 if (rate_index < 0) {
1238 dice->rx_channels[mode] = 0;
1239 dice->rx_midi_ports[mode] = 0;
1240 return 0;
1241 }
1242
1243 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
1244 if (err < 0)
1245 return err;
1246
1247 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1248 rx_address(dice, RX_NUMBER_AUDIO),
1249 values, 2 * 4, 0);
1250 if (err < 0)
1251 return err;
1252
1253 dice->rx_channels[mode] = be32_to_cpu(values[0]);
1254 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
1255
1256 return 0;
1257 }
1258
1259 static int dice_read_params(struct dice *dice)
1260 {
1261 __be32 pointers[6];
1262 __be32 value;
1263 int mode, err;
1264
1265 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1266 DICE_PRIVATE_SPACE,
1267 pointers, sizeof(pointers), 0);
1268 if (err < 0)
1269 return err;
1270
1271 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1272 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1273
1274 /* some very old firmwares don't tell about their clock support */
1275 if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
1276 err = snd_fw_transaction(
1277 dice->unit, TCODE_READ_QUADLET_REQUEST,
1278 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
1279 &value, 4, 0);
1280 if (err < 0)
1281 return err;
1282 dice->clock_caps = be32_to_cpu(value);
1283 } else {
1284 /* this should be supported by any device */
1285 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1286 CLOCK_CAP_RATE_48000 |
1287 CLOCK_CAP_SOURCE_ARX1 |
1288 CLOCK_CAP_SOURCE_INTERNAL;
1289 }
1290
1291 for (mode = 2; mode >= 0; --mode) {
1292 err = dice_read_mode_params(dice, mode);
1293 if (err < 0)
1294 return err;
1295 }
1296
1297 return 0;
1298 }
1299
1300 static void dice_card_strings(struct dice *dice)
1301 {
1302 struct snd_card *card = dice->card;
1303 struct fw_device *dev = fw_parent_device(dice->unit);
1304 char vendor[32], model[32];
1305 unsigned int i;
1306 int err;
1307
1308 strcpy(card->driver, "DICE");
1309
1310 strcpy(card->shortname, "DICE");
1311 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1312 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1313 global_address(dice, GLOBAL_NICK_NAME),
1314 card->shortname, sizeof(card->shortname), 0);
1315 if (err >= 0) {
1316 /* DICE strings are returned in "always-wrong" endianness */
1317 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1318 for (i = 0; i < sizeof(card->shortname); i += 4)
1319 swab32s((u32 *)&card->shortname[i]);
1320 card->shortname[sizeof(card->shortname) - 1] = '\0';
1321 }
1322
1323 strcpy(vendor, "?");
1324 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1325 strcpy(model, "?");
1326 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1327 snprintf(card->longname, sizeof(card->longname),
1328 "%s %s (serial %u) at %s, S%d",
1329 vendor, model, dev->config_rom[4] & 0x3fffff,
1330 dev_name(&dice->unit->device), 100 << dev->max_speed);
1331
1332 strcpy(card->mixername, "DICE");
1333 }
1334
1335 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1336 {
1337 struct snd_card *card;
1338 struct dice *dice;
1339 __be32 clock_sel;
1340 int err;
1341
1342 err = dice_interface_check(unit);
1343 if (err < 0)
1344 return err;
1345
1346 err = snd_card_new(&unit->device, -1, NULL, THIS_MODULE,
1347 sizeof(*dice), &card);
1348 if (err < 0)
1349 return err;
1350
1351 dice = card->private_data;
1352 dice->card = card;
1353 spin_lock_init(&dice->lock);
1354 mutex_init(&dice->mutex);
1355 dice->unit = unit;
1356 init_completion(&dice->clock_accepted);
1357 init_waitqueue_head(&dice->hwdep_wait);
1358
1359 dice->notification_handler.length = 4;
1360 dice->notification_handler.address_callback = dice_notification;
1361 dice->notification_handler.callback_data = dice;
1362 err = fw_core_add_address_handler(&dice->notification_handler,
1363 &fw_high_memory_region);
1364 if (err < 0)
1365 goto err_mutex;
1366
1367 err = dice_owner_set(dice);
1368 if (err < 0)
1369 goto err_notification_handler;
1370
1371 err = dice_read_params(dice);
1372 if (err < 0)
1373 goto err_owner;
1374
1375 err = fw_iso_resources_init(&dice->resources, unit);
1376 if (err < 0)
1377 goto err_owner;
1378 dice->resources.channels_mask = 0x00000000ffffffffuLL;
1379
1380 err = amdtp_stream_init(&dice->stream, unit, AMDTP_OUT_STREAM,
1381 CIP_BLOCKING);
1382 if (err < 0)
1383 goto err_resources;
1384
1385 card->private_free = dice_card_free;
1386
1387 dice_card_strings(dice);
1388
1389 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1390 global_address(dice, GLOBAL_CLOCK_SELECT),
1391 &clock_sel, 4, 0);
1392 if (err < 0)
1393 goto error;
1394 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1395 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1396 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1397 global_address(dice, GLOBAL_CLOCK_SELECT),
1398 &clock_sel, 4, 0);
1399 if (err < 0)
1400 goto error;
1401
1402 err = dice_create_pcm(dice);
1403 if (err < 0)
1404 goto error;
1405
1406 err = dice_create_hwdep(dice);
1407 if (err < 0)
1408 goto error;
1409
1410 dice_create_proc(dice);
1411
1412 err = snd_card_register(card);
1413 if (err < 0)
1414 goto error;
1415
1416 dev_set_drvdata(&unit->device, dice);
1417
1418 return 0;
1419
1420 err_resources:
1421 fw_iso_resources_destroy(&dice->resources);
1422 err_owner:
1423 dice_owner_clear(dice);
1424 err_notification_handler:
1425 fw_core_remove_address_handler(&dice->notification_handler);
1426 err_mutex:
1427 mutex_destroy(&dice->mutex);
1428 error:
1429 snd_card_free(card);
1430 return err;
1431 }
1432
1433 static void dice_remove(struct fw_unit *unit)
1434 {
1435 struct dice *dice = dev_get_drvdata(&unit->device);
1436
1437 amdtp_stream_pcm_abort(&dice->stream);
1438
1439 snd_card_disconnect(dice->card);
1440
1441 mutex_lock(&dice->mutex);
1442
1443 dice_stream_stop(dice);
1444 dice_owner_clear(dice);
1445
1446 mutex_unlock(&dice->mutex);
1447
1448 snd_card_free_when_closed(dice->card);
1449 }
1450
1451 static void dice_bus_reset(struct fw_unit *unit)
1452 {
1453 struct dice *dice = dev_get_drvdata(&unit->device);
1454
1455 /*
1456 * On a bus reset, the DICE firmware disables streaming and then goes
1457 * off contemplating its own navel for hundreds of milliseconds before
1458 * it can react to any of our attempts to reenable streaming. This
1459 * means that we lose synchronization anyway, so we force our streams
1460 * to stop so that the application can restart them in an orderly
1461 * manner.
1462 */
1463 amdtp_stream_pcm_abort(&dice->stream);
1464
1465 mutex_lock(&dice->mutex);
1466
1467 dice->global_enabled = false;
1468 dice_stream_stop_packets(dice);
1469
1470 dice_owner_update(dice);
1471
1472 fw_iso_resources_update(&dice->resources);
1473
1474 mutex_unlock(&dice->mutex);
1475 }
1476
1477 #define DICE_INTERFACE 0x000001
1478
1479 static const struct ieee1394_device_id dice_id_table[] = {
1480 {
1481 .match_flags = IEEE1394_MATCH_VERSION,
1482 .version = DICE_INTERFACE,
1483 },
1484 { }
1485 };
1486 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1487
1488 static struct fw_driver dice_driver = {
1489 .driver = {
1490 .owner = THIS_MODULE,
1491 .name = KBUILD_MODNAME,
1492 .bus = &fw_bus_type,
1493 },
1494 .probe = dice_probe,
1495 .update = dice_bus_reset,
1496 .remove = dice_remove,
1497 .id_table = dice_id_table,
1498 };
1499
1500 static int __init alsa_dice_init(void)
1501 {
1502 return driver_register(&dice_driver.driver);
1503 }
1504
1505 static void __exit alsa_dice_exit(void)
1506 {
1507 driver_unregister(&dice_driver.driver);
1508 }
1509
1510 module_init(alsa_dice_init);
1511 module_exit(alsa_dice_exit);
Linux with added FPC-III support