2 * SuperH Timer Support - MTU2
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
32 #include <linux/slab.h>
35 void __iomem
*mapbase
;
37 struct irqaction irqaction
;
38 struct platform_device
*pdev
;
40 unsigned long periodic
;
41 struct clock_event_device ced
;
44 static DEFINE_SPINLOCK(sh_mtu2_lock
);
46 #define TSTR -1 /* shared register */
47 #define TCR 0 /* channel register */
48 #define TMDR 1 /* channel register */
49 #define TIOR 2 /* channel register */
50 #define TIER 3 /* channel register */
51 #define TSR 4 /* channel register */
52 #define TCNT 5 /* channel register */
53 #define TGR 6 /* channel register */
55 static unsigned long mtu2_reg_offs
[] = {
65 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv
*p
, int reg_nr
)
67 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
68 void __iomem
*base
= p
->mapbase
;
72 return ioread8(base
+ cfg
->channel_offset
);
74 offs
= mtu2_reg_offs
[reg_nr
];
76 if ((reg_nr
== TCNT
) || (reg_nr
== TGR
))
77 return ioread16(base
+ offs
);
79 return ioread8(base
+ offs
);
82 static inline void sh_mtu2_write(struct sh_mtu2_priv
*p
, int reg_nr
,
85 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
86 void __iomem
*base
= p
->mapbase
;
90 iowrite8(value
, base
+ cfg
->channel_offset
);
94 offs
= mtu2_reg_offs
[reg_nr
];
96 if ((reg_nr
== TCNT
) || (reg_nr
== TGR
))
97 iowrite16(value
, base
+ offs
);
99 iowrite8(value
, base
+ offs
);
102 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv
*p
, int start
)
104 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
105 unsigned long flags
, value
;
107 /* start stop register shared by multiple timer channels */
108 spin_lock_irqsave(&sh_mtu2_lock
, flags
);
109 value
= sh_mtu2_read(p
, TSTR
);
112 value
|= 1 << cfg
->timer_bit
;
114 value
&= ~(1 << cfg
->timer_bit
);
116 sh_mtu2_write(p
, TSTR
, value
);
117 spin_unlock_irqrestore(&sh_mtu2_lock
, flags
);
120 static int sh_mtu2_enable(struct sh_mtu2_priv
*p
)
122 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
126 ret
= clk_enable(p
->clk
);
128 pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg
->clk
);
132 /* make sure channel is disabled */
133 sh_mtu2_start_stop_ch(p
, 0);
135 p
->rate
= clk_get_rate(p
->clk
) / 64;
136 p
->periodic
= (p
->rate
+ HZ
/2) / HZ
;
138 /* "Periodic Counter Operation" */
139 sh_mtu2_write(p
, TCR
, 0x23); /* TGRA clear, divide clock by 64 */
140 sh_mtu2_write(p
, TIOR
, 0);
141 sh_mtu2_write(p
, TGR
, p
->periodic
);
142 sh_mtu2_write(p
, TCNT
, 0);
143 sh_mtu2_write(p
, TMDR
, 0);
144 sh_mtu2_write(p
, TIER
, 0x01);
147 sh_mtu2_start_stop_ch(p
, 1);
152 static void sh_mtu2_disable(struct sh_mtu2_priv
*p
)
154 /* disable channel */
155 sh_mtu2_start_stop_ch(p
, 0);
161 static irqreturn_t
sh_mtu2_interrupt(int irq
, void *dev_id
)
163 struct sh_mtu2_priv
*p
= dev_id
;
165 /* acknowledge interrupt */
166 sh_mtu2_read(p
, TSR
);
167 sh_mtu2_write(p
, TSR
, 0xfe);
169 /* notify clockevent layer */
170 p
->ced
.event_handler(&p
->ced
);
174 static struct sh_mtu2_priv
*ced_to_sh_mtu2(struct clock_event_device
*ced
)
176 return container_of(ced
, struct sh_mtu2_priv
, ced
);
179 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode
,
180 struct clock_event_device
*ced
)
182 struct sh_mtu2_priv
*p
= ced_to_sh_mtu2(ced
);
185 /* deal with old setting first */
187 case CLOCK_EVT_MODE_PERIODIC
:
196 case CLOCK_EVT_MODE_PERIODIC
:
197 pr_info("sh_mtu2: %s used for periodic clock events\n",
201 case CLOCK_EVT_MODE_UNUSED
:
205 case CLOCK_EVT_MODE_SHUTDOWN
:
211 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv
*p
,
212 char *name
, unsigned long rating
)
214 struct clock_event_device
*ced
= &p
->ced
;
217 memset(ced
, 0, sizeof(*ced
));
220 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
221 ced
->rating
= rating
;
222 ced
->cpumask
= cpumask_of(0);
223 ced
->set_mode
= sh_mtu2_clock_event_mode
;
225 pr_info("sh_mtu2: %s used for clock events\n", ced
->name
);
226 clockevents_register_device(ced
);
228 ret
= setup_irq(p
->irqaction
.irq
, &p
->irqaction
);
230 pr_err("sh_mtu2: failed to request irq %d\n",
236 static int sh_mtu2_register(struct sh_mtu2_priv
*p
, char *name
,
237 unsigned long clockevent_rating
)
239 if (clockevent_rating
)
240 sh_mtu2_register_clockevent(p
, name
, clockevent_rating
);
245 static int sh_mtu2_setup(struct sh_mtu2_priv
*p
, struct platform_device
*pdev
)
247 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
248 struct resource
*res
;
252 memset(p
, 0, sizeof(*p
));
256 dev_err(&p
->pdev
->dev
, "missing platform data\n");
260 platform_set_drvdata(pdev
, p
);
262 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
264 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
268 irq
= platform_get_irq(p
->pdev
, 0);
270 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
274 /* map memory, let mapbase point to our channel */
275 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
276 if (p
->mapbase
== NULL
) {
277 pr_err("sh_mtu2: failed to remap I/O memory\n");
281 /* setup data for setup_irq() (too early for request_irq()) */
282 p
->irqaction
.name
= cfg
->name
;
283 p
->irqaction
.handler
= sh_mtu2_interrupt
;
284 p
->irqaction
.dev_id
= p
;
285 p
->irqaction
.irq
= irq
;
286 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
;
288 /* get hold of clock */
289 p
->clk
= clk_get(&p
->pdev
->dev
, cfg
->clk
);
290 if (IS_ERR(p
->clk
)) {
291 pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg
->clk
);
292 ret
= PTR_ERR(p
->clk
);
296 return sh_mtu2_register(p
, cfg
->name
, cfg
->clockevent_rating
);
303 static int __devinit
sh_mtu2_probe(struct platform_device
*pdev
)
305 struct sh_mtu2_priv
*p
= platform_get_drvdata(pdev
);
306 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
310 pr_info("sh_mtu2: %s kept as earlytimer\n", cfg
->name
);
314 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
316 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
320 ret
= sh_mtu2_setup(p
, pdev
);
323 platform_set_drvdata(pdev
, NULL
);
328 static int __devexit
sh_mtu2_remove(struct platform_device
*pdev
)
330 return -EBUSY
; /* cannot unregister clockevent */
333 static struct platform_driver sh_mtu2_device_driver
= {
334 .probe
= sh_mtu2_probe
,
335 .remove
= __devexit_p(sh_mtu2_remove
),
341 static int __init
sh_mtu2_init(void)
343 return platform_driver_register(&sh_mtu2_device_driver
);
346 static void __exit
sh_mtu2_exit(void)
348 platform_driver_unregister(&sh_mtu2_device_driver
);
351 early_platform_init("earlytimer", &sh_mtu2_device_driver
);
352 module_init(sh_mtu2_init
);
353 module_exit(sh_mtu2_exit
);
355 MODULE_AUTHOR("Magnus Damm");
356 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
357 MODULE_LICENSE("GPL v2");