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Staging: netwave: delete the driver
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_legacy_encoders.c
blob2441cca7d775d899de9cf5f27481352aef2da30f
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
33 {
34 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
35 struct drm_encoder_helper_funcs *encoder_funcs;
36
37 encoder_funcs = encoder->helper_private;
38 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
39 radeon_encoder->active_device = 0;
40 }
41
42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
43 {
44 struct drm_device *dev = encoder->dev;
45 struct radeon_device *rdev = dev->dev_private;
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000;
49 bool is_mac = false;
50 DRM_DEBUG("\n");
51
52 if (radeon_encoder->enc_priv) {
53 if (rdev->is_atom_bios) {
54 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
55 panel_pwr_delay = lvds->panel_pwr_delay;
56 } else {
57 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
58 panel_pwr_delay = lvds->panel_pwr_delay;
59 }
60 }
61
62 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
63 * Taken from radeonfb.
64 */
65 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
66 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
67 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
68 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
69 is_mac = true;
70
71 switch (mode) {
72 case DRM_MODE_DPMS_ON:
73 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
74 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
75 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
76 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
77 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
78 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
79 udelay(1000);
80
81 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
82 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
83 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
84
85 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
86 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
87 if (is_mac)
88 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
89 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
90 udelay(panel_pwr_delay * 1000);
91 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
92 break;
93 case DRM_MODE_DPMS_STANDBY:
94 case DRM_MODE_DPMS_SUSPEND:
95 case DRM_MODE_DPMS_OFF:
96 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
98 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
99 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
100 if (is_mac) {
101 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
102 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
103 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
104 } else {
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
107 }
108 udelay(panel_pwr_delay * 1000);
109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
111 break;
112 }
113
114 if (rdev->is_atom_bios)
115 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
116 else
117 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
118
119 /* adjust pm to dpms change */
120 radeon_pm_compute_clocks(rdev);
121 }
122
123 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
124 {
125 struct radeon_device *rdev = encoder->dev->dev_private;
126
127 if (rdev->is_atom_bios)
128 radeon_atom_output_lock(encoder, true);
129 else
130 radeon_combios_output_lock(encoder, true);
131 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
132 }
133
134 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
135 {
136 struct radeon_device *rdev = encoder->dev->dev_private;
137
138 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
139 if (rdev->is_atom_bios)
140 radeon_atom_output_lock(encoder, false);
141 else
142 radeon_combios_output_lock(encoder, false);
143 }
144
145 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
146 struct drm_display_mode *mode,
147 struct drm_display_mode *adjusted_mode)
148 {
149 struct drm_device *dev = encoder->dev;
150 struct radeon_device *rdev = dev->dev_private;
151 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
152 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
153 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
154
155 DRM_DEBUG("\n");
156
157 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
158 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
159
160 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
161 if (rdev->is_atom_bios) {
162 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
163 * need to call that on resume to set up the reg properly.
164 */
165 radeon_encoder->pixel_clock = adjusted_mode->clock;
166 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
167 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
168 } else {
169 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
170 if (lvds) {
171 DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
172 lvds_gen_cntl = lvds->lvds_gen_cntl;
173 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
174 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
175 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
176 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
177 } else
178 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
179 }
180 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
181 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
182 RADEON_LVDS_BLON |
183 RADEON_LVDS_EN |
184 RADEON_LVDS_RST_FM);
185
186 if (ASIC_IS_R300(rdev))
187 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
188
189 if (radeon_crtc->crtc_id == 0) {
190 if (ASIC_IS_R300(rdev)) {
191 if (radeon_encoder->rmx_type != RMX_OFF)
192 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
193 } else
194 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
195 } else {
196 if (ASIC_IS_R300(rdev))
197 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
198 else
199 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
200 }
201
202 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
203 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
204 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
205
206 if (rdev->family == CHIP_RV410)
207 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
208
209 if (rdev->is_atom_bios)
210 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
211 else
212 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
213 }
214
215 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
216 struct drm_display_mode *mode,
217 struct drm_display_mode *adjusted_mode)
218 {
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_device *dev = encoder->dev;
221 struct radeon_device *rdev = dev->dev_private;
222
223 /* adjust pm to upcoming mode change */
224 radeon_pm_compute_clocks(rdev);
225
226 /* set the active encoder to connector routing */
227 radeon_encoder_set_active_device(encoder);
228 drm_mode_set_crtcinfo(adjusted_mode, 0);
229
230 /* get the native mode for LVDS */
231 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
232 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
233 int mode_id = adjusted_mode->base.id;
234 *adjusted_mode = *native_mode;
235 adjusted_mode->hdisplay = mode->hdisplay;
236 adjusted_mode->vdisplay = mode->vdisplay;
237 adjusted_mode->crtc_hdisplay = mode->hdisplay;
238 adjusted_mode->crtc_vdisplay = mode->vdisplay;
239 adjusted_mode->base.id = mode_id;
240 }
241
242 return true;
243 }
244
245 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
246 .dpms = radeon_legacy_lvds_dpms,
247 .mode_fixup = radeon_legacy_mode_fixup,
248 .prepare = radeon_legacy_lvds_prepare,
249 .mode_set = radeon_legacy_lvds_mode_set,
250 .commit = radeon_legacy_lvds_commit,
251 .disable = radeon_legacy_encoder_disable,
252 };
253
254
255 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
256 .destroy = radeon_enc_destroy,
257 };
258
259 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
260 {
261 struct drm_device *dev = encoder->dev;
262 struct radeon_device *rdev = dev->dev_private;
263 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
264 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
265 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
266
267 DRM_DEBUG("\n");
268
269 switch (mode) {
270 case DRM_MODE_DPMS_ON:
271 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
272 dac_cntl &= ~RADEON_DAC_PDWN;
273 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
274 RADEON_DAC_PDWN_G |
275 RADEON_DAC_PDWN_B);
276 break;
277 case DRM_MODE_DPMS_STANDBY:
278 case DRM_MODE_DPMS_SUSPEND:
279 case DRM_MODE_DPMS_OFF:
280 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
281 dac_cntl |= RADEON_DAC_PDWN;
282 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
283 RADEON_DAC_PDWN_G |
284 RADEON_DAC_PDWN_B);
285 break;
286 }
287
288 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
289 WREG32(RADEON_DAC_CNTL, dac_cntl);
290 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
291
292 if (rdev->is_atom_bios)
293 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
294 else
295 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
296
297 /* adjust pm to dpms change */
298 radeon_pm_compute_clocks(rdev);
299 }
300
301 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
302 {
303 struct radeon_device *rdev = encoder->dev->dev_private;
304
305 if (rdev->is_atom_bios)
306 radeon_atom_output_lock(encoder, true);
307 else
308 radeon_combios_output_lock(encoder, true);
309 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
310 }
311
312 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
313 {
314 struct radeon_device *rdev = encoder->dev->dev_private;
315
316 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
317
318 if (rdev->is_atom_bios)
319 radeon_atom_output_lock(encoder, false);
320 else
321 radeon_combios_output_lock(encoder, false);
322 }
323
324 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
325 struct drm_display_mode *mode,
326 struct drm_display_mode *adjusted_mode)
327 {
328 struct drm_device *dev = encoder->dev;
329 struct radeon_device *rdev = dev->dev_private;
330 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
332 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
333
334 DRM_DEBUG("\n");
335
336 if (radeon_crtc->crtc_id == 0) {
337 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
338 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
339 ~(RADEON_DISP_DAC_SOURCE_MASK);
340 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
341 } else {
342 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
343 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
344 }
345 } else {
346 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
347 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
348 ~(RADEON_DISP_DAC_SOURCE_MASK);
349 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
350 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
351 } else {
352 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
353 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
354 }
355 }
356
357 dac_cntl = (RADEON_DAC_MASK_ALL |
358 RADEON_DAC_VGA_ADR_EN |
359 /* TODO 6-bits */
360 RADEON_DAC_8BIT_EN);
361
362 WREG32_P(RADEON_DAC_CNTL,
363 dac_cntl,
364 RADEON_DAC_RANGE_CNTL |
365 RADEON_DAC_BLANKING);
366
367 if (radeon_encoder->enc_priv) {
368 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
369 dac_macro_cntl = p_dac->ps2_pdac_adj;
370 } else
371 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
372 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
373 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
374
375 if (rdev->is_atom_bios)
376 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
377 else
378 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
379 }
380
381 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
382 struct drm_connector *connector)
383 {
384 struct drm_device *dev = encoder->dev;
385 struct radeon_device *rdev = dev->dev_private;
386 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
387 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
388 enum drm_connector_status found = connector_status_disconnected;
389 bool color = true;
390
391 /* save the regs we need */
392 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
393 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
394 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
395 dac_cntl = RREG32(RADEON_DAC_CNTL);
396 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
397
398 tmp = vclk_ecp_cntl &
399 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
400 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
401
402 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
403 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
404
405 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
406 RADEON_DAC_FORCE_DATA_EN;
407
408 if (color)
409 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
410 else
411 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
412
413 if (ASIC_IS_R300(rdev))
414 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
415 else
416 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
417
418 WREG32(RADEON_DAC_EXT_CNTL, tmp);
419
420 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
421 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
422 WREG32(RADEON_DAC_CNTL, tmp);
423
424 tmp &= ~(RADEON_DAC_PDWN_R |
425 RADEON_DAC_PDWN_G |
426 RADEON_DAC_PDWN_B);
427
428 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
429
430 udelay(2000);
431
432 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
433 found = connector_status_connected;
434
435 /* restore the regs we used */
436 WREG32(RADEON_DAC_CNTL, dac_cntl);
437 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
438 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
439 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
440 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
441
442 return found;
443 }
444
445 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
446 .dpms = radeon_legacy_primary_dac_dpms,
447 .mode_fixup = radeon_legacy_mode_fixup,
448 .prepare = radeon_legacy_primary_dac_prepare,
449 .mode_set = radeon_legacy_primary_dac_mode_set,
450 .commit = radeon_legacy_primary_dac_commit,
451 .detect = radeon_legacy_primary_dac_detect,
452 .disable = radeon_legacy_encoder_disable,
453 };
454
455
456 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
457 .destroy = radeon_enc_destroy,
458 };
459
460 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
461 {
462 struct drm_device *dev = encoder->dev;
463 struct radeon_device *rdev = dev->dev_private;
464 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
465 DRM_DEBUG("\n");
466
467 switch (mode) {
468 case DRM_MODE_DPMS_ON:
469 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
470 break;
471 case DRM_MODE_DPMS_STANDBY:
472 case DRM_MODE_DPMS_SUSPEND:
473 case DRM_MODE_DPMS_OFF:
474 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
475 break;
476 }
477
478 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
479
480 if (rdev->is_atom_bios)
481 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
482 else
483 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
484
485 /* adjust pm to dpms change */
486 radeon_pm_compute_clocks(rdev);
487 }
488
489 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
490 {
491 struct radeon_device *rdev = encoder->dev->dev_private;
492
493 if (rdev->is_atom_bios)
494 radeon_atom_output_lock(encoder, true);
495 else
496 radeon_combios_output_lock(encoder, true);
497 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
498 }
499
500 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
501 {
502 struct radeon_device *rdev = encoder->dev->dev_private;
503
504 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
505
506 if (rdev->is_atom_bios)
507 radeon_atom_output_lock(encoder, true);
508 else
509 radeon_combios_output_lock(encoder, true);
510 }
511
512 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
513 struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515 {
516 struct drm_device *dev = encoder->dev;
517 struct radeon_device *rdev = dev->dev_private;
518 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
519 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
520 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
521 int i;
522
523 DRM_DEBUG("\n");
524
525 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
526 tmp &= 0xfffff;
527 if (rdev->family == CHIP_RV280) {
528 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
529 tmp ^= (1 << 22);
530 tmds_pll_cntl ^= (1 << 22);
531 }
532
533 if (radeon_encoder->enc_priv) {
534 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
535
536 for (i = 0; i < 4; i++) {
537 if (tmds->tmds_pll[i].freq == 0)
538 break;
539 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
540 tmp = tmds->tmds_pll[i].value ;
541 break;
542 }
543 }
544 }
545
546 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
547 if (tmp & 0xfff00000)
548 tmds_pll_cntl = tmp;
549 else {
550 tmds_pll_cntl &= 0xfff00000;
551 tmds_pll_cntl |= tmp;
552 }
553 } else
554 tmds_pll_cntl = tmp;
555
556 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
557 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
558
559 if (rdev->family == CHIP_R200 ||
560 rdev->family == CHIP_R100 ||
561 ASIC_IS_R300(rdev))
562 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
563 else /* RV chips got this bit reversed */
564 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
565
566 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
567 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
568 RADEON_FP_CRTC_DONT_SHADOW_HEND));
569
570 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
571
572 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
573 RADEON_FP_DFP_SYNC_SEL |
574 RADEON_FP_CRT_SYNC_SEL |
575 RADEON_FP_CRTC_LOCK_8DOT |
576 RADEON_FP_USE_SHADOW_EN |
577 RADEON_FP_CRTC_USE_SHADOW_VEND |
578 RADEON_FP_CRT_SYNC_ALT);
579
580 if (1) /* FIXME rgbBits == 8 */
581 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
582 else
583 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
584
585 if (radeon_crtc->crtc_id == 0) {
586 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
587 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
588 if (radeon_encoder->rmx_type != RMX_OFF)
589 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
590 else
591 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
592 } else
593 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
594 } else {
595 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
596 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
597 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
598 } else
599 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
600 }
601
602 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
603 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
604 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
605
606 if (rdev->is_atom_bios)
607 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
608 else
609 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
610 }
611
612 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
613 .dpms = radeon_legacy_tmds_int_dpms,
614 .mode_fixup = radeon_legacy_mode_fixup,
615 .prepare = radeon_legacy_tmds_int_prepare,
616 .mode_set = radeon_legacy_tmds_int_mode_set,
617 .commit = radeon_legacy_tmds_int_commit,
618 .disable = radeon_legacy_encoder_disable,
619 };
620
621
622 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
623 .destroy = radeon_enc_destroy,
624 };
625
626 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
627 {
628 struct drm_device *dev = encoder->dev;
629 struct radeon_device *rdev = dev->dev_private;
630 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
631 DRM_DEBUG("\n");
632
633 switch (mode) {
634 case DRM_MODE_DPMS_ON:
635 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
636 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
637 break;
638 case DRM_MODE_DPMS_STANDBY:
639 case DRM_MODE_DPMS_SUSPEND:
640 case DRM_MODE_DPMS_OFF:
641 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
642 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
643 break;
644 }
645
646 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
647
648 if (rdev->is_atom_bios)
649 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
650 else
651 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
652
653 /* adjust pm to dpms change */
654 radeon_pm_compute_clocks(rdev);
655 }
656
657 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
658 {
659 struct radeon_device *rdev = encoder->dev->dev_private;
660
661 if (rdev->is_atom_bios)
662 radeon_atom_output_lock(encoder, true);
663 else
664 radeon_combios_output_lock(encoder, true);
665 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
666 }
667
668 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
669 {
670 struct radeon_device *rdev = encoder->dev->dev_private;
671 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
672
673 if (rdev->is_atom_bios)
674 radeon_atom_output_lock(encoder, false);
675 else
676 radeon_combios_output_lock(encoder, false);
677 }
678
679 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
680 struct drm_display_mode *mode,
681 struct drm_display_mode *adjusted_mode)
682 {
683 struct drm_device *dev = encoder->dev;
684 struct radeon_device *rdev = dev->dev_private;
685 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
686 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
687 uint32_t fp2_gen_cntl;
688
689 DRM_DEBUG("\n");
690
691 if (rdev->is_atom_bios) {
692 radeon_encoder->pixel_clock = adjusted_mode->clock;
693 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
694 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
695 } else {
696 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
697
698 if (1) /* FIXME rgbBits == 8 */
699 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
700 else
701 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
702
703 fp2_gen_cntl &= ~(RADEON_FP2_ON |
704 RADEON_FP2_DVO_EN |
705 RADEON_FP2_DVO_RATE_SEL_SDR);
706
707 /* XXX: these are oem specific */
708 if (ASIC_IS_R300(rdev)) {
709 if ((dev->pdev->device == 0x4850) &&
710 (dev->pdev->subsystem_vendor == 0x1028) &&
711 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
712 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
713 else
714 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
715
716 /*if (mode->clock > 165000)
717 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
718 }
719 if (!radeon_combios_external_tmds_setup(encoder))
720 radeon_external_tmds_setup(encoder);
721 }
722
723 if (radeon_crtc->crtc_id == 0) {
724 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
725 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
726 if (radeon_encoder->rmx_type != RMX_OFF)
727 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
728 else
729 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
730 } else
731 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
732 } else {
733 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
734 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
735 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
736 } else
737 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
738 }
739
740 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
741
742 if (rdev->is_atom_bios)
743 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
744 else
745 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
746 }
747
748 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
749 {
750 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
751 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
752 if (tmds) {
753 if (tmds->i2c_bus)
754 radeon_i2c_destroy(tmds->i2c_bus);
755 }
756 kfree(radeon_encoder->enc_priv);
757 drm_encoder_cleanup(encoder);
758 kfree(radeon_encoder);
759 }
760
761 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
762 .dpms = radeon_legacy_tmds_ext_dpms,
763 .mode_fixup = radeon_legacy_mode_fixup,
764 .prepare = radeon_legacy_tmds_ext_prepare,
765 .mode_set = radeon_legacy_tmds_ext_mode_set,
766 .commit = radeon_legacy_tmds_ext_commit,
767 .disable = radeon_legacy_encoder_disable,
768 };
769
770
771 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
772 .destroy = radeon_ext_tmds_enc_destroy,
773 };
774
775 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
776 {
777 struct drm_device *dev = encoder->dev;
778 struct radeon_device *rdev = dev->dev_private;
779 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
780 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
781 uint32_t tv_master_cntl = 0;
782 bool is_tv;
783 DRM_DEBUG("\n");
784
785 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
786
787 if (rdev->family == CHIP_R200)
788 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
789 else {
790 if (is_tv)
791 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
792 else
793 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
794 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
795 }
796
797 switch (mode) {
798 case DRM_MODE_DPMS_ON:
799 if (rdev->family == CHIP_R200) {
800 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
801 } else {
802 if (is_tv)
803 tv_master_cntl |= RADEON_TV_ON;
804 else
805 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
806
807 if (rdev->family == CHIP_R420 ||
808 rdev->family == CHIP_R423 ||
809 rdev->family == CHIP_RV410)
810 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
811 R420_TV_DAC_GDACPD |
812 R420_TV_DAC_BDACPD |
813 RADEON_TV_DAC_BGSLEEP);
814 else
815 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
816 RADEON_TV_DAC_GDACPD |
817 RADEON_TV_DAC_BDACPD |
818 RADEON_TV_DAC_BGSLEEP);
819 }
820 break;
821 case DRM_MODE_DPMS_STANDBY:
822 case DRM_MODE_DPMS_SUSPEND:
823 case DRM_MODE_DPMS_OFF:
824 if (rdev->family == CHIP_R200)
825 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
826 else {
827 if (is_tv)
828 tv_master_cntl &= ~RADEON_TV_ON;
829 else
830 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
831
832 if (rdev->family == CHIP_R420 ||
833 rdev->family == CHIP_R423 ||
834 rdev->family == CHIP_RV410)
835 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
836 R420_TV_DAC_GDACPD |
837 R420_TV_DAC_BDACPD |
838 RADEON_TV_DAC_BGSLEEP);
839 else
840 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
841 RADEON_TV_DAC_GDACPD |
842 RADEON_TV_DAC_BDACPD |
843 RADEON_TV_DAC_BGSLEEP);
844 }
845 break;
846 }
847
848 if (rdev->family == CHIP_R200) {
849 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
850 } else {
851 if (is_tv)
852 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
853 else
854 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
855 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
856 }
857
858 if (rdev->is_atom_bios)
859 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
860 else
861 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
862
863 /* adjust pm to dpms change */
864 radeon_pm_compute_clocks(rdev);
865 }
866
867 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
868 {
869 struct radeon_device *rdev = encoder->dev->dev_private;
870
871 if (rdev->is_atom_bios)
872 radeon_atom_output_lock(encoder, true);
873 else
874 radeon_combios_output_lock(encoder, true);
875 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
876 }
877
878 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
879 {
880 struct radeon_device *rdev = encoder->dev->dev_private;
881
882 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
883
884 if (rdev->is_atom_bios)
885 radeon_atom_output_lock(encoder, true);
886 else
887 radeon_combios_output_lock(encoder, true);
888 }
889
890 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
891 struct drm_display_mode *mode,
892 struct drm_display_mode *adjusted_mode)
893 {
894 struct drm_device *dev = encoder->dev;
895 struct radeon_device *rdev = dev->dev_private;
896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
897 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
898 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
899 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
900 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
901 bool is_tv = false;
902
903 DRM_DEBUG("\n");
904
905 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
906
907 if (rdev->family != CHIP_R200) {
908 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
909 if (rdev->family == CHIP_R420 ||
910 rdev->family == CHIP_R423 ||
911 rdev->family == CHIP_RV410) {
912 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
913 RADEON_TV_DAC_BGADJ_MASK |
914 R420_TV_DAC_DACADJ_MASK |
915 R420_TV_DAC_RDACPD |
916 R420_TV_DAC_GDACPD |
917 R420_TV_DAC_BDACPD |
918 R420_TV_DAC_TVENABLE);
919 } else {
920 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
921 RADEON_TV_DAC_BGADJ_MASK |
922 RADEON_TV_DAC_DACADJ_MASK |
923 RADEON_TV_DAC_RDACPD |
924 RADEON_TV_DAC_GDACPD |
925 RADEON_TV_DAC_BDACPD);
926 }
927
928 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
929
930 if (is_tv) {
931 if (tv_dac->tv_std == TV_STD_NTSC ||
932 tv_dac->tv_std == TV_STD_NTSC_J ||
933 tv_dac->tv_std == TV_STD_PAL_M ||
934 tv_dac->tv_std == TV_STD_PAL_60)
935 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
936 else
937 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
938
939 if (tv_dac->tv_std == TV_STD_NTSC ||
940 tv_dac->tv_std == TV_STD_NTSC_J)
941 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
942 else
943 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
944 } else
945 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
946 tv_dac->ps2_tvdac_adj);
947
948 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
949 }
950
951 if (ASIC_IS_R300(rdev)) {
952 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
953 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
954 }
955
956 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
957 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
958 else
959 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
960
961 if (rdev->family == CHIP_R200)
962 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
963
964 if (is_tv) {
965 uint32_t dac_cntl;
966
967 dac_cntl = RREG32(RADEON_DAC_CNTL);
968 dac_cntl &= ~RADEON_DAC_TVO_EN;
969 WREG32(RADEON_DAC_CNTL, dac_cntl);
970
971 if (ASIC_IS_R300(rdev))
972 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
973
974 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
975 if (radeon_crtc->crtc_id == 0) {
976 if (ASIC_IS_R300(rdev)) {
977 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
978 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
979 RADEON_DISP_TV_SOURCE_CRTC);
980 }
981 if (rdev->family >= CHIP_R200) {
982 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
983 } else {
984 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
985 }
986 } else {
987 if (ASIC_IS_R300(rdev)) {
988 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
989 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
990 }
991 if (rdev->family >= CHIP_R200) {
992 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
993 } else {
994 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
995 }
996 }
997 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
998 } else {
999
1000 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1001
1002 if (radeon_crtc->crtc_id == 0) {
1003 if (ASIC_IS_R300(rdev)) {
1004 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1005 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1006 } else if (rdev->family == CHIP_R200) {
1007 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1008 RADEON_FP2_DVO_RATE_SEL_SDR);
1009 } else
1010 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1011 } else {
1012 if (ASIC_IS_R300(rdev)) {
1013 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1014 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1015 } else if (rdev->family == CHIP_R200) {
1016 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1017 RADEON_FP2_DVO_RATE_SEL_SDR);
1018 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1019 } else
1020 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1021 }
1022 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1023 }
1024
1025 if (ASIC_IS_R300(rdev)) {
1026 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1027 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1028 }
1029
1030 if (rdev->family >= CHIP_R200)
1031 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1032 else
1033 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1034
1035 if (rdev->family == CHIP_R200)
1036 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1037
1038 if (is_tv)
1039 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1040
1041 if (rdev->is_atom_bios)
1042 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1043 else
1044 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1045
1046 }
1047
1048 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1049 struct drm_connector *connector)
1050 {
1051 struct drm_device *dev = encoder->dev;
1052 struct radeon_device *rdev = dev->dev_private;
1053 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1054 uint32_t disp_output_cntl, gpiopad_a, tmp;
1055 bool found = false;
1056
1057 /* save regs needed */
1058 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1059 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1060 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1061 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1062 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1063 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1064
1065 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1066
1067 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1068
1069 WREG32(RADEON_CRTC2_GEN_CNTL,
1070 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1071
1072 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1073 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1074 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1075
1076 WREG32(RADEON_DAC_EXT_CNTL,
1077 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1078 RADEON_DAC2_FORCE_DATA_EN |
1079 RADEON_DAC_FORCE_DATA_SEL_RGB |
1080 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1081
1082 WREG32(RADEON_TV_DAC_CNTL,
1083 RADEON_TV_DAC_STD_NTSC |
1084 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1085 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1086
1087 RREG32(RADEON_TV_DAC_CNTL);
1088 mdelay(4);
1089
1090 WREG32(RADEON_TV_DAC_CNTL,
1091 RADEON_TV_DAC_NBLANK |
1092 RADEON_TV_DAC_NHOLD |
1093 RADEON_TV_MONITOR_DETECT_EN |
1094 RADEON_TV_DAC_STD_NTSC |
1095 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1096 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1097
1098 RREG32(RADEON_TV_DAC_CNTL);
1099 mdelay(6);
1100
1101 tmp = RREG32(RADEON_TV_DAC_CNTL);
1102 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1103 found = true;
1104 DRM_DEBUG("S-video TV connection detected\n");
1105 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1106 found = true;
1107 DRM_DEBUG("Composite TV connection detected\n");
1108 }
1109
1110 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1111 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1112 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1113 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1114 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1115 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1116 return found;
1117 }
1118
1119 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1120 struct drm_connector *connector)
1121 {
1122 struct drm_device *dev = encoder->dev;
1123 struct radeon_device *rdev = dev->dev_private;
1124 uint32_t tv_dac_cntl, dac_cntl2;
1125 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1126 bool found = false;
1127
1128 if (ASIC_IS_R300(rdev))
1129 return r300_legacy_tv_detect(encoder, connector);
1130
1131 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1132 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1133 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1134 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1135 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1136
1137 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1138 WREG32(RADEON_DAC_CNTL2, tmp);
1139
1140 tmp = tv_master_cntl | RADEON_TV_ON;
1141 tmp &= ~(RADEON_TV_ASYNC_RST |
1142 RADEON_RESTART_PHASE_FIX |
1143 RADEON_CRT_FIFO_CE_EN |
1144 RADEON_TV_FIFO_CE_EN |
1145 RADEON_RE_SYNC_NOW_SEL_MASK);
1146 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1147 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1148
1149 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1150 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1151 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1152
1153 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1154 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1155 else
1156 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1157 WREG32(RADEON_TV_DAC_CNTL, tmp);
1158
1159 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1160 RADEON_RED_MX_FORCE_DAC_DATA |
1161 RADEON_GRN_MX_FORCE_DAC_DATA |
1162 RADEON_BLU_MX_FORCE_DAC_DATA |
1163 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1164 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1165
1166 mdelay(3);
1167 tmp = RREG32(RADEON_TV_DAC_CNTL);
1168 if (tmp & RADEON_TV_DAC_GDACDET) {
1169 found = true;
1170 DRM_DEBUG("S-video TV connection detected\n");
1171 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1172 found = true;
1173 DRM_DEBUG("Composite TV connection detected\n");
1174 }
1175
1176 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1177 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1178 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1179 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1180 return found;
1181 }
1182
1183 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1184 struct drm_connector *connector)
1185 {
1186 struct drm_device *dev = encoder->dev;
1187 struct radeon_device *rdev = dev->dev_private;
1188 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1189 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1190 enum drm_connector_status found = connector_status_disconnected;
1191 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1192 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1193 bool color = true;
1194
1195 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1196 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1197 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1198 bool tv_detect;
1199
1200 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1201 return connector_status_disconnected;
1202
1203 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1204 if (tv_detect && tv_dac)
1205 found = connector_status_connected;
1206 return found;
1207 }
1208
1209 /* don't probe if the encoder is being used for something else not CRT related */
1210 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1211 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1212 return connector_status_disconnected;
1213 }
1214
1215 /* save the regs we need */
1216 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1217 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1218 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1219 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1220 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1221 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1222 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1223 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1224
1225 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1226 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1227 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1228
1229 if (ASIC_IS_R300(rdev))
1230 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1231
1232 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1233 tmp |= RADEON_CRTC2_CRT2_ON |
1234 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1235
1236 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1237
1238 if (ASIC_IS_R300(rdev)) {
1239 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1240 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1241 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1242 } else {
1243 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1244 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1245 }
1246
1247 tmp = RADEON_TV_DAC_NBLANK |
1248 RADEON_TV_DAC_NHOLD |
1249 RADEON_TV_MONITOR_DETECT_EN |
1250 RADEON_TV_DAC_STD_PS2;
1251
1252 WREG32(RADEON_TV_DAC_CNTL, tmp);
1253
1254 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1255 RADEON_DAC2_FORCE_DATA_EN;
1256
1257 if (color)
1258 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1259 else
1260 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1261
1262 if (ASIC_IS_R300(rdev))
1263 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1264 else
1265 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1266
1267 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1268
1269 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1270 WREG32(RADEON_DAC_CNTL2, tmp);
1271
1272 udelay(10000);
1273
1274 if (ASIC_IS_R300(rdev)) {
1275 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1276 found = connector_status_connected;
1277 } else {
1278 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1279 found = connector_status_connected;
1280 }
1281
1282 /* restore regs we used */
1283 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1284 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1285 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1286 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1287
1288 if (ASIC_IS_R300(rdev)) {
1289 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1290 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1291 } else {
1292 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1293 }
1294 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1295
1296 return found;
1297
1298 }
1299
1300 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1301 .dpms = radeon_legacy_tv_dac_dpms,
1302 .mode_fixup = radeon_legacy_mode_fixup,
1303 .prepare = radeon_legacy_tv_dac_prepare,
1304 .mode_set = radeon_legacy_tv_dac_mode_set,
1305 .commit = radeon_legacy_tv_dac_commit,
1306 .detect = radeon_legacy_tv_dac_detect,
1307 .disable = radeon_legacy_encoder_disable,
1308 };
1309
1310
1311 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1312 .destroy = radeon_enc_destroy,
1313 };
1314
1315
1316 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1317 {
1318 struct drm_device *dev = encoder->base.dev;
1319 struct radeon_device *rdev = dev->dev_private;
1320 struct radeon_encoder_int_tmds *tmds = NULL;
1321 bool ret;
1322
1323 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1324
1325 if (!tmds)
1326 return NULL;
1327
1328 if (rdev->is_atom_bios)
1329 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1330 else
1331 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1332
1333 if (ret == false)
1334 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1335
1336 return tmds;
1337 }
1338
1339 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1340 {
1341 struct drm_device *dev = encoder->base.dev;
1342 struct radeon_device *rdev = dev->dev_private;
1343 struct radeon_encoder_ext_tmds *tmds = NULL;
1344 bool ret;
1345
1346 if (rdev->is_atom_bios)
1347 return NULL;
1348
1349 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1350
1351 if (!tmds)
1352 return NULL;
1353
1354 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1355
1356 if (ret == false)
1357 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1358
1359 return tmds;
1360 }
1361
1362 void
1363 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1364 {
1365 struct radeon_device *rdev = dev->dev_private;
1366 struct drm_encoder *encoder;
1367 struct radeon_encoder *radeon_encoder;
1368
1369 /* see if we already added it */
1370 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1371 radeon_encoder = to_radeon_encoder(encoder);
1372 if (radeon_encoder->encoder_id == encoder_id) {
1373 radeon_encoder->devices |= supported_device;
1374 return;
1375 }
1376
1377 }
1378
1379 /* add a new one */
1380 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1381 if (!radeon_encoder)
1382 return;
1383
1384 encoder = &radeon_encoder->base;
1385 if (rdev->flags & RADEON_SINGLE_CRTC)
1386 encoder->possible_crtcs = 0x1;
1387 else
1388 encoder->possible_crtcs = 0x3;
1389
1390 radeon_encoder->enc_priv = NULL;
1391
1392 radeon_encoder->encoder_id = encoder_id;
1393 radeon_encoder->devices = supported_device;
1394 radeon_encoder->rmx_type = RMX_OFF;
1395
1396 switch (radeon_encoder->encoder_id) {
1397 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1398 encoder->possible_crtcs = 0x1;
1399 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1400 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1401 if (rdev->is_atom_bios)
1402 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1403 else
1404 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1405 radeon_encoder->rmx_type = RMX_FULL;
1406 break;
1407 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1408 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1409 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1410 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1411 break;
1412 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1413 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1414 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1415 if (rdev->is_atom_bios)
1416 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1417 else
1418 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1419 break;
1420 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1421 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1422 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1423 if (rdev->is_atom_bios)
1424 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1425 else
1426 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1427 break;
1428 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1429 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1430 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1431 if (!rdev->is_atom_bios)
1432 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1433 break;
1434 }
1435 }
Linux with added FPC-III support