Staging: netwave: delete the driver
[linux/fpc-iii.git] / drivers / pci / pci.c
blob37499127c801e5db16927377981e6a721bf0bd0d
1 /*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pm.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
26 #include "pci.h"
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
36 int pci_pci_problems;
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_dev_d3_sleep(struct pci_dev *dev)
43 unsigned int delay = dev->d3_delay;
45 if (delay < pci_pm_d3_delay)
46 delay = pci_pm_d3_delay;
48 msleep(delay);
51 #ifdef CONFIG_PCI_DOMAINS
52 int pci_domains_supported = 1;
53 #endif
55 #define DEFAULT_CARDBUS_IO_SIZE (256)
56 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
57 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
58 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
59 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
61 #define DEFAULT_HOTPLUG_IO_SIZE (256)
62 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
63 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
64 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
65 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
68 * The default CLS is used if arch didn't set CLS explicitly and not
69 * all pci devices agree on the same value. Arch can override either
70 * the dfl or actual value as it sees fit. Don't forget this is
71 * measured in 32-bit words, not bytes.
73 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
74 u8 pci_cache_line_size;
76 /**
77 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
78 * @bus: pointer to PCI bus structure to search
80 * Given a PCI bus, returns the highest PCI bus number present in the set
81 * including the given PCI bus and its list of child PCI buses.
83 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
85 struct list_head *tmp;
86 unsigned char max, n;
88 max = bus->subordinate;
89 list_for_each(tmp, &bus->children) {
90 n = pci_bus_max_busnr(pci_bus_b(tmp));
91 if(n > max)
92 max = n;
94 return max;
96 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
98 #ifdef CONFIG_HAS_IOMEM
99 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
102 * Make sure the BAR is actually a memory resource, not an IO resource
104 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
105 WARN_ON(1);
106 return NULL;
108 return ioremap_nocache(pci_resource_start(pdev, bar),
109 pci_resource_len(pdev, bar));
111 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
112 #endif
114 #if 0
116 * pci_max_busnr - returns maximum PCI bus number
118 * Returns the highest PCI bus number present in the system global list of
119 * PCI buses.
121 unsigned char __devinit
122 pci_max_busnr(void)
124 struct pci_bus *bus = NULL;
125 unsigned char max, n;
127 max = 0;
128 while ((bus = pci_find_next_bus(bus)) != NULL) {
129 n = pci_bus_max_busnr(bus);
130 if(n > max)
131 max = n;
133 return max;
136 #endif /* 0 */
138 #define PCI_FIND_CAP_TTL 48
140 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
141 u8 pos, int cap, int *ttl)
143 u8 id;
145 while ((*ttl)--) {
146 pci_bus_read_config_byte(bus, devfn, pos, &pos);
147 if (pos < 0x40)
148 break;
149 pos &= ~3;
150 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
151 &id);
152 if (id == 0xff)
153 break;
154 if (id == cap)
155 return pos;
156 pos += PCI_CAP_LIST_NEXT;
158 return 0;
161 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
162 u8 pos, int cap)
164 int ttl = PCI_FIND_CAP_TTL;
166 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
169 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
171 return __pci_find_next_cap(dev->bus, dev->devfn,
172 pos + PCI_CAP_LIST_NEXT, cap);
174 EXPORT_SYMBOL_GPL(pci_find_next_capability);
176 static int __pci_bus_find_cap_start(struct pci_bus *bus,
177 unsigned int devfn, u8 hdr_type)
179 u16 status;
181 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
182 if (!(status & PCI_STATUS_CAP_LIST))
183 return 0;
185 switch (hdr_type) {
186 case PCI_HEADER_TYPE_NORMAL:
187 case PCI_HEADER_TYPE_BRIDGE:
188 return PCI_CAPABILITY_LIST;
189 case PCI_HEADER_TYPE_CARDBUS:
190 return PCI_CB_CAPABILITY_LIST;
191 default:
192 return 0;
195 return 0;
199 * pci_find_capability - query for devices' capabilities
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Tell if a device supports a given PCI capability.
204 * Returns the address of the requested capability structure within the
205 * device's PCI configuration space or 0 in case the device does not
206 * support it. Possible values for @cap:
208 * %PCI_CAP_ID_PM Power Management
209 * %PCI_CAP_ID_AGP Accelerated Graphics Port
210 * %PCI_CAP_ID_VPD Vital Product Data
211 * %PCI_CAP_ID_SLOTID Slot Identification
212 * %PCI_CAP_ID_MSI Message Signalled Interrupts
213 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
214 * %PCI_CAP_ID_PCIX PCI-X
215 * %PCI_CAP_ID_EXP PCI Express
217 int pci_find_capability(struct pci_dev *dev, int cap)
219 int pos;
221 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
222 if (pos)
223 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
225 return pos;
229 * pci_bus_find_capability - query for devices' capabilities
230 * @bus: the PCI bus to query
231 * @devfn: PCI device to query
232 * @cap: capability code
234 * Like pci_find_capability() but works for pci devices that do not have a
235 * pci_dev structure set up yet.
237 * Returns the address of the requested capability structure within the
238 * device's PCI configuration space or 0 in case the device does not
239 * support it.
241 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
243 int pos;
244 u8 hdr_type;
246 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
248 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
249 if (pos)
250 pos = __pci_find_next_cap(bus, devfn, pos, cap);
252 return pos;
256 * pci_find_ext_capability - Find an extended capability
257 * @dev: PCI device to query
258 * @cap: capability code
260 * Returns the address of the requested extended capability structure
261 * within the device's PCI configuration space or 0 if the device does
262 * not support it. Possible values for @cap:
264 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
265 * %PCI_EXT_CAP_ID_VC Virtual Channel
266 * %PCI_EXT_CAP_ID_DSN Device Serial Number
267 * %PCI_EXT_CAP_ID_PWR Power Budgeting
269 int pci_find_ext_capability(struct pci_dev *dev, int cap)
271 u32 header;
272 int ttl;
273 int pos = PCI_CFG_SPACE_SIZE;
275 /* minimum 8 bytes per capability */
276 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
278 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
279 return 0;
281 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
282 return 0;
285 * If we have no capabilities, this is indicated by cap ID,
286 * cap version and next pointer all being 0.
288 if (header == 0)
289 return 0;
291 while (ttl-- > 0) {
292 if (PCI_EXT_CAP_ID(header) == cap)
293 return pos;
295 pos = PCI_EXT_CAP_NEXT(header);
296 if (pos < PCI_CFG_SPACE_SIZE)
297 break;
299 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 break;
303 return 0;
305 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
308 * pci_bus_find_ext_capability - find an extended capability
309 * @bus: the PCI bus to query
310 * @devfn: PCI device to query
311 * @cap: capability code
313 * Like pci_find_ext_capability() but works for pci devices that do not have a
314 * pci_dev structure set up yet.
316 * Returns the address of the requested capability structure within the
317 * device's PCI configuration space or 0 in case the device does not
318 * support it.
320 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
321 int cap)
323 u32 header;
324 int ttl;
325 int pos = PCI_CFG_SPACE_SIZE;
327 /* minimum 8 bytes per capability */
328 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
330 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
331 return 0;
332 if (header == 0xffffffff || header == 0)
333 return 0;
335 while (ttl-- > 0) {
336 if (PCI_EXT_CAP_ID(header) == cap)
337 return pos;
339 pos = PCI_EXT_CAP_NEXT(header);
340 if (pos < PCI_CFG_SPACE_SIZE)
341 break;
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
344 break;
347 return 0;
350 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
352 int rc, ttl = PCI_FIND_CAP_TTL;
353 u8 cap, mask;
355 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
356 mask = HT_3BIT_CAP_MASK;
357 else
358 mask = HT_5BIT_CAP_MASK;
360 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
361 PCI_CAP_ID_HT, &ttl);
362 while (pos) {
363 rc = pci_read_config_byte(dev, pos + 3, &cap);
364 if (rc != PCIBIOS_SUCCESSFUL)
365 return 0;
367 if ((cap & mask) == ht_cap)
368 return pos;
370 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
371 pos + PCI_CAP_LIST_NEXT,
372 PCI_CAP_ID_HT, &ttl);
375 return 0;
378 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @pos: Position from which to continue searching
381 * @ht_cap: Hypertransport capability code
383 * To be used in conjunction with pci_find_ht_capability() to search for
384 * all capabilities matching @ht_cap. @pos should always be a value returned
385 * from pci_find_ht_capability().
387 * NB. To be 100% safe against broken PCI devices, the caller should take
388 * steps to avoid an infinite loop.
390 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
392 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
394 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
397 * pci_find_ht_capability - query a device's Hypertransport capabilities
398 * @dev: PCI device to query
399 * @ht_cap: Hypertransport capability code
401 * Tell if a device supports a given Hypertransport capability.
402 * Returns an address within the device's PCI configuration space
403 * or 0 in case the device does not support the request capability.
404 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
405 * which has a Hypertransport capability matching @ht_cap.
407 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
409 int pos;
411 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
412 if (pos)
413 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
415 return pos;
417 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
420 * pci_find_parent_resource - return resource region of parent bus of given region
421 * @dev: PCI device structure contains resources to be searched
422 * @res: child resource record for which parent is sought
424 * For given resource region of given device, return the resource
425 * region of parent bus the given region is contained in or where
426 * it should be allocated from.
428 struct resource *
429 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
431 const struct pci_bus *bus = dev->bus;
432 int i;
433 struct resource *best = NULL, *r;
435 pci_bus_for_each_resource(bus, r, i) {
436 if (!r)
437 continue;
438 if (res->start && !(res->start >= r->start && res->end <= r->end))
439 continue; /* Not contained */
440 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
441 continue; /* Wrong type */
442 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
443 return r; /* Exact match */
444 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
445 if (r->flags & IORESOURCE_PREFETCH)
446 continue;
447 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
448 if (!best)
449 best = r;
451 return best;
455 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
456 * @dev: PCI device to have its BARs restored
458 * Restore the BAR values for a given device, so as to make it
459 * accessible by its driver.
461 static void
462 pci_restore_bars(struct pci_dev *dev)
464 int i;
466 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
467 pci_update_resource(dev, i);
470 static struct pci_platform_pm_ops *pci_platform_pm;
472 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
474 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
475 || !ops->sleep_wake || !ops->can_wakeup)
476 return -EINVAL;
477 pci_platform_pm = ops;
478 return 0;
481 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
483 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
486 static inline int platform_pci_set_power_state(struct pci_dev *dev,
487 pci_power_t t)
489 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
492 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
494 return pci_platform_pm ?
495 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
498 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
500 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
503 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
505 return pci_platform_pm ?
506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
509 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
511 return pci_platform_pm ?
512 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
517 * given PCI device
518 * @dev: PCI device to handle.
519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
521 * RETURN VALUE:
522 * -EINVAL if the requested state is invalid.
523 * -EIO if device does not support PCI PM or its PM capabilities register has a
524 * wrong version, or device doesn't support the requested state.
525 * 0 if device already is in the requested state.
526 * 0 if device's power state has been successfully changed.
528 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
530 u16 pmcsr;
531 bool need_restore = false;
533 /* Check if we're already there */
534 if (dev->current_state == state)
535 return 0;
537 if (!dev->pm_cap)
538 return -EIO;
540 if (state < PCI_D0 || state > PCI_D3hot)
541 return -EINVAL;
543 /* Validate current state:
544 * Can enter D0 from any state, but if we can only go deeper
545 * to sleep if we're already in a low power state
547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548 && dev->current_state > state) {
549 dev_err(&dev->dev, "invalid power transition "
550 "(from state %d to %d)\n", dev->current_state, state);
551 return -EINVAL;
554 /* check if this device supports the desired state */
555 if ((state == PCI_D1 && !dev->d1_support)
556 || (state == PCI_D2 && !dev->d2_support))
557 return -EIO;
559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
561 /* If we're (effectively) in D3, force entire word to 0.
562 * This doesn't affect PME_Status, disables PME_En, and
563 * sets PowerState to 0.
565 switch (dev->current_state) {
566 case PCI_D0:
567 case PCI_D1:
568 case PCI_D2:
569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
570 pmcsr |= state;
571 break;
572 case PCI_D3hot:
573 case PCI_D3cold:
574 case PCI_UNKNOWN: /* Boot-up */
575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
577 need_restore = true;
578 /* Fall-through: force to D0 */
579 default:
580 pmcsr = 0;
581 break;
584 /* enter specified state */
585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
587 /* Mandatory power management transition delays */
588 /* see PCI PM 1.1 5.6.1 table 18 */
589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590 pci_dev_d3_sleep(dev);
591 else if (state == PCI_D2 || dev->current_state == PCI_D2)
592 udelay(PCI_PM_D2_DELAY);
594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
596 if (dev->current_state != state && printk_ratelimit())
597 dev_info(&dev->dev, "Refused to change power state, "
598 "currently in D%d\n", dev->current_state);
600 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
601 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
602 * from D3hot to D0 _may_ perform an internal reset, thereby
603 * going to "D0 Uninitialized" rather than "D0 Initialized".
604 * For example, at least some versions of the 3c905B and the
605 * 3c556B exhibit this behaviour.
607 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
608 * devices in a D3hot state at boot. Consequently, we need to
609 * restore at least the BARs so that the device will be
610 * accessible to its driver.
612 if (need_restore)
613 pci_restore_bars(dev);
615 if (dev->bus->self)
616 pcie_aspm_pm_state_change(dev->bus->self);
618 return 0;
622 * pci_update_current_state - Read PCI power state of given device from its
623 * PCI PM registers and cache it
624 * @dev: PCI device to handle.
625 * @state: State to cache in case the device doesn't have the PM capability
627 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
629 if (dev->pm_cap) {
630 u16 pmcsr;
632 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
633 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
634 } else {
635 dev->current_state = state;
640 * pci_platform_power_transition - Use platform to change device power state
641 * @dev: PCI device to handle.
642 * @state: State to put the device into.
644 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
646 int error;
648 if (platform_pci_power_manageable(dev)) {
649 error = platform_pci_set_power_state(dev, state);
650 if (!error)
651 pci_update_current_state(dev, state);
652 } else {
653 error = -ENODEV;
654 /* Fall back to PCI_D0 if native PM is not supported */
655 if (!dev->pm_cap)
656 dev->current_state = PCI_D0;
659 return error;
663 * __pci_start_power_transition - Start power transition of a PCI device
664 * @dev: PCI device to handle.
665 * @state: State to put the device into.
667 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
669 if (state == PCI_D0)
670 pci_platform_power_transition(dev, PCI_D0);
674 * __pci_complete_power_transition - Complete power transition of a PCI device
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
678 * This function should not be called directly by device drivers.
680 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
682 return state >= PCI_D0 ?
683 pci_platform_power_transition(dev, state) : -EINVAL;
685 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
688 * pci_set_power_state - Set the power state of a PCI device
689 * @dev: PCI device to handle.
690 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
692 * Transition a device to a new power state, using the platform firmware and/or
693 * the device's PCI PM registers.
695 * RETURN VALUE:
696 * -EINVAL if the requested state is invalid.
697 * -EIO if device does not support PCI PM or its PM capabilities register has a
698 * wrong version, or device doesn't support the requested state.
699 * 0 if device already is in the requested state.
700 * 0 if device's power state has been successfully changed.
702 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
704 int error;
706 /* bound the state we're entering */
707 if (state > PCI_D3hot)
708 state = PCI_D3hot;
709 else if (state < PCI_D0)
710 state = PCI_D0;
711 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
713 * If the device or the parent bridge do not support PCI PM,
714 * ignore the request if we're doing anything other than putting
715 * it into D0 (which would only happen on boot).
717 return 0;
719 __pci_start_power_transition(dev, state);
721 /* This device is quirked not to be put into D3, so
722 don't put it in D3 */
723 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
724 return 0;
726 error = pci_raw_set_power_state(dev, state);
728 if (!__pci_complete_power_transition(dev, state))
729 error = 0;
731 return error;
735 * pci_choose_state - Choose the power state of a PCI device
736 * @dev: PCI device to be suspended
737 * @state: target sleep state for the whole system. This is the value
738 * that is passed to suspend() function.
740 * Returns PCI power state suitable for given device and given system
741 * message.
744 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
746 pci_power_t ret;
748 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
749 return PCI_D0;
751 ret = platform_pci_choose_state(dev);
752 if (ret != PCI_POWER_ERROR)
753 return ret;
755 switch (state.event) {
756 case PM_EVENT_ON:
757 return PCI_D0;
758 case PM_EVENT_FREEZE:
759 case PM_EVENT_PRETHAW:
760 /* REVISIT both freeze and pre-thaw "should" use D0 */
761 case PM_EVENT_SUSPEND:
762 case PM_EVENT_HIBERNATE:
763 return PCI_D3hot;
764 default:
765 dev_info(&dev->dev, "unrecognized suspend event %d\n",
766 state.event);
767 BUG();
769 return PCI_D0;
772 EXPORT_SYMBOL(pci_choose_state);
774 #define PCI_EXP_SAVE_REGS 7
776 #define pcie_cap_has_devctl(type, flags) 1
777 #define pcie_cap_has_lnkctl(type, flags) \
778 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
779 (type == PCI_EXP_TYPE_ROOT_PORT || \
780 type == PCI_EXP_TYPE_ENDPOINT || \
781 type == PCI_EXP_TYPE_LEG_END))
782 #define pcie_cap_has_sltctl(type, flags) \
783 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
784 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
785 (type == PCI_EXP_TYPE_DOWNSTREAM && \
786 (flags & PCI_EXP_FLAGS_SLOT))))
787 #define pcie_cap_has_rtctl(type, flags) \
788 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
789 (type == PCI_EXP_TYPE_ROOT_PORT || \
790 type == PCI_EXP_TYPE_RC_EC))
791 #define pcie_cap_has_devctl2(type, flags) \
792 ((flags & PCI_EXP_FLAGS_VERS) > 1)
793 #define pcie_cap_has_lnkctl2(type, flags) \
794 ((flags & PCI_EXP_FLAGS_VERS) > 1)
795 #define pcie_cap_has_sltctl2(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1)
798 static int pci_save_pcie_state(struct pci_dev *dev)
800 int pos, i = 0;
801 struct pci_cap_saved_state *save_state;
802 u16 *cap;
803 u16 flags;
805 pos = pci_pcie_cap(dev);
806 if (!pos)
807 return 0;
809 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
810 if (!save_state) {
811 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
812 return -ENOMEM;
814 cap = (u16 *)&save_state->data[0];
816 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
818 if (pcie_cap_has_devctl(dev->pcie_type, flags))
819 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
820 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
821 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
822 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
823 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
824 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
825 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
826 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
827 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
828 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
829 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
830 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
831 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
833 return 0;
836 static void pci_restore_pcie_state(struct pci_dev *dev)
838 int i = 0, pos;
839 struct pci_cap_saved_state *save_state;
840 u16 *cap;
841 u16 flags;
843 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
844 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
845 if (!save_state || pos <= 0)
846 return;
847 cap = (u16 *)&save_state->data[0];
849 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
851 if (pcie_cap_has_devctl(dev->pcie_type, flags))
852 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
853 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
854 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
855 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
856 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
857 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
858 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
859 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
860 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
861 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
862 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
863 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
864 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
868 static int pci_save_pcix_state(struct pci_dev *dev)
870 int pos;
871 struct pci_cap_saved_state *save_state;
873 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
874 if (pos <= 0)
875 return 0;
877 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
878 if (!save_state) {
879 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
880 return -ENOMEM;
883 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
885 return 0;
888 static void pci_restore_pcix_state(struct pci_dev *dev)
890 int i = 0, pos;
891 struct pci_cap_saved_state *save_state;
892 u16 *cap;
894 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
895 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
896 if (!save_state || pos <= 0)
897 return;
898 cap = (u16 *)&save_state->data[0];
900 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
905 * pci_save_state - save the PCI configuration space of a device before suspending
906 * @dev: - PCI device that we're dealing with
909 pci_save_state(struct pci_dev *dev)
911 int i;
912 /* XXX: 100% dword access ok here? */
913 for (i = 0; i < 16; i++)
914 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
915 dev->state_saved = true;
916 if ((i = pci_save_pcie_state(dev)) != 0)
917 return i;
918 if ((i = pci_save_pcix_state(dev)) != 0)
919 return i;
920 return 0;
923 /**
924 * pci_restore_state - Restore the saved state of a PCI device
925 * @dev: - PCI device that we're dealing with
927 int
928 pci_restore_state(struct pci_dev *dev)
930 int i;
931 u32 val;
933 if (!dev->state_saved)
934 return 0;
936 /* PCI Express register must be restored first */
937 pci_restore_pcie_state(dev);
940 * The Base Address register should be programmed before the command
941 * register(s)
943 for (i = 15; i >= 0; i--) {
944 pci_read_config_dword(dev, i * 4, &val);
945 if (val != dev->saved_config_space[i]) {
946 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
947 "space at offset %#x (was %#x, writing %#x)\n",
948 i, val, (int)dev->saved_config_space[i]);
949 pci_write_config_dword(dev,i * 4,
950 dev->saved_config_space[i]);
953 pci_restore_pcix_state(dev);
954 pci_restore_msi_state(dev);
955 pci_restore_iov_state(dev);
957 dev->state_saved = false;
959 return 0;
962 static int do_pci_enable_device(struct pci_dev *dev, int bars)
964 int err;
966 err = pci_set_power_state(dev, PCI_D0);
967 if (err < 0 && err != -EIO)
968 return err;
969 err = pcibios_enable_device(dev, bars);
970 if (err < 0)
971 return err;
972 pci_fixup_device(pci_fixup_enable, dev);
974 return 0;
978 * pci_reenable_device - Resume abandoned device
979 * @dev: PCI device to be resumed
981 * Note this function is a backend of pci_default_resume and is not supposed
982 * to be called by normal code, write proper resume handler and use it instead.
984 int pci_reenable_device(struct pci_dev *dev)
986 if (pci_is_enabled(dev))
987 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
988 return 0;
991 static int __pci_enable_device_flags(struct pci_dev *dev,
992 resource_size_t flags)
994 int err;
995 int i, bars = 0;
997 if (atomic_add_return(1, &dev->enable_cnt) > 1)
998 return 0; /* already enabled */
1000 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1001 if (dev->resource[i].flags & flags)
1002 bars |= (1 << i);
1004 err = do_pci_enable_device(dev, bars);
1005 if (err < 0)
1006 atomic_dec(&dev->enable_cnt);
1007 return err;
1011 * pci_enable_device_io - Initialize a device for use with IO space
1012 * @dev: PCI device to be initialized
1014 * Initialize device before it's used by a driver. Ask low-level code
1015 * to enable I/O resources. Wake up the device if it was suspended.
1016 * Beware, this function can fail.
1018 int pci_enable_device_io(struct pci_dev *dev)
1020 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1024 * pci_enable_device_mem - Initialize a device for use with Memory space
1025 * @dev: PCI device to be initialized
1027 * Initialize device before it's used by a driver. Ask low-level code
1028 * to enable Memory resources. Wake up the device if it was suspended.
1029 * Beware, this function can fail.
1031 int pci_enable_device_mem(struct pci_dev *dev)
1033 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1037 * pci_enable_device - Initialize device before it's used by a driver.
1038 * @dev: PCI device to be initialized
1040 * Initialize device before it's used by a driver. Ask low-level code
1041 * to enable I/O and memory. Wake up the device if it was suspended.
1042 * Beware, this function can fail.
1044 * Note we don't actually enable the device many times if we call
1045 * this function repeatedly (we just increment the count).
1047 int pci_enable_device(struct pci_dev *dev)
1049 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1053 * Managed PCI resources. This manages device on/off, intx/msi/msix
1054 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1055 * there's no need to track it separately. pci_devres is initialized
1056 * when a device is enabled using managed PCI device enable interface.
1058 struct pci_devres {
1059 unsigned int enabled:1;
1060 unsigned int pinned:1;
1061 unsigned int orig_intx:1;
1062 unsigned int restore_intx:1;
1063 u32 region_mask;
1066 static void pcim_release(struct device *gendev, void *res)
1068 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1069 struct pci_devres *this = res;
1070 int i;
1072 if (dev->msi_enabled)
1073 pci_disable_msi(dev);
1074 if (dev->msix_enabled)
1075 pci_disable_msix(dev);
1077 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1078 if (this->region_mask & (1 << i))
1079 pci_release_region(dev, i);
1081 if (this->restore_intx)
1082 pci_intx(dev, this->orig_intx);
1084 if (this->enabled && !this->pinned)
1085 pci_disable_device(dev);
1088 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1090 struct pci_devres *dr, *new_dr;
1092 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1093 if (dr)
1094 return dr;
1096 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1097 if (!new_dr)
1098 return NULL;
1099 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1102 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1104 if (pci_is_managed(pdev))
1105 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1106 return NULL;
1110 * pcim_enable_device - Managed pci_enable_device()
1111 * @pdev: PCI device to be initialized
1113 * Managed pci_enable_device().
1115 int pcim_enable_device(struct pci_dev *pdev)
1117 struct pci_devres *dr;
1118 int rc;
1120 dr = get_pci_dr(pdev);
1121 if (unlikely(!dr))
1122 return -ENOMEM;
1123 if (dr->enabled)
1124 return 0;
1126 rc = pci_enable_device(pdev);
1127 if (!rc) {
1128 pdev->is_managed = 1;
1129 dr->enabled = 1;
1131 return rc;
1135 * pcim_pin_device - Pin managed PCI device
1136 * @pdev: PCI device to pin
1138 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1139 * driver detach. @pdev must have been enabled with
1140 * pcim_enable_device().
1142 void pcim_pin_device(struct pci_dev *pdev)
1144 struct pci_devres *dr;
1146 dr = find_pci_dr(pdev);
1147 WARN_ON(!dr || !dr->enabled);
1148 if (dr)
1149 dr->pinned = 1;
1153 * pcibios_disable_device - disable arch specific PCI resources for device dev
1154 * @dev: the PCI device to disable
1156 * Disables architecture specific PCI resources for the device. This
1157 * is the default implementation. Architecture implementations can
1158 * override this.
1160 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1162 static void do_pci_disable_device(struct pci_dev *dev)
1164 u16 pci_command;
1166 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1167 if (pci_command & PCI_COMMAND_MASTER) {
1168 pci_command &= ~PCI_COMMAND_MASTER;
1169 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1172 pcibios_disable_device(dev);
1176 * pci_disable_enabled_device - Disable device without updating enable_cnt
1177 * @dev: PCI device to disable
1179 * NOTE: This function is a backend of PCI power management routines and is
1180 * not supposed to be called drivers.
1182 void pci_disable_enabled_device(struct pci_dev *dev)
1184 if (pci_is_enabled(dev))
1185 do_pci_disable_device(dev);
1189 * pci_disable_device - Disable PCI device after use
1190 * @dev: PCI device to be disabled
1192 * Signal to the system that the PCI device is not in use by the system
1193 * anymore. This only involves disabling PCI bus-mastering, if active.
1195 * Note we don't actually disable the device until all callers of
1196 * pci_device_enable() have called pci_device_disable().
1198 void
1199 pci_disable_device(struct pci_dev *dev)
1201 struct pci_devres *dr;
1203 dr = find_pci_dr(dev);
1204 if (dr)
1205 dr->enabled = 0;
1207 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1208 return;
1210 do_pci_disable_device(dev);
1212 dev->is_busmaster = 0;
1216 * pcibios_set_pcie_reset_state - set reset state for device dev
1217 * @dev: the PCIe device reset
1218 * @state: Reset state to enter into
1221 * Sets the PCIe reset state for the device. This is the default
1222 * implementation. Architecture implementations can override this.
1224 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1225 enum pcie_reset_state state)
1227 return -EINVAL;
1231 * pci_set_pcie_reset_state - set reset state for device dev
1232 * @dev: the PCIe device reset
1233 * @state: Reset state to enter into
1236 * Sets the PCI reset state for the device.
1238 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1240 return pcibios_set_pcie_reset_state(dev, state);
1244 * pci_check_pme_status - Check if given device has generated PME.
1245 * @dev: Device to check.
1247 * Check the PME status of the device and if set, clear it and clear PME enable
1248 * (if set). Return 'true' if PME status and PME enable were both set or
1249 * 'false' otherwise.
1251 bool pci_check_pme_status(struct pci_dev *dev)
1253 int pmcsr_pos;
1254 u16 pmcsr;
1255 bool ret = false;
1257 if (!dev->pm_cap)
1258 return false;
1260 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1261 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1262 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1263 return false;
1265 /* Clear PME status. */
1266 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1267 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1268 /* Disable PME to avoid interrupt flood. */
1269 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1270 ret = true;
1273 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1275 return ret;
1279 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1280 * @dev: Device to handle.
1281 * @ign: Ignored.
1283 * Check if @dev has generated PME and queue a resume request for it in that
1284 * case.
1286 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1288 if (pci_check_pme_status(dev))
1289 pm_request_resume(&dev->dev);
1290 return 0;
1294 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1295 * @bus: Top bus of the subtree to walk.
1297 void pci_pme_wakeup_bus(struct pci_bus *bus)
1299 if (bus)
1300 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1304 * pci_pme_capable - check the capability of PCI device to generate PME#
1305 * @dev: PCI device to handle.
1306 * @state: PCI state from which device will issue PME#.
1308 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1310 if (!dev->pm_cap)
1311 return false;
1313 return !!(dev->pme_support & (1 << state));
1317 * pci_pme_active - enable or disable PCI device's PME# function
1318 * @dev: PCI device to handle.
1319 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1321 * The caller must verify that the device is capable of generating PME# before
1322 * calling this function with @enable equal to 'true'.
1324 void pci_pme_active(struct pci_dev *dev, bool enable)
1326 u16 pmcsr;
1328 if (!dev->pm_cap)
1329 return;
1331 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1332 /* Clear PME_Status by writing 1 to it and enable PME# */
1333 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1334 if (!enable)
1335 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1337 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1339 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1340 enable ? "enabled" : "disabled");
1344 * __pci_enable_wake - enable PCI device as wakeup event source
1345 * @dev: PCI device affected
1346 * @state: PCI state from which device will issue wakeup events
1347 * @runtime: True if the events are to be generated at run time
1348 * @enable: True to enable event generation; false to disable
1350 * This enables the device as a wakeup event source, or disables it.
1351 * When such events involves platform-specific hooks, those hooks are
1352 * called automatically by this routine.
1354 * Devices with legacy power management (no standard PCI PM capabilities)
1355 * always require such platform hooks.
1357 * RETURN VALUE:
1358 * 0 is returned on success
1359 * -EINVAL is returned if device is not supposed to wake up the system
1360 * Error code depending on the platform is returned if both the platform and
1361 * the native mechanism fail to enable the generation of wake-up events
1363 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1364 bool runtime, bool enable)
1366 int ret = 0;
1368 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1369 return -EINVAL;
1371 /* Don't do the same thing twice in a row for one device. */
1372 if (!!enable == !!dev->wakeup_prepared)
1373 return 0;
1376 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1377 * Anderson we should be doing PME# wake enable followed by ACPI wake
1378 * enable. To disable wake-up we call the platform first, for symmetry.
1381 if (enable) {
1382 int error;
1384 if (pci_pme_capable(dev, state))
1385 pci_pme_active(dev, true);
1386 else
1387 ret = 1;
1388 error = runtime ? platform_pci_run_wake(dev, true) :
1389 platform_pci_sleep_wake(dev, true);
1390 if (ret)
1391 ret = error;
1392 if (!ret)
1393 dev->wakeup_prepared = true;
1394 } else {
1395 if (runtime)
1396 platform_pci_run_wake(dev, false);
1397 else
1398 platform_pci_sleep_wake(dev, false);
1399 pci_pme_active(dev, false);
1400 dev->wakeup_prepared = false;
1403 return ret;
1405 EXPORT_SYMBOL(__pci_enable_wake);
1408 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1409 * @dev: PCI device to prepare
1410 * @enable: True to enable wake-up event generation; false to disable
1412 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1413 * and this function allows them to set that up cleanly - pci_enable_wake()
1414 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1415 * ordering constraints.
1417 * This function only returns error code if the device is not capable of
1418 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1419 * enable wake-up power for it.
1421 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1423 return pci_pme_capable(dev, PCI_D3cold) ?
1424 pci_enable_wake(dev, PCI_D3cold, enable) :
1425 pci_enable_wake(dev, PCI_D3hot, enable);
1429 * pci_target_state - find an appropriate low power state for a given PCI dev
1430 * @dev: PCI device
1432 * Use underlying platform code to find a supported low power state for @dev.
1433 * If the platform can't manage @dev, return the deepest state from which it
1434 * can generate wake events, based on any available PME info.
1436 pci_power_t pci_target_state(struct pci_dev *dev)
1438 pci_power_t target_state = PCI_D3hot;
1440 if (platform_pci_power_manageable(dev)) {
1442 * Call the platform to choose the target state of the device
1443 * and enable wake-up from this state if supported.
1445 pci_power_t state = platform_pci_choose_state(dev);
1447 switch (state) {
1448 case PCI_POWER_ERROR:
1449 case PCI_UNKNOWN:
1450 break;
1451 case PCI_D1:
1452 case PCI_D2:
1453 if (pci_no_d1d2(dev))
1454 break;
1455 default:
1456 target_state = state;
1458 } else if (!dev->pm_cap) {
1459 target_state = PCI_D0;
1460 } else if (device_may_wakeup(&dev->dev)) {
1462 * Find the deepest state from which the device can generate
1463 * wake-up events, make it the target state and enable device
1464 * to generate PME#.
1466 if (dev->pme_support) {
1467 while (target_state
1468 && !(dev->pme_support & (1 << target_state)))
1469 target_state--;
1473 return target_state;
1477 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1478 * @dev: Device to handle.
1480 * Choose the power state appropriate for the device depending on whether
1481 * it can wake up the system and/or is power manageable by the platform
1482 * (PCI_D3hot is the default) and put the device into that state.
1484 int pci_prepare_to_sleep(struct pci_dev *dev)
1486 pci_power_t target_state = pci_target_state(dev);
1487 int error;
1489 if (target_state == PCI_POWER_ERROR)
1490 return -EIO;
1492 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1494 error = pci_set_power_state(dev, target_state);
1496 if (error)
1497 pci_enable_wake(dev, target_state, false);
1499 return error;
1503 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1504 * @dev: Device to handle.
1506 * Disable device's sytem wake-up capability and put it into D0.
1508 int pci_back_from_sleep(struct pci_dev *dev)
1510 pci_enable_wake(dev, PCI_D0, false);
1511 return pci_set_power_state(dev, PCI_D0);
1515 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1516 * @dev: PCI device being suspended.
1518 * Prepare @dev to generate wake-up events at run time and put it into a low
1519 * power state.
1521 int pci_finish_runtime_suspend(struct pci_dev *dev)
1523 pci_power_t target_state = pci_target_state(dev);
1524 int error;
1526 if (target_state == PCI_POWER_ERROR)
1527 return -EIO;
1529 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1531 error = pci_set_power_state(dev, target_state);
1533 if (error)
1534 __pci_enable_wake(dev, target_state, true, false);
1536 return error;
1540 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1541 * @dev: Device to check.
1543 * Return true if the device itself is cabable of generating wake-up events
1544 * (through the platform or using the native PCIe PME) or if the device supports
1545 * PME and one of its upstream bridges can generate wake-up events.
1547 bool pci_dev_run_wake(struct pci_dev *dev)
1549 struct pci_bus *bus = dev->bus;
1551 if (device_run_wake(&dev->dev))
1552 return true;
1554 if (!dev->pme_support)
1555 return false;
1557 while (bus->parent) {
1558 struct pci_dev *bridge = bus->self;
1560 if (device_run_wake(&bridge->dev))
1561 return true;
1563 bus = bus->parent;
1566 /* We have reached the root bus. */
1567 if (bus->bridge)
1568 return device_run_wake(bus->bridge);
1570 return false;
1572 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1575 * pci_pm_init - Initialize PM functions of given PCI device
1576 * @dev: PCI device to handle.
1578 void pci_pm_init(struct pci_dev *dev)
1580 int pm;
1581 u16 pmc;
1583 pm_runtime_forbid(&dev->dev);
1584 device_enable_async_suspend(&dev->dev);
1585 dev->wakeup_prepared = false;
1587 dev->pm_cap = 0;
1589 /* find PCI PM capability in list */
1590 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1591 if (!pm)
1592 return;
1593 /* Check device's ability to generate PME# */
1594 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1596 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1597 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1598 pmc & PCI_PM_CAP_VER_MASK);
1599 return;
1602 dev->pm_cap = pm;
1603 dev->d3_delay = PCI_PM_D3_WAIT;
1605 dev->d1_support = false;
1606 dev->d2_support = false;
1607 if (!pci_no_d1d2(dev)) {
1608 if (pmc & PCI_PM_CAP_D1)
1609 dev->d1_support = true;
1610 if (pmc & PCI_PM_CAP_D2)
1611 dev->d2_support = true;
1613 if (dev->d1_support || dev->d2_support)
1614 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1615 dev->d1_support ? " D1" : "",
1616 dev->d2_support ? " D2" : "");
1619 pmc &= PCI_PM_CAP_PME_MASK;
1620 if (pmc) {
1621 dev_printk(KERN_DEBUG, &dev->dev,
1622 "PME# supported from%s%s%s%s%s\n",
1623 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1624 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1625 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1626 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1627 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1628 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1630 * Make device's PM flags reflect the wake-up capability, but
1631 * let the user space enable it to wake up the system as needed.
1633 device_set_wakeup_capable(&dev->dev, true);
1634 device_set_wakeup_enable(&dev->dev, false);
1635 /* Disable the PME# generation functionality */
1636 pci_pme_active(dev, false);
1637 } else {
1638 dev->pme_support = 0;
1643 * platform_pci_wakeup_init - init platform wakeup if present
1644 * @dev: PCI device
1646 * Some devices don't have PCI PM caps but can still generate wakeup
1647 * events through platform methods (like ACPI events). If @dev supports
1648 * platform wakeup events, set the device flag to indicate as much. This
1649 * may be redundant if the device also supports PCI PM caps, but double
1650 * initialization should be safe in that case.
1652 void platform_pci_wakeup_init(struct pci_dev *dev)
1654 if (!platform_pci_can_wakeup(dev))
1655 return;
1657 device_set_wakeup_capable(&dev->dev, true);
1658 device_set_wakeup_enable(&dev->dev, false);
1659 platform_pci_sleep_wake(dev, false);
1663 * pci_add_save_buffer - allocate buffer for saving given capability registers
1664 * @dev: the PCI device
1665 * @cap: the capability to allocate the buffer for
1666 * @size: requested size of the buffer
1668 static int pci_add_cap_save_buffer(
1669 struct pci_dev *dev, char cap, unsigned int size)
1671 int pos;
1672 struct pci_cap_saved_state *save_state;
1674 pos = pci_find_capability(dev, cap);
1675 if (pos <= 0)
1676 return 0;
1678 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1679 if (!save_state)
1680 return -ENOMEM;
1682 save_state->cap_nr = cap;
1683 pci_add_saved_cap(dev, save_state);
1685 return 0;
1689 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1690 * @dev: the PCI device
1692 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1694 int error;
1696 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1697 PCI_EXP_SAVE_REGS * sizeof(u16));
1698 if (error)
1699 dev_err(&dev->dev,
1700 "unable to preallocate PCI Express save buffer\n");
1702 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1703 if (error)
1704 dev_err(&dev->dev,
1705 "unable to preallocate PCI-X save buffer\n");
1709 * pci_enable_ari - enable ARI forwarding if hardware support it
1710 * @dev: the PCI device
1712 void pci_enable_ari(struct pci_dev *dev)
1714 int pos;
1715 u32 cap;
1716 u16 ctrl;
1717 struct pci_dev *bridge;
1719 if (!pci_is_pcie(dev) || dev->devfn)
1720 return;
1722 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1723 if (!pos)
1724 return;
1726 bridge = dev->bus->self;
1727 if (!bridge || !pci_is_pcie(bridge))
1728 return;
1730 pos = pci_pcie_cap(bridge);
1731 if (!pos)
1732 return;
1734 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1735 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1736 return;
1738 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1739 ctrl |= PCI_EXP_DEVCTL2_ARI;
1740 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1742 bridge->ari_enabled = 1;
1745 static int pci_acs_enable;
1748 * pci_request_acs - ask for ACS to be enabled if supported
1750 void pci_request_acs(void)
1752 pci_acs_enable = 1;
1756 * pci_enable_acs - enable ACS if hardware support it
1757 * @dev: the PCI device
1759 void pci_enable_acs(struct pci_dev *dev)
1761 int pos;
1762 u16 cap;
1763 u16 ctrl;
1765 if (!pci_acs_enable)
1766 return;
1768 if (!pci_is_pcie(dev))
1769 return;
1771 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1772 if (!pos)
1773 return;
1775 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1776 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1778 /* Source Validation */
1779 ctrl |= (cap & PCI_ACS_SV);
1781 /* P2P Request Redirect */
1782 ctrl |= (cap & PCI_ACS_RR);
1784 /* P2P Completion Redirect */
1785 ctrl |= (cap & PCI_ACS_CR);
1787 /* Upstream Forwarding */
1788 ctrl |= (cap & PCI_ACS_UF);
1790 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1794 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1795 * @dev: the PCI device
1796 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1798 * Perform INTx swizzling for a device behind one level of bridge. This is
1799 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1800 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1801 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1802 * the PCI Express Base Specification, Revision 2.1)
1804 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1806 int slot;
1808 if (pci_ari_enabled(dev->bus))
1809 slot = 0;
1810 else
1811 slot = PCI_SLOT(dev->devfn);
1813 return (((pin - 1) + slot) % 4) + 1;
1817 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1819 u8 pin;
1821 pin = dev->pin;
1822 if (!pin)
1823 return -1;
1825 while (!pci_is_root_bus(dev->bus)) {
1826 pin = pci_swizzle_interrupt_pin(dev, pin);
1827 dev = dev->bus->self;
1829 *bridge = dev;
1830 return pin;
1834 * pci_common_swizzle - swizzle INTx all the way to root bridge
1835 * @dev: the PCI device
1836 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1838 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1839 * bridges all the way up to a PCI root bus.
1841 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1843 u8 pin = *pinp;
1845 while (!pci_is_root_bus(dev->bus)) {
1846 pin = pci_swizzle_interrupt_pin(dev, pin);
1847 dev = dev->bus->self;
1849 *pinp = pin;
1850 return PCI_SLOT(dev->devfn);
1854 * pci_release_region - Release a PCI bar
1855 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1856 * @bar: BAR to release
1858 * Releases the PCI I/O and memory resources previously reserved by a
1859 * successful call to pci_request_region. Call this function only
1860 * after all use of the PCI regions has ceased.
1862 void pci_release_region(struct pci_dev *pdev, int bar)
1864 struct pci_devres *dr;
1866 if (pci_resource_len(pdev, bar) == 0)
1867 return;
1868 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1869 release_region(pci_resource_start(pdev, bar),
1870 pci_resource_len(pdev, bar));
1871 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1872 release_mem_region(pci_resource_start(pdev, bar),
1873 pci_resource_len(pdev, bar));
1875 dr = find_pci_dr(pdev);
1876 if (dr)
1877 dr->region_mask &= ~(1 << bar);
1881 * __pci_request_region - Reserved PCI I/O and memory resource
1882 * @pdev: PCI device whose resources are to be reserved
1883 * @bar: BAR to be reserved
1884 * @res_name: Name to be associated with resource.
1885 * @exclusive: whether the region access is exclusive or not
1887 * Mark the PCI region associated with PCI device @pdev BR @bar as
1888 * being reserved by owner @res_name. Do not access any
1889 * address inside the PCI regions unless this call returns
1890 * successfully.
1892 * If @exclusive is set, then the region is marked so that userspace
1893 * is explicitly not allowed to map the resource via /dev/mem or
1894 * sysfs MMIO access.
1896 * Returns 0 on success, or %EBUSY on error. A warning
1897 * message is also printed on failure.
1899 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1900 int exclusive)
1902 struct pci_devres *dr;
1904 if (pci_resource_len(pdev, bar) == 0)
1905 return 0;
1907 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1908 if (!request_region(pci_resource_start(pdev, bar),
1909 pci_resource_len(pdev, bar), res_name))
1910 goto err_out;
1912 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1913 if (!__request_mem_region(pci_resource_start(pdev, bar),
1914 pci_resource_len(pdev, bar), res_name,
1915 exclusive))
1916 goto err_out;
1919 dr = find_pci_dr(pdev);
1920 if (dr)
1921 dr->region_mask |= 1 << bar;
1923 return 0;
1925 err_out:
1926 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1927 &pdev->resource[bar]);
1928 return -EBUSY;
1932 * pci_request_region - Reserve PCI I/O and memory resource
1933 * @pdev: PCI device whose resources are to be reserved
1934 * @bar: BAR to be reserved
1935 * @res_name: Name to be associated with resource
1937 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1938 * being reserved by owner @res_name. Do not access any
1939 * address inside the PCI regions unless this call returns
1940 * successfully.
1942 * Returns 0 on success, or %EBUSY on error. A warning
1943 * message is also printed on failure.
1945 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1947 return __pci_request_region(pdev, bar, res_name, 0);
1951 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1952 * @pdev: PCI device whose resources are to be reserved
1953 * @bar: BAR to be reserved
1954 * @res_name: Name to be associated with resource.
1956 * Mark the PCI region associated with PCI device @pdev BR @bar as
1957 * being reserved by owner @res_name. Do not access any
1958 * address inside the PCI regions unless this call returns
1959 * successfully.
1961 * Returns 0 on success, or %EBUSY on error. A warning
1962 * message is also printed on failure.
1964 * The key difference that _exclusive makes it that userspace is
1965 * explicitly not allowed to map the resource via /dev/mem or
1966 * sysfs.
1968 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1970 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1973 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1974 * @pdev: PCI device whose resources were previously reserved
1975 * @bars: Bitmask of BARs to be released
1977 * Release selected PCI I/O and memory resources previously reserved.
1978 * Call this function only after all use of the PCI regions has ceased.
1980 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1982 int i;
1984 for (i = 0; i < 6; i++)
1985 if (bars & (1 << i))
1986 pci_release_region(pdev, i);
1989 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1990 const char *res_name, int excl)
1992 int i;
1994 for (i = 0; i < 6; i++)
1995 if (bars & (1 << i))
1996 if (__pci_request_region(pdev, i, res_name, excl))
1997 goto err_out;
1998 return 0;
2000 err_out:
2001 while(--i >= 0)
2002 if (bars & (1 << i))
2003 pci_release_region(pdev, i);
2005 return -EBUSY;
2010 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2011 * @pdev: PCI device whose resources are to be reserved
2012 * @bars: Bitmask of BARs to be requested
2013 * @res_name: Name to be associated with resource
2015 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2016 const char *res_name)
2018 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2021 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2022 int bars, const char *res_name)
2024 return __pci_request_selected_regions(pdev, bars, res_name,
2025 IORESOURCE_EXCLUSIVE);
2029 * pci_release_regions - Release reserved PCI I/O and memory resources
2030 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2032 * Releases all PCI I/O and memory resources previously reserved by a
2033 * successful call to pci_request_regions. Call this function only
2034 * after all use of the PCI regions has ceased.
2037 void pci_release_regions(struct pci_dev *pdev)
2039 pci_release_selected_regions(pdev, (1 << 6) - 1);
2043 * pci_request_regions - Reserved PCI I/O and memory resources
2044 * @pdev: PCI device whose resources are to be reserved
2045 * @res_name: Name to be associated with resource.
2047 * Mark all PCI regions associated with PCI device @pdev as
2048 * being reserved by owner @res_name. Do not access any
2049 * address inside the PCI regions unless this call returns
2050 * successfully.
2052 * Returns 0 on success, or %EBUSY on error. A warning
2053 * message is also printed on failure.
2055 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2057 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2061 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2062 * @pdev: PCI device whose resources are to be reserved
2063 * @res_name: Name to be associated with resource.
2065 * Mark all PCI regions associated with PCI device @pdev as
2066 * being reserved by owner @res_name. Do not access any
2067 * address inside the PCI regions unless this call returns
2068 * successfully.
2070 * pci_request_regions_exclusive() will mark the region so that
2071 * /dev/mem and the sysfs MMIO access will not be allowed.
2073 * Returns 0 on success, or %EBUSY on error. A warning
2074 * message is also printed on failure.
2076 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2078 return pci_request_selected_regions_exclusive(pdev,
2079 ((1 << 6) - 1), res_name);
2082 static void __pci_set_master(struct pci_dev *dev, bool enable)
2084 u16 old_cmd, cmd;
2086 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2087 if (enable)
2088 cmd = old_cmd | PCI_COMMAND_MASTER;
2089 else
2090 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2091 if (cmd != old_cmd) {
2092 dev_dbg(&dev->dev, "%s bus mastering\n",
2093 enable ? "enabling" : "disabling");
2094 pci_write_config_word(dev, PCI_COMMAND, cmd);
2096 dev->is_busmaster = enable;
2100 * pci_set_master - enables bus-mastering for device dev
2101 * @dev: the PCI device to enable
2103 * Enables bus-mastering on the device and calls pcibios_set_master()
2104 * to do the needed arch specific settings.
2106 void pci_set_master(struct pci_dev *dev)
2108 __pci_set_master(dev, true);
2109 pcibios_set_master(dev);
2113 * pci_clear_master - disables bus-mastering for device dev
2114 * @dev: the PCI device to disable
2116 void pci_clear_master(struct pci_dev *dev)
2118 __pci_set_master(dev, false);
2122 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2123 * @dev: the PCI device for which MWI is to be enabled
2125 * Helper function for pci_set_mwi.
2126 * Originally copied from drivers/net/acenic.c.
2127 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2129 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2131 int pci_set_cacheline_size(struct pci_dev *dev)
2133 u8 cacheline_size;
2135 if (!pci_cache_line_size)
2136 return -EINVAL;
2138 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2139 equal to or multiple of the right value. */
2140 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2141 if (cacheline_size >= pci_cache_line_size &&
2142 (cacheline_size % pci_cache_line_size) == 0)
2143 return 0;
2145 /* Write the correct value. */
2146 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2147 /* Read it back. */
2148 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2149 if (cacheline_size == pci_cache_line_size)
2150 return 0;
2152 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2153 "supported\n", pci_cache_line_size << 2);
2155 return -EINVAL;
2157 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2159 #ifdef PCI_DISABLE_MWI
2160 int pci_set_mwi(struct pci_dev *dev)
2162 return 0;
2165 int pci_try_set_mwi(struct pci_dev *dev)
2167 return 0;
2170 void pci_clear_mwi(struct pci_dev *dev)
2174 #else
2177 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2178 * @dev: the PCI device for which MWI is enabled
2180 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2182 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2185 pci_set_mwi(struct pci_dev *dev)
2187 int rc;
2188 u16 cmd;
2190 rc = pci_set_cacheline_size(dev);
2191 if (rc)
2192 return rc;
2194 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2195 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2196 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2197 cmd |= PCI_COMMAND_INVALIDATE;
2198 pci_write_config_word(dev, PCI_COMMAND, cmd);
2201 return 0;
2205 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2206 * @dev: the PCI device for which MWI is enabled
2208 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2209 * Callers are not required to check the return value.
2211 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2213 int pci_try_set_mwi(struct pci_dev *dev)
2215 int rc = pci_set_mwi(dev);
2216 return rc;
2220 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2221 * @dev: the PCI device to disable
2223 * Disables PCI Memory-Write-Invalidate transaction on the device
2225 void
2226 pci_clear_mwi(struct pci_dev *dev)
2228 u16 cmd;
2230 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2231 if (cmd & PCI_COMMAND_INVALIDATE) {
2232 cmd &= ~PCI_COMMAND_INVALIDATE;
2233 pci_write_config_word(dev, PCI_COMMAND, cmd);
2236 #endif /* ! PCI_DISABLE_MWI */
2239 * pci_intx - enables/disables PCI INTx for device dev
2240 * @pdev: the PCI device to operate on
2241 * @enable: boolean: whether to enable or disable PCI INTx
2243 * Enables/disables PCI INTx for device dev
2245 void
2246 pci_intx(struct pci_dev *pdev, int enable)
2248 u16 pci_command, new;
2250 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2252 if (enable) {
2253 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2254 } else {
2255 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2258 if (new != pci_command) {
2259 struct pci_devres *dr;
2261 pci_write_config_word(pdev, PCI_COMMAND, new);
2263 dr = find_pci_dr(pdev);
2264 if (dr && !dr->restore_intx) {
2265 dr->restore_intx = 1;
2266 dr->orig_intx = !enable;
2272 * pci_msi_off - disables any msi or msix capabilities
2273 * @dev: the PCI device to operate on
2275 * If you want to use msi see pci_enable_msi and friends.
2276 * This is a lower level primitive that allows us to disable
2277 * msi operation at the device level.
2279 void pci_msi_off(struct pci_dev *dev)
2281 int pos;
2282 u16 control;
2284 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2285 if (pos) {
2286 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2287 control &= ~PCI_MSI_FLAGS_ENABLE;
2288 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2290 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2291 if (pos) {
2292 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2293 control &= ~PCI_MSIX_FLAGS_ENABLE;
2294 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2298 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2299 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2301 return dma_set_max_seg_size(&dev->dev, size);
2303 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2304 #endif
2306 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2307 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2309 return dma_set_seg_boundary(&dev->dev, mask);
2311 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2312 #endif
2314 static int pcie_flr(struct pci_dev *dev, int probe)
2316 int i;
2317 int pos;
2318 u32 cap;
2319 u16 status, control;
2321 pos = pci_pcie_cap(dev);
2322 if (!pos)
2323 return -ENOTTY;
2325 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2326 if (!(cap & PCI_EXP_DEVCAP_FLR))
2327 return -ENOTTY;
2329 if (probe)
2330 return 0;
2332 /* Wait for Transaction Pending bit clean */
2333 for (i = 0; i < 4; i++) {
2334 if (i)
2335 msleep((1 << (i - 1)) * 100);
2337 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2338 if (!(status & PCI_EXP_DEVSTA_TRPND))
2339 goto clear;
2342 dev_err(&dev->dev, "transaction is not cleared; "
2343 "proceeding with reset anyway\n");
2345 clear:
2346 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2347 control |= PCI_EXP_DEVCTL_BCR_FLR;
2348 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2350 msleep(100);
2352 return 0;
2355 static int pci_af_flr(struct pci_dev *dev, int probe)
2357 int i;
2358 int pos;
2359 u8 cap;
2360 u8 status;
2362 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2363 if (!pos)
2364 return -ENOTTY;
2366 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2367 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2368 return -ENOTTY;
2370 if (probe)
2371 return 0;
2373 /* Wait for Transaction Pending bit clean */
2374 for (i = 0; i < 4; i++) {
2375 if (i)
2376 msleep((1 << (i - 1)) * 100);
2378 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2379 if (!(status & PCI_AF_STATUS_TP))
2380 goto clear;
2383 dev_err(&dev->dev, "transaction is not cleared; "
2384 "proceeding with reset anyway\n");
2386 clear:
2387 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2388 msleep(100);
2390 return 0;
2393 static int pci_pm_reset(struct pci_dev *dev, int probe)
2395 u16 csr;
2397 if (!dev->pm_cap)
2398 return -ENOTTY;
2400 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2401 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2402 return -ENOTTY;
2404 if (probe)
2405 return 0;
2407 if (dev->current_state != PCI_D0)
2408 return -EINVAL;
2410 csr &= ~PCI_PM_CTRL_STATE_MASK;
2411 csr |= PCI_D3hot;
2412 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2413 pci_dev_d3_sleep(dev);
2415 csr &= ~PCI_PM_CTRL_STATE_MASK;
2416 csr |= PCI_D0;
2417 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2418 pci_dev_d3_sleep(dev);
2420 return 0;
2423 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2425 u16 ctrl;
2426 struct pci_dev *pdev;
2428 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2429 return -ENOTTY;
2431 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2432 if (pdev != dev)
2433 return -ENOTTY;
2435 if (probe)
2436 return 0;
2438 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2439 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2440 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2441 msleep(100);
2443 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2444 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2445 msleep(100);
2447 return 0;
2450 static int pci_dev_reset(struct pci_dev *dev, int probe)
2452 int rc;
2454 might_sleep();
2456 if (!probe) {
2457 pci_block_user_cfg_access(dev);
2458 /* block PM suspend, driver probe, etc. */
2459 device_lock(&dev->dev);
2462 rc = pci_dev_specific_reset(dev, probe);
2463 if (rc != -ENOTTY)
2464 goto done;
2466 rc = pcie_flr(dev, probe);
2467 if (rc != -ENOTTY)
2468 goto done;
2470 rc = pci_af_flr(dev, probe);
2471 if (rc != -ENOTTY)
2472 goto done;
2474 rc = pci_pm_reset(dev, probe);
2475 if (rc != -ENOTTY)
2476 goto done;
2478 rc = pci_parent_bus_reset(dev, probe);
2479 done:
2480 if (!probe) {
2481 device_unlock(&dev->dev);
2482 pci_unblock_user_cfg_access(dev);
2485 return rc;
2489 * __pci_reset_function - reset a PCI device function
2490 * @dev: PCI device to reset
2492 * Some devices allow an individual function to be reset without affecting
2493 * other functions in the same device. The PCI device must be responsive
2494 * to PCI config space in order to use this function.
2496 * The device function is presumed to be unused when this function is called.
2497 * Resetting the device will make the contents of PCI configuration space
2498 * random, so any caller of this must be prepared to reinitialise the
2499 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2500 * etc.
2502 * Returns 0 if the device function was successfully reset or negative if the
2503 * device doesn't support resetting a single function.
2505 int __pci_reset_function(struct pci_dev *dev)
2507 return pci_dev_reset(dev, 0);
2509 EXPORT_SYMBOL_GPL(__pci_reset_function);
2512 * pci_probe_reset_function - check whether the device can be safely reset
2513 * @dev: PCI device to reset
2515 * Some devices allow an individual function to be reset without affecting
2516 * other functions in the same device. The PCI device must be responsive
2517 * to PCI config space in order to use this function.
2519 * Returns 0 if the device function can be reset or negative if the
2520 * device doesn't support resetting a single function.
2522 int pci_probe_reset_function(struct pci_dev *dev)
2524 return pci_dev_reset(dev, 1);
2528 * pci_reset_function - quiesce and reset a PCI device function
2529 * @dev: PCI device to reset
2531 * Some devices allow an individual function to be reset without affecting
2532 * other functions in the same device. The PCI device must be responsive
2533 * to PCI config space in order to use this function.
2535 * This function does not just reset the PCI portion of a device, but
2536 * clears all the state associated with the device. This function differs
2537 * from __pci_reset_function in that it saves and restores device state
2538 * over the reset.
2540 * Returns 0 if the device function was successfully reset or negative if the
2541 * device doesn't support resetting a single function.
2543 int pci_reset_function(struct pci_dev *dev)
2545 int rc;
2547 rc = pci_dev_reset(dev, 1);
2548 if (rc)
2549 return rc;
2551 pci_save_state(dev);
2554 * both INTx and MSI are disabled after the Interrupt Disable bit
2555 * is set and the Bus Master bit is cleared.
2557 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2559 rc = pci_dev_reset(dev, 0);
2561 pci_restore_state(dev);
2563 return rc;
2565 EXPORT_SYMBOL_GPL(pci_reset_function);
2568 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2569 * @dev: PCI device to query
2571 * Returns mmrbc: maximum designed memory read count in bytes
2572 * or appropriate error value.
2574 int pcix_get_max_mmrbc(struct pci_dev *dev)
2576 int cap;
2577 u32 stat;
2579 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2580 if (!cap)
2581 return -EINVAL;
2583 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2584 return -EINVAL;
2586 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2588 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2591 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2592 * @dev: PCI device to query
2594 * Returns mmrbc: maximum memory read count in bytes
2595 * or appropriate error value.
2597 int pcix_get_mmrbc(struct pci_dev *dev)
2599 int cap;
2600 u16 cmd;
2602 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2603 if (!cap)
2604 return -EINVAL;
2606 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2607 return -EINVAL;
2609 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2611 EXPORT_SYMBOL(pcix_get_mmrbc);
2614 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2615 * @dev: PCI device to query
2616 * @mmrbc: maximum memory read count in bytes
2617 * valid values are 512, 1024, 2048, 4096
2619 * If possible sets maximum memory read byte count, some bridges have erratas
2620 * that prevent this.
2622 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2624 int cap;
2625 u32 stat, v, o;
2626 u16 cmd;
2628 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2629 return -EINVAL;
2631 v = ffs(mmrbc) - 10;
2633 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2634 if (!cap)
2635 return -EINVAL;
2637 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2638 return -EINVAL;
2640 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2641 return -E2BIG;
2643 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2644 return -EINVAL;
2646 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2647 if (o != v) {
2648 if (v > o && dev->bus &&
2649 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2650 return -EIO;
2652 cmd &= ~PCI_X_CMD_MAX_READ;
2653 cmd |= v << 2;
2654 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2655 return -EIO;
2657 return 0;
2659 EXPORT_SYMBOL(pcix_set_mmrbc);
2662 * pcie_get_readrq - get PCI Express read request size
2663 * @dev: PCI device to query
2665 * Returns maximum memory read request in bytes
2666 * or appropriate error value.
2668 int pcie_get_readrq(struct pci_dev *dev)
2670 int ret, cap;
2671 u16 ctl;
2673 cap = pci_pcie_cap(dev);
2674 if (!cap)
2675 return -EINVAL;
2677 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2678 if (!ret)
2679 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2681 return ret;
2683 EXPORT_SYMBOL(pcie_get_readrq);
2686 * pcie_set_readrq - set PCI Express maximum memory read request
2687 * @dev: PCI device to query
2688 * @rq: maximum memory read count in bytes
2689 * valid values are 128, 256, 512, 1024, 2048, 4096
2691 * If possible sets maximum read byte count
2693 int pcie_set_readrq(struct pci_dev *dev, int rq)
2695 int cap, err = -EINVAL;
2696 u16 ctl, v;
2698 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2699 goto out;
2701 v = (ffs(rq) - 8) << 12;
2703 cap = pci_pcie_cap(dev);
2704 if (!cap)
2705 goto out;
2707 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2708 if (err)
2709 goto out;
2711 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2712 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2713 ctl |= v;
2714 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2717 out:
2718 return err;
2720 EXPORT_SYMBOL(pcie_set_readrq);
2723 * pci_select_bars - Make BAR mask from the type of resource
2724 * @dev: the PCI device for which BAR mask is made
2725 * @flags: resource type mask to be selected
2727 * This helper routine makes bar mask from the type of resource.
2729 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2731 int i, bars = 0;
2732 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2733 if (pci_resource_flags(dev, i) & flags)
2734 bars |= (1 << i);
2735 return bars;
2739 * pci_resource_bar - get position of the BAR associated with a resource
2740 * @dev: the PCI device
2741 * @resno: the resource number
2742 * @type: the BAR type to be filled in
2744 * Returns BAR position in config space, or 0 if the BAR is invalid.
2746 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2748 int reg;
2750 if (resno < PCI_ROM_RESOURCE) {
2751 *type = pci_bar_unknown;
2752 return PCI_BASE_ADDRESS_0 + 4 * resno;
2753 } else if (resno == PCI_ROM_RESOURCE) {
2754 *type = pci_bar_mem32;
2755 return dev->rom_base_reg;
2756 } else if (resno < PCI_BRIDGE_RESOURCES) {
2757 /* device specific resource */
2758 reg = pci_iov_resource_bar(dev, resno, type);
2759 if (reg)
2760 return reg;
2763 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2764 return 0;
2767 /* Some architectures require additional programming to enable VGA */
2768 static arch_set_vga_state_t arch_set_vga_state;
2770 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2772 arch_set_vga_state = func; /* NULL disables */
2775 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2776 unsigned int command_bits, bool change_bridge)
2778 if (arch_set_vga_state)
2779 return arch_set_vga_state(dev, decode, command_bits,
2780 change_bridge);
2781 return 0;
2785 * pci_set_vga_state - set VGA decode state on device and parents if requested
2786 * @dev: the PCI device
2787 * @decode: true = enable decoding, false = disable decoding
2788 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2789 * @change_bridge: traverse ancestors and change bridges
2791 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2792 unsigned int command_bits, bool change_bridge)
2794 struct pci_bus *bus;
2795 struct pci_dev *bridge;
2796 u16 cmd;
2797 int rc;
2799 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2801 /* ARCH specific VGA enables */
2802 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2803 if (rc)
2804 return rc;
2806 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2807 if (decode == true)
2808 cmd |= command_bits;
2809 else
2810 cmd &= ~command_bits;
2811 pci_write_config_word(dev, PCI_COMMAND, cmd);
2813 if (change_bridge == false)
2814 return 0;
2816 bus = dev->bus;
2817 while (bus) {
2818 bridge = bus->self;
2819 if (bridge) {
2820 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2821 &cmd);
2822 if (decode == true)
2823 cmd |= PCI_BRIDGE_CTL_VGA;
2824 else
2825 cmd &= ~PCI_BRIDGE_CTL_VGA;
2826 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2827 cmd);
2829 bus = bus->parent;
2831 return 0;
2834 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2835 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2836 static DEFINE_SPINLOCK(resource_alignment_lock);
2839 * pci_specified_resource_alignment - get resource alignment specified by user.
2840 * @dev: the PCI device to get
2842 * RETURNS: Resource alignment if it is specified.
2843 * Zero if it is not specified.
2845 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2847 int seg, bus, slot, func, align_order, count;
2848 resource_size_t align = 0;
2849 char *p;
2851 spin_lock(&resource_alignment_lock);
2852 p = resource_alignment_param;
2853 while (*p) {
2854 count = 0;
2855 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2856 p[count] == '@') {
2857 p += count + 1;
2858 } else {
2859 align_order = -1;
2861 if (sscanf(p, "%x:%x:%x.%x%n",
2862 &seg, &bus, &slot, &func, &count) != 4) {
2863 seg = 0;
2864 if (sscanf(p, "%x:%x.%x%n",
2865 &bus, &slot, &func, &count) != 3) {
2866 /* Invalid format */
2867 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2869 break;
2872 p += count;
2873 if (seg == pci_domain_nr(dev->bus) &&
2874 bus == dev->bus->number &&
2875 slot == PCI_SLOT(dev->devfn) &&
2876 func == PCI_FUNC(dev->devfn)) {
2877 if (align_order == -1) {
2878 align = PAGE_SIZE;
2879 } else {
2880 align = 1 << align_order;
2882 /* Found */
2883 break;
2885 if (*p != ';' && *p != ',') {
2886 /* End of param or invalid format */
2887 break;
2889 p++;
2891 spin_unlock(&resource_alignment_lock);
2892 return align;
2896 * pci_is_reassigndev - check if specified PCI is target device to reassign
2897 * @dev: the PCI device to check
2899 * RETURNS: non-zero for PCI device is a target device to reassign,
2900 * or zero is not.
2902 int pci_is_reassigndev(struct pci_dev *dev)
2904 return (pci_specified_resource_alignment(dev) != 0);
2907 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2909 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2910 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2911 spin_lock(&resource_alignment_lock);
2912 strncpy(resource_alignment_param, buf, count);
2913 resource_alignment_param[count] = '\0';
2914 spin_unlock(&resource_alignment_lock);
2915 return count;
2918 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2920 size_t count;
2921 spin_lock(&resource_alignment_lock);
2922 count = snprintf(buf, size, "%s", resource_alignment_param);
2923 spin_unlock(&resource_alignment_lock);
2924 return count;
2927 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2929 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2932 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2933 const char *buf, size_t count)
2935 return pci_set_resource_alignment_param(buf, count);
2938 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2939 pci_resource_alignment_store);
2941 static int __init pci_resource_alignment_sysfs_init(void)
2943 return bus_create_file(&pci_bus_type,
2944 &bus_attr_resource_alignment);
2947 late_initcall(pci_resource_alignment_sysfs_init);
2949 static void __devinit pci_no_domains(void)
2951 #ifdef CONFIG_PCI_DOMAINS
2952 pci_domains_supported = 0;
2953 #endif
2957 * pci_ext_cfg_enabled - can we access extended PCI config space?
2958 * @dev: The PCI device of the root bridge.
2960 * Returns 1 if we can access PCI extended config space (offsets
2961 * greater than 0xff). This is the default implementation. Architecture
2962 * implementations can override this.
2964 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2966 return 1;
2969 void __weak pci_fixup_cardbus(struct pci_bus *bus)
2972 EXPORT_SYMBOL(pci_fixup_cardbus);
2974 static int __init pci_setup(char *str)
2976 while (str) {
2977 char *k = strchr(str, ',');
2978 if (k)
2979 *k++ = 0;
2980 if (*str && (str = pcibios_setup(str)) && *str) {
2981 if (!strcmp(str, "nomsi")) {
2982 pci_no_msi();
2983 } else if (!strcmp(str, "noaer")) {
2984 pci_no_aer();
2985 } else if (!strcmp(str, "nodomains")) {
2986 pci_no_domains();
2987 } else if (!strncmp(str, "cbiosize=", 9)) {
2988 pci_cardbus_io_size = memparse(str + 9, &str);
2989 } else if (!strncmp(str, "cbmemsize=", 10)) {
2990 pci_cardbus_mem_size = memparse(str + 10, &str);
2991 } else if (!strncmp(str, "resource_alignment=", 19)) {
2992 pci_set_resource_alignment_param(str + 19,
2993 strlen(str + 19));
2994 } else if (!strncmp(str, "ecrc=", 5)) {
2995 pcie_ecrc_get_policy(str + 5);
2996 } else if (!strncmp(str, "hpiosize=", 9)) {
2997 pci_hotplug_io_size = memparse(str + 9, &str);
2998 } else if (!strncmp(str, "hpmemsize=", 10)) {
2999 pci_hotplug_mem_size = memparse(str + 10, &str);
3000 } else {
3001 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3002 str);
3005 str = k;
3007 return 0;
3009 early_param("pci", pci_setup);
3011 EXPORT_SYMBOL(pci_reenable_device);
3012 EXPORT_SYMBOL(pci_enable_device_io);
3013 EXPORT_SYMBOL(pci_enable_device_mem);
3014 EXPORT_SYMBOL(pci_enable_device);
3015 EXPORT_SYMBOL(pcim_enable_device);
3016 EXPORT_SYMBOL(pcim_pin_device);
3017 EXPORT_SYMBOL(pci_disable_device);
3018 EXPORT_SYMBOL(pci_find_capability);
3019 EXPORT_SYMBOL(pci_bus_find_capability);
3020 EXPORT_SYMBOL(pci_release_regions);
3021 EXPORT_SYMBOL(pci_request_regions);
3022 EXPORT_SYMBOL(pci_request_regions_exclusive);
3023 EXPORT_SYMBOL(pci_release_region);
3024 EXPORT_SYMBOL(pci_request_region);
3025 EXPORT_SYMBOL(pci_request_region_exclusive);
3026 EXPORT_SYMBOL(pci_release_selected_regions);
3027 EXPORT_SYMBOL(pci_request_selected_regions);
3028 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3029 EXPORT_SYMBOL(pci_set_master);
3030 EXPORT_SYMBOL(pci_clear_master);
3031 EXPORT_SYMBOL(pci_set_mwi);
3032 EXPORT_SYMBOL(pci_try_set_mwi);
3033 EXPORT_SYMBOL(pci_clear_mwi);
3034 EXPORT_SYMBOL_GPL(pci_intx);
3035 EXPORT_SYMBOL(pci_assign_resource);
3036 EXPORT_SYMBOL(pci_find_parent_resource);
3037 EXPORT_SYMBOL(pci_select_bars);
3039 EXPORT_SYMBOL(pci_set_power_state);
3040 EXPORT_SYMBOL(pci_save_state);
3041 EXPORT_SYMBOL(pci_restore_state);
3042 EXPORT_SYMBOL(pci_pme_capable);
3043 EXPORT_SYMBOL(pci_pme_active);
3044 EXPORT_SYMBOL(pci_wake_from_d3);
3045 EXPORT_SYMBOL(pci_target_state);
3046 EXPORT_SYMBOL(pci_prepare_to_sleep);
3047 EXPORT_SYMBOL(pci_back_from_sleep);
3048 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);